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128 lines
3.7 KiB
C
128 lines
3.7 KiB
C
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/*
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* Driver for Zarlink DVB-T MT352 demodulator
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*
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* Written by Holger Waechtler <holger@qanu.de>
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* and Daniel Mack <daniel@qanu.de>
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*
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* AVerMedia AVerTV DVB-T 771 support by
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* Wolfram Joost <dbox2@frokaschwei.de>
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*
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* Support for Samsung TDTC9251DH01C(M) tuner
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* Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
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* Amauri Celani <acelani@essegi.net>
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*
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* DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
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* Christopher Pascoe <c.pascoe@itee.uq.edu.au>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
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*/
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#ifndef _MT352_PRIV_
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#define _MT352_PRIV_
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#define ID_MT352 0x13
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#define msb(x) (((x) >> 8) & 0xff)
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#define lsb(x) ((x) & 0xff)
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enum mt352_reg_addr {
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STATUS_0 = 0x00,
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STATUS_1 = 0x01,
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STATUS_2 = 0x02,
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STATUS_3 = 0x03,
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STATUS_4 = 0x04,
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INTERRUPT_0 = 0x05,
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INTERRUPT_1 = 0x06,
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INTERRUPT_2 = 0x07,
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INTERRUPT_3 = 0x08,
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SNR = 0x09,
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VIT_ERR_CNT_2 = 0x0A,
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VIT_ERR_CNT_1 = 0x0B,
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VIT_ERR_CNT_0 = 0x0C,
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RS_ERR_CNT_2 = 0x0D,
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RS_ERR_CNT_1 = 0x0E,
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RS_ERR_CNT_0 = 0x0F,
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RS_UBC_1 = 0x10,
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RS_UBC_0 = 0x11,
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AGC_GAIN_3 = 0x12,
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AGC_GAIN_2 = 0x13,
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AGC_GAIN_1 = 0x14,
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AGC_GAIN_0 = 0x15,
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FREQ_OFFSET_2 = 0x17,
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FREQ_OFFSET_1 = 0x18,
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FREQ_OFFSET_0 = 0x19,
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TIMING_OFFSET_1 = 0x1A,
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TIMING_OFFSET_0 = 0x1B,
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CHAN_FREQ_1 = 0x1C,
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CHAN_FREQ_0 = 0x1D,
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TPS_RECEIVED_1 = 0x1E,
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TPS_RECEIVED_0 = 0x1F,
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TPS_CURRENT_1 = 0x20,
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TPS_CURRENT_0 = 0x21,
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TPS_CELL_ID_1 = 0x22,
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TPS_CELL_ID_0 = 0x23,
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TPS_MISC_DATA_2 = 0x24,
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TPS_MISC_DATA_1 = 0x25,
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TPS_MISC_DATA_0 = 0x26,
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RESET = 0x50,
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TPS_GIVEN_1 = 0x51,
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TPS_GIVEN_0 = 0x52,
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ACQ_CTL = 0x53,
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TRL_NOMINAL_RATE_1 = 0x54,
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TRL_NOMINAL_RATE_0 = 0x55,
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INPUT_FREQ_1 = 0x56,
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INPUT_FREQ_0 = 0x57,
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TUNER_ADDR = 0x58,
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CHAN_START_1 = 0x59,
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CHAN_START_0 = 0x5A,
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CONT_1 = 0x5B,
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CONT_0 = 0x5C,
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TUNER_GO = 0x5D,
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STATUS_EN_0 = 0x5F,
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STATUS_EN_1 = 0x60,
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INTERRUPT_EN_0 = 0x61,
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INTERRUPT_EN_1 = 0x62,
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INTERRUPT_EN_2 = 0x63,
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INTERRUPT_EN_3 = 0x64,
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AGC_TARGET = 0x67,
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AGC_CTL = 0x68,
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CAPT_RANGE = 0x75,
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SNR_SELECT_1 = 0x79,
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SNR_SELECT_0 = 0x7A,
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RS_ERR_PER_1 = 0x7C,
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RS_ERR_PER_0 = 0x7D,
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CHIP_ID = 0x7F,
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CHAN_STOP_1 = 0x80,
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CHAN_STOP_0 = 0x81,
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CHAN_STEP_1 = 0x82,
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CHAN_STEP_0 = 0x83,
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FEC_LOCK_TIME = 0x85,
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OFDM_LOCK_TIME = 0x86,
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ACQ_DELAY = 0x87,
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SCAN_CTL = 0x88,
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CLOCK_CTL = 0x89,
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CONFIG = 0x8A,
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MCLK_RATIO = 0x8B,
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GPP_CTL = 0x8C,
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ADC_CTL_1 = 0x8E,
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ADC_CTL_0 = 0x8F
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};
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/* here we assume 1/6MHz == 166.66kHz stepsize */
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#define IF_FREQUENCYx6 217 /* 6 * 36.16666666667MHz */
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#endif /* _MT352_PRIV_ */
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