Device tree aware EMAC driver
Based on BenH's earlier work, this is a new version of the EMAC driver
for the built-in ethernet found on PowerPC 4xx embedded CPUs. The
same ASIC is also found in the Axon bridge chip. This new version is
designed to work in the arch/powerpc tree, using the device tree to
probe the device, rather than the old and ugly arch/ppc OCP layer.
This driver is designed to sit alongside the old driver (that lies in
drivers/net/ibm_emac and this one in drivers/net/ibm_newemac). The
old driver is left in place to support arch/ppc until arch/ppc itself
reaches its final demise (not too long now, with luck).
This driver still has a number of things that could do with cleaning
up, but I think they can be fixed up after merging. Specifically:
- Should be adjusted to properly use the dma mapping API.
Axon needs this.
- Probe logic needs reworking, in conjuction with the general
probing code for of_platform devices. The dependencies here between
EMAC, MAL, ZMII etc. make this complicated. At present, it usually
works, because we initialize and register the sub-drivers before the
EMAC driver itself, and (being in driver code) runs after the devices
themselves have been instantiated from the device tree.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-08-23 03:56:01 +00:00
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/*
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* drivers/net/ibm_newemac/debug.c
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*
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* Driver for PowerPC 4xx on-chip ethernet controller, debug print routines.
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*
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2007-12-05 00:14:33 +00:00
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* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
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* <benh@kernel.crashing.org>
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*
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* Based on the arch/ppc version of the driver:
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*
|
Device tree aware EMAC driver
Based on BenH's earlier work, this is a new version of the EMAC driver
for the built-in ethernet found on PowerPC 4xx embedded CPUs. The
same ASIC is also found in the Axon bridge chip. This new version is
designed to work in the arch/powerpc tree, using the device tree to
probe the device, rather than the old and ugly arch/ppc OCP layer.
This driver is designed to sit alongside the old driver (that lies in
drivers/net/ibm_emac and this one in drivers/net/ibm_newemac). The
old driver is left in place to support arch/ppc until arch/ppc itself
reaches its final demise (not too long now, with luck).
This driver still has a number of things that could do with cleaning
up, but I think they can be fixed up after merging. Specifically:
- Should be adjusted to properly use the dma mapping API.
Axon needs this.
- Probe logic needs reworking, in conjuction with the general
probing code for of_platform devices. The dependencies here between
EMAC, MAL, ZMII etc. make this complicated. At present, it usually
works, because we initialize and register the sub-drivers before the
EMAC driver itself, and (being in driver code) runs after the devices
themselves have been instantiated from the device tree.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-08-23 03:56:01 +00:00
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* Copyright (c) 2004, 2005 Zultys Technologies
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/netdevice.h>
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#include <linux/sysrq.h>
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#include <asm/io.h>
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#include "core.h"
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2007-12-14 00:02:57 +00:00
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static DEFINE_SPINLOCK(emac_dbg_lock);
|
Device tree aware EMAC driver
Based on BenH's earlier work, this is a new version of the EMAC driver
for the built-in ethernet found on PowerPC 4xx embedded CPUs. The
same ASIC is also found in the Axon bridge chip. This new version is
designed to work in the arch/powerpc tree, using the device tree to
probe the device, rather than the old and ugly arch/ppc OCP layer.
This driver is designed to sit alongside the old driver (that lies in
drivers/net/ibm_emac and this one in drivers/net/ibm_newemac). The
old driver is left in place to support arch/ppc until arch/ppc itself
reaches its final demise (not too long now, with luck).
This driver still has a number of things that could do with cleaning
up, but I think they can be fixed up after merging. Specifically:
- Should be adjusted to properly use the dma mapping API.
Axon needs this.
- Probe logic needs reworking, in conjuction with the general
probing code for of_platform devices. The dependencies here between
EMAC, MAL, ZMII etc. make this complicated. At present, it usually
works, because we initialize and register the sub-drivers before the
EMAC driver itself, and (being in driver code) runs after the devices
themselves have been instantiated from the device tree.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-08-23 03:56:01 +00:00
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static void emac_desc_dump(struct emac_instance *p)
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{
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int i;
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printk("** EMAC %s TX BDs **\n"
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" tx_cnt = %d tx_slot = %d ack_slot = %d\n",
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p->ofdev->node->full_name,
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p->tx_cnt, p->tx_slot, p->ack_slot);
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for (i = 0; i < NUM_TX_BUFF / 2; ++i)
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printk
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("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
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i, p->tx_desc[i].data_ptr, p->tx_skb[i] ? 'V' : ' ',
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p->tx_desc[i].ctrl, p->tx_desc[i].data_len,
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NUM_TX_BUFF / 2 + i,
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p->tx_desc[NUM_TX_BUFF / 2 + i].data_ptr,
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p->tx_skb[NUM_TX_BUFF / 2 + i] ? 'V' : ' ',
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p->tx_desc[NUM_TX_BUFF / 2 + i].ctrl,
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p->tx_desc[NUM_TX_BUFF / 2 + i].data_len);
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printk("** EMAC %s RX BDs **\n"
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" rx_slot = %d flags = 0x%lx rx_skb_size = %d rx_sync_size = %d\n"
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" rx_sg_skb = 0x%p\n",
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p->ofdev->node->full_name,
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p->rx_slot, p->commac.flags, p->rx_skb_size,
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p->rx_sync_size, p->rx_sg_skb);
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for (i = 0; i < NUM_RX_BUFF / 2; ++i)
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printk
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("bd[%2d] 0x%08x %c 0x%04x %4u - bd[%2d] 0x%08x %c 0x%04x %4u\n",
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i, p->rx_desc[i].data_ptr, p->rx_skb[i] ? 'V' : ' ',
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p->rx_desc[i].ctrl, p->rx_desc[i].data_len,
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NUM_RX_BUFF / 2 + i,
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p->rx_desc[NUM_RX_BUFF / 2 + i].data_ptr,
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p->rx_skb[NUM_RX_BUFF / 2 + i] ? 'V' : ' ',
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p->rx_desc[NUM_RX_BUFF / 2 + i].ctrl,
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p->rx_desc[NUM_RX_BUFF / 2 + i].data_len);
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}
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static void emac_mac_dump(struct emac_instance *dev)
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{
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struct emac_regs __iomem *p = dev->emacp;
|
ibm_newemac: Parameterize EMAC Multicast Match Handling
Various instances of the EMAC core have varying: 1) number of address
match slots, 2) width of the registers for handling address match slots,
3) number of registers for handling address match slots and 4) base
offset for those registers.
As the driver stands today, it assumes that all EMACs have 4 IAHT and
GAHT 32-bit registers, starting at offset 0x30 from the register base,
with only 16-bits of each used for a total of 64 match slots.
The 405EX(r) and 460EX now use the EMAC4SYNC core rather than the EMAC4
core. This core has 8 IAHT and GAHT registers, starting at offset 0x80
from the register base, with ALL 32-bits of each used for a total of
256 match slots.
This adds a new compatible device tree entry "emac4sync" and a new,
related feature flag "EMAC_FTR_EMAC4SYNC" along with a series of macros
and inlines which supply the appropriate parameterized value based on
the presence or absence of the EMAC4SYNC feature.
The code has further been reworked where appropriate to use those macros
and inlines.
In addition, the register size passed to ioremap is now taken from the
device tree:
c4 for EMAC4SYNC cores
74 for EMAC4 cores
70 for EMAC cores
rather than sizeof (emac_regs).
Finally, the device trees have been updated with the appropriate compatible
entries and resource sizes.
This has been tested on an AMCC Haleakala board such that: 1) inbound
ICMP requests to 'haleakala.local' via MDNS from both Mac OS X 10.4.11
and Ubuntu 8.04 systems as well as 2) outbound ICMP requests from
'haleakala.local' to those same systems in the '.local' domain via MDNS
now work.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Acked-by: Jeff Garzik <jgarzik@pobox.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2008-07-07 22:03:11 +00:00
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const int xaht_regs = EMAC_XAHT_REGS(dev);
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u32 *gaht_base = emac_gaht_base(dev);
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u32 *iaht_base = emac_iaht_base(dev);
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int emac4sync = emac_has_feature(dev, EMAC_FTR_EMAC4SYNC);
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int n;
|
Device tree aware EMAC driver
Based on BenH's earlier work, this is a new version of the EMAC driver
for the built-in ethernet found on PowerPC 4xx embedded CPUs. The
same ASIC is also found in the Axon bridge chip. This new version is
designed to work in the arch/powerpc tree, using the device tree to
probe the device, rather than the old and ugly arch/ppc OCP layer.
This driver is designed to sit alongside the old driver (that lies in
drivers/net/ibm_emac and this one in drivers/net/ibm_newemac). The
old driver is left in place to support arch/ppc until arch/ppc itself
reaches its final demise (not too long now, with luck).
This driver still has a number of things that could do with cleaning
up, but I think they can be fixed up after merging. Specifically:
- Should be adjusted to properly use the dma mapping API.
Axon needs this.
- Probe logic needs reworking, in conjuction with the general
probing code for of_platform devices. The dependencies here between
EMAC, MAL, ZMII etc. make this complicated. At present, it usually
works, because we initialize and register the sub-drivers before the
EMAC driver itself, and (being in driver code) runs after the devices
themselves have been instantiated from the device tree.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-08-23 03:56:01 +00:00
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printk("** EMAC %s registers **\n"
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"MR0 = 0x%08x MR1 = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x\n"
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"RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x\n"
|
ibm_newemac: Parameterize EMAC Multicast Match Handling
Various instances of the EMAC core have varying: 1) number of address
match slots, 2) width of the registers for handling address match slots,
3) number of registers for handling address match slots and 4) base
offset for those registers.
As the driver stands today, it assumes that all EMACs have 4 IAHT and
GAHT 32-bit registers, starting at offset 0x30 from the register base,
with only 16-bits of each used for a total of 64 match slots.
The 405EX(r) and 460EX now use the EMAC4SYNC core rather than the EMAC4
core. This core has 8 IAHT and GAHT registers, starting at offset 0x80
from the register base, with ALL 32-bits of each used for a total of
256 match slots.
This adds a new compatible device tree entry "emac4sync" and a new,
related feature flag "EMAC_FTR_EMAC4SYNC" along with a series of macros
and inlines which supply the appropriate parameterized value based on
the presence or absence of the EMAC4SYNC feature.
The code has further been reworked where appropriate to use those macros
and inlines.
In addition, the register size passed to ioremap is now taken from the
device tree:
c4 for EMAC4SYNC cores
74 for EMAC4 cores
70 for EMAC cores
rather than sizeof (emac_regs).
Finally, the device trees have been updated with the appropriate compatible
entries and resource sizes.
This has been tested on an AMCC Haleakala board such that: 1) inbound
ICMP requests to 'haleakala.local' via MDNS from both Mac OS X 10.4.11
and Ubuntu 8.04 systems as well as 2) outbound ICMP requests from
'haleakala.local' to those same systems in the '.local' domain via MDNS
now work.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Acked-by: Jeff Garzik <jgarzik@pobox.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2008-07-07 22:03:11 +00:00
|
|
|
"IAR = %04x%08x VTPID = 0x%04x VTCI = 0x%04x\n",
|
Device tree aware EMAC driver
Based on BenH's earlier work, this is a new version of the EMAC driver
for the built-in ethernet found on PowerPC 4xx embedded CPUs. The
same ASIC is also found in the Axon bridge chip. This new version is
designed to work in the arch/powerpc tree, using the device tree to
probe the device, rather than the old and ugly arch/ppc OCP layer.
This driver is designed to sit alongside the old driver (that lies in
drivers/net/ibm_emac and this one in drivers/net/ibm_newemac). The
old driver is left in place to support arch/ppc until arch/ppc itself
reaches its final demise (not too long now, with luck).
This driver still has a number of things that could do with cleaning
up, but I think they can be fixed up after merging. Specifically:
- Should be adjusted to properly use the dma mapping API.
Axon needs this.
- Probe logic needs reworking, in conjuction with the general
probing code for of_platform devices. The dependencies here between
EMAC, MAL, ZMII etc. make this complicated. At present, it usually
works, because we initialize and register the sub-drivers before the
EMAC driver itself, and (being in driver code) runs after the devices
themselves have been instantiated from the device tree.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-08-23 03:56:01 +00:00
|
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|
dev->ofdev->node->full_name, in_be32(&p->mr0), in_be32(&p->mr1),
|
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|
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in_be32(&p->tmr0), in_be32(&p->tmr1),
|
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in_be32(&p->rmr), in_be32(&p->isr), in_be32(&p->iser),
|
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|
|
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in_be32(&p->iahr), in_be32(&p->ialr), in_be32(&p->vtpid),
|
ibm_newemac: Parameterize EMAC Multicast Match Handling
Various instances of the EMAC core have varying: 1) number of address
match slots, 2) width of the registers for handling address match slots,
3) number of registers for handling address match slots and 4) base
offset for those registers.
As the driver stands today, it assumes that all EMACs have 4 IAHT and
GAHT 32-bit registers, starting at offset 0x30 from the register base,
with only 16-bits of each used for a total of 64 match slots.
The 405EX(r) and 460EX now use the EMAC4SYNC core rather than the EMAC4
core. This core has 8 IAHT and GAHT registers, starting at offset 0x80
from the register base, with ALL 32-bits of each used for a total of
256 match slots.
This adds a new compatible device tree entry "emac4sync" and a new,
related feature flag "EMAC_FTR_EMAC4SYNC" along with a series of macros
and inlines which supply the appropriate parameterized value based on
the presence or absence of the EMAC4SYNC feature.
The code has further been reworked where appropriate to use those macros
and inlines.
In addition, the register size passed to ioremap is now taken from the
device tree:
c4 for EMAC4SYNC cores
74 for EMAC4 cores
70 for EMAC cores
rather than sizeof (emac_regs).
Finally, the device trees have been updated with the appropriate compatible
entries and resource sizes.
This has been tested on an AMCC Haleakala board such that: 1) inbound
ICMP requests to 'haleakala.local' via MDNS from both Mac OS X 10.4.11
and Ubuntu 8.04 systems as well as 2) outbound ICMP requests from
'haleakala.local' to those same systems in the '.local' domain via MDNS
now work.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Acked-by: Jeff Garzik <jgarzik@pobox.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2008-07-07 22:03:11 +00:00
|
|
|
in_be32(&p->vtci)
|
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);
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if (emac4sync)
|
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printk("MAR = %04x%08x MMAR = %04x%08x\n",
|
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|
|
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in_be32(&p->u0.emac4sync.mahr),
|
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|
|
|
in_be32(&p->u0.emac4sync.malr),
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|
|
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in_be32(&p->u0.emac4sync.mmahr),
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|
|
|
in_be32(&p->u0.emac4sync.mmalr)
|
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);
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for (n = 0; n < xaht_regs; n++)
|
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|
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printk("IAHT%02d = 0x%08x\n", n + 1, in_be32(iaht_base + n));
|
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|
|
|
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|
for (n = 0; n < xaht_regs; n++)
|
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|
|
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printk("GAHT%02d = 0x%08x\n", n + 1, in_be32(gaht_base + n));
|
|
|
|
|
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|
|
|
printk("LSA = %04x%08x IPGVR = 0x%04x\n"
|
|
|
|
|
"STACR = 0x%08x TRTR = 0x%08x RWMR = 0x%08x\n"
|
|
|
|
|
"OCTX = 0x%08x OCRX = 0x%08x\n",
|
Device tree aware EMAC driver
Based on BenH's earlier work, this is a new version of the EMAC driver
for the built-in ethernet found on PowerPC 4xx embedded CPUs. The
same ASIC is also found in the Axon bridge chip. This new version is
designed to work in the arch/powerpc tree, using the device tree to
probe the device, rather than the old and ugly arch/ppc OCP layer.
This driver is designed to sit alongside the old driver (that lies in
drivers/net/ibm_emac and this one in drivers/net/ibm_newemac). The
old driver is left in place to support arch/ppc until arch/ppc itself
reaches its final demise (not too long now, with luck).
This driver still has a number of things that could do with cleaning
up, but I think they can be fixed up after merging. Specifically:
- Should be adjusted to properly use the dma mapping API.
Axon needs this.
- Probe logic needs reworking, in conjuction with the general
probing code for of_platform devices. The dependencies here between
EMAC, MAL, ZMII etc. make this complicated. At present, it usually
works, because we initialize and register the sub-drivers before the
EMAC driver itself, and (being in driver code) runs after the devices
themselves have been instantiated from the device tree.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-08-23 03:56:01 +00:00
|
|
|
in_be32(&p->lsah), in_be32(&p->lsal), in_be32(&p->ipgvr),
|
|
|
|
|
in_be32(&p->stacr), in_be32(&p->trtr), in_be32(&p->rwmr),
|
ibm_newemac: Parameterize EMAC Multicast Match Handling
Various instances of the EMAC core have varying: 1) number of address
match slots, 2) width of the registers for handling address match slots,
3) number of registers for handling address match slots and 4) base
offset for those registers.
As the driver stands today, it assumes that all EMACs have 4 IAHT and
GAHT 32-bit registers, starting at offset 0x30 from the register base,
with only 16-bits of each used for a total of 64 match slots.
The 405EX(r) and 460EX now use the EMAC4SYNC core rather than the EMAC4
core. This core has 8 IAHT and GAHT registers, starting at offset 0x80
from the register base, with ALL 32-bits of each used for a total of
256 match slots.
This adds a new compatible device tree entry "emac4sync" and a new,
related feature flag "EMAC_FTR_EMAC4SYNC" along with a series of macros
and inlines which supply the appropriate parameterized value based on
the presence or absence of the EMAC4SYNC feature.
The code has further been reworked where appropriate to use those macros
and inlines.
In addition, the register size passed to ioremap is now taken from the
device tree:
c4 for EMAC4SYNC cores
74 for EMAC4 cores
70 for EMAC cores
rather than sizeof (emac_regs).
Finally, the device trees have been updated with the appropriate compatible
entries and resource sizes.
This has been tested on an AMCC Haleakala board such that: 1) inbound
ICMP requests to 'haleakala.local' via MDNS from both Mac OS X 10.4.11
and Ubuntu 8.04 systems as well as 2) outbound ICMP requests from
'haleakala.local' to those same systems in the '.local' domain via MDNS
now work.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Acked-by: Jeff Garzik <jgarzik@pobox.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2008-07-07 22:03:11 +00:00
|
|
|
in_be32(&p->octx), in_be32(&p->ocrx)
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
if (!emac4sync) {
|
|
|
|
|
printk("IPCR = 0x%08x\n",
|
|
|
|
|
in_be32(&p->u1.emac4.ipcr)
|
|
|
|
|
);
|
|
|
|
|
} else {
|
|
|
|
|
printk("REVID = 0x%08x TPC = 0x%08x\n",
|
|
|
|
|
in_be32(&p->u1.emac4sync.revid),
|
|
|
|
|
in_be32(&p->u1.emac4sync.tpc)
|
|
|
|
|
);
|
|
|
|
|
}
|
Device tree aware EMAC driver
Based on BenH's earlier work, this is a new version of the EMAC driver
for the built-in ethernet found on PowerPC 4xx embedded CPUs. The
same ASIC is also found in the Axon bridge chip. This new version is
designed to work in the arch/powerpc tree, using the device tree to
probe the device, rather than the old and ugly arch/ppc OCP layer.
This driver is designed to sit alongside the old driver (that lies in
drivers/net/ibm_emac and this one in drivers/net/ibm_newemac). The
old driver is left in place to support arch/ppc until arch/ppc itself
reaches its final demise (not too long now, with luck).
This driver still has a number of things that could do with cleaning
up, but I think they can be fixed up after merging. Specifically:
- Should be adjusted to properly use the dma mapping API.
Axon needs this.
- Probe logic needs reworking, in conjuction with the general
probing code for of_platform devices. The dependencies here between
EMAC, MAL, ZMII etc. make this complicated. At present, it usually
works, because we initialize and register the sub-drivers before the
EMAC driver itself, and (being in driver code) runs after the devices
themselves have been instantiated from the device tree.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-08-23 03:56:01 +00:00
|
|
|
|
|
|
|
|
emac_desc_dump(dev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void emac_mal_dump(struct mal_instance *mal)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
printk("** MAL %s Registers **\n"
|
|
|
|
|
"CFG = 0x%08x ESR = 0x%08x IER = 0x%08x\n"
|
|
|
|
|
"TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n"
|
|
|
|
|
"RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x\n",
|
|
|
|
|
mal->ofdev->node->full_name,
|
|
|
|
|
get_mal_dcrn(mal, MAL_CFG), get_mal_dcrn(mal, MAL_ESR),
|
|
|
|
|
get_mal_dcrn(mal, MAL_IER),
|
|
|
|
|
get_mal_dcrn(mal, MAL_TXCASR), get_mal_dcrn(mal, MAL_TXCARR),
|
|
|
|
|
get_mal_dcrn(mal, MAL_TXEOBISR), get_mal_dcrn(mal, MAL_TXDEIR),
|
|
|
|
|
get_mal_dcrn(mal, MAL_RXCASR), get_mal_dcrn(mal, MAL_RXCARR),
|
|
|
|
|
get_mal_dcrn(mal, MAL_RXEOBISR), get_mal_dcrn(mal, MAL_RXDEIR)
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
printk("TX|");
|
|
|
|
|
for (i = 0; i < mal->num_tx_chans; ++i) {
|
|
|
|
|
if (i && !(i % 4))
|
|
|
|
|
printk("\n ");
|
|
|
|
|
printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_TXCTPR(i)));
|
|
|
|
|
}
|
|
|
|
|
printk("\nRX|");
|
|
|
|
|
for (i = 0; i < mal->num_rx_chans; ++i) {
|
|
|
|
|
if (i && !(i % 4))
|
|
|
|
|
printk("\n ");
|
|
|
|
|
printk("CTP%d = 0x%08x ", i, get_mal_dcrn(mal, MAL_RXCTPR(i)));
|
|
|
|
|
}
|
|
|
|
|
printk("\n ");
|
|
|
|
|
for (i = 0; i < mal->num_rx_chans; ++i) {
|
|
|
|
|
u32 r = get_mal_dcrn(mal, MAL_RCBS(i));
|
|
|
|
|
if (i && !(i % 3))
|
|
|
|
|
printk("\n ");
|
|
|
|
|
printk("RCBS%d = 0x%08x (%d) ", i, r, r * 16);
|
|
|
|
|
}
|
|
|
|
|
printk("\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct emac_instance *__emacs[4];
|
|
|
|
|
static struct mal_instance *__mals[1];
|
|
|
|
|
|
|
|
|
|
void emac_dbg_register(struct emac_instance *dev)
|
|
|
|
|
{
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&emac_dbg_lock, flags);
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(__emacs); i++)
|
|
|
|
|
if (__emacs[i] == NULL) {
|
|
|
|
|
__emacs[i] = dev;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
spin_unlock_irqrestore(&emac_dbg_lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emac_dbg_unregister(struct emac_instance *dev)
|
|
|
|
|
{
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&emac_dbg_lock, flags);
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(__emacs); i++)
|
|
|
|
|
if (__emacs[i] == dev) {
|
|
|
|
|
__emacs[i] = NULL;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
spin_unlock_irqrestore(&emac_dbg_lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void mal_dbg_register(struct mal_instance *mal)
|
|
|
|
|
{
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&emac_dbg_lock, flags);
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(__mals); i++)
|
|
|
|
|
if (__mals[i] == NULL) {
|
|
|
|
|
__mals[i] = mal;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
spin_unlock_irqrestore(&emac_dbg_lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void mal_dbg_unregister(struct mal_instance *mal)
|
|
|
|
|
{
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&emac_dbg_lock, flags);
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(__mals); i++)
|
|
|
|
|
if (__mals[i] == mal) {
|
|
|
|
|
__mals[i] = NULL;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
spin_unlock_irqrestore(&emac_dbg_lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void emac_dbg_dump_all(void)
|
|
|
|
|
{
|
|
|
|
|
unsigned int i;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&emac_dbg_lock, flags);
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(__mals); ++i)
|
|
|
|
|
if (__mals[i])
|
|
|
|
|
emac_mal_dump(__mals[i]);
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(__emacs); ++i)
|
|
|
|
|
if (__emacs[i])
|
|
|
|
|
emac_mac_dump(__emacs[i]);
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&emac_dbg_lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_MAGIC_SYSRQ)
|
|
|
|
|
static void emac_sysrq_handler(int key, struct tty_struct *tty)
|
|
|
|
|
{
|
|
|
|
|
emac_dbg_dump_all();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct sysrq_key_op emac_sysrq_op = {
|
|
|
|
|
.handler = emac_sysrq_handler,
|
|
|
|
|
.help_msg = "emaC",
|
|
|
|
|
.action_msg = "Show EMAC(s) status",
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int __init emac_init_debug(void)
|
|
|
|
|
{
|
|
|
|
|
return register_sysrq_key('c', &emac_sysrq_op);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __exit emac_fini_debug(void)
|
|
|
|
|
{
|
|
|
|
|
unregister_sysrq_key('c', &emac_sysrq_op);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
int __init emac_init_debug(void)
|
|
|
|
|
{
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
void __exit emac_fini_debug(void)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_MAGIC_SYSRQ */
|
