2014-03-25 00:20:29 +00:00
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/*
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* Hibernation support specific for ARM
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*
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* Derived from work on ARM hibernation support by:
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*
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* Ubuntu project, hibernation support for mach-dove
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* Copyright (C) 2010 Nokia Corporation (Hiroshi Doyu)
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* Copyright (C) 2010 Texas Instruments, Inc. (Teerth Reddy et al.)
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* https://lkml.org/lkml/2010/6/18/4
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* https://lists.linux-foundation.org/pipermail/linux-pm/2010-June/027422.html
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* https://patchwork.kernel.org/patch/96442/
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*
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* Copyright (C) 2006 Rafael J. Wysocki <rjw@sisk.pl>
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/mm.h>
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#include <linux/suspend.h>
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#include <asm/system_misc.h>
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#include <asm/idmap.h>
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#include <asm/suspend.h>
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#include <asm/memory.h>
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2014-10-09 22:30:30 +00:00
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#include <asm/sections.h>
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ARM: fix broken hibernation
Normally, when a CPU wants to clear a cache line to zero in the external
L2 cache, it would generate bus cycles to write each word as it would do
with any other data access.
However, a Cortex A9 connected to a L2C-310 has a specific feature where
the CPU can detect this operation, and signal that it wants to zero an
entire cache line. This feature, known as Full Line of Zeros (FLZ),
involves a non-standard AXI signalling mechanism which only the L2C-310
can properly interpret.
There are separate enable bits in both the L2C-310 and the Cortex A9 -
the L2C-310 needs to be enabled and have the FLZ enable bit set in the
auxiliary control register before the Cortex A9 has this feature
enabled.
Unfortunately, the suspend code was not respecting this - it's not
obvious from the code:
swsusp_arch_suspend()
cpu_suspend() /* saves the Cortex A9 auxiliary control register */
arch_save_image()
soft_restart() /* turns off FLZ in Cortex A9, and disables L2C */
cpu_resume() /* restores the Cortex A9 registers, inc auxcr */
At this point, we end up with the L2C disabled, but the Cortex A9 with
FLZ enabled - which means any memset() or zeroing of a full cache line
will fail to take effect.
A similar issue exists in the resume path, but it's slightly more
complex:
swsusp_arch_suspend()
cpu_suspend() /* saves the Cortex A9 auxiliary control register */
arch_save_image() /* image with A9 auxcr saved */
...
swsusp_arch_resume()
call_with_stack()
arch_restore_image() /* restores image with A9 auxcr saved above */
soft_restart() /* turns off FLZ in Cortex A9, and disables L2C */
cpu_resume() /* restores the Cortex A9 registers, inc auxcr */
Again, here we end up with the L2C disabled, but Cortex A9 FLZ enabled.
There's no need to turn off the L2C in either of these two paths; there
are benefits from not doing so - for example, the page copies will be
faster with the L2C enabled.
Hence, fix this by providing a variant of soft_restart() which can be
used without turning the L2 cache controller off, and use it in both
of these paths to keep the L2C enabled across the respective resume
transitions.
Fixes: 8ef418c7178f ("ARM: l2c: trial at enabling some Cortex-A9 optimisations")
Reported-by: Sean Cross <xobs@kosagi.com>
Tested-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-01 15:20:39 +00:00
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#include "reboot.h"
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2014-03-25 00:20:29 +00:00
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int pfn_is_nosave(unsigned long pfn)
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{
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unsigned long nosave_begin_pfn = virt_to_pfn(&__nosave_begin);
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unsigned long nosave_end_pfn = virt_to_pfn(&__nosave_end - 1);
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return (pfn >= nosave_begin_pfn) && (pfn <= nosave_end_pfn);
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}
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void notrace save_processor_state(void)
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{
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WARN_ON(num_online_cpus() != 1);
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local_fiq_disable();
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}
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void notrace restore_processor_state(void)
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{
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local_fiq_enable();
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}
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/*
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* Snapshot kernel memory and reset the system.
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*
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* swsusp_save() is executed in the suspend finisher so that the CPU
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* context pointer and memory are part of the saved image, which is
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* required by the resume kernel image to restart execution from
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* swsusp_arch_suspend().
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*
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* soft_restart is not technically needed, but is used to get success
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* returned from cpu_suspend.
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*
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* When soft reboot completes, the hibernation snapshot is written out.
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*/
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static int notrace arch_save_image(unsigned long unused)
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{
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int ret;
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ret = swsusp_save();
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if (ret == 0)
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ARM: fix broken hibernation
Normally, when a CPU wants to clear a cache line to zero in the external
L2 cache, it would generate bus cycles to write each word as it would do
with any other data access.
However, a Cortex A9 connected to a L2C-310 has a specific feature where
the CPU can detect this operation, and signal that it wants to zero an
entire cache line. This feature, known as Full Line of Zeros (FLZ),
involves a non-standard AXI signalling mechanism which only the L2C-310
can properly interpret.
There are separate enable bits in both the L2C-310 and the Cortex A9 -
the L2C-310 needs to be enabled and have the FLZ enable bit set in the
auxiliary control register before the Cortex A9 has this feature
enabled.
Unfortunately, the suspend code was not respecting this - it's not
obvious from the code:
swsusp_arch_suspend()
cpu_suspend() /* saves the Cortex A9 auxiliary control register */
arch_save_image()
soft_restart() /* turns off FLZ in Cortex A9, and disables L2C */
cpu_resume() /* restores the Cortex A9 registers, inc auxcr */
At this point, we end up with the L2C disabled, but the Cortex A9 with
FLZ enabled - which means any memset() or zeroing of a full cache line
will fail to take effect.
A similar issue exists in the resume path, but it's slightly more
complex:
swsusp_arch_suspend()
cpu_suspend() /* saves the Cortex A9 auxiliary control register */
arch_save_image() /* image with A9 auxcr saved */
...
swsusp_arch_resume()
call_with_stack()
arch_restore_image() /* restores image with A9 auxcr saved above */
soft_restart() /* turns off FLZ in Cortex A9, and disables L2C */
cpu_resume() /* restores the Cortex A9 registers, inc auxcr */
Again, here we end up with the L2C disabled, but Cortex A9 FLZ enabled.
There's no need to turn off the L2C in either of these two paths; there
are benefits from not doing so - for example, the page copies will be
faster with the L2C enabled.
Hence, fix this by providing a variant of soft_restart() which can be
used without turning the L2 cache controller off, and use it in both
of these paths to keep the L2C enabled across the respective resume
transitions.
Fixes: 8ef418c7178f ("ARM: l2c: trial at enabling some Cortex-A9 optimisations")
Reported-by: Sean Cross <xobs@kosagi.com>
Tested-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-01 15:20:39 +00:00
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_soft_restart(virt_to_phys(cpu_resume), false);
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2014-03-25 00:20:29 +00:00
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return ret;
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}
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/*
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* Save the current CPU state before suspend / poweroff.
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*/
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int notrace swsusp_arch_suspend(void)
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{
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return cpu_suspend(0, arch_save_image);
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}
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/*
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* Restore page contents for physical pages that were in use during loading
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* hibernation image. Switch to idmap_pgd so the physical page tables
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* are overwritten with the same contents.
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*/
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static void notrace arch_restore_image(void *unused)
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{
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struct pbe *pbe;
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cpu_switch_mm(idmap_pgd, &init_mm);
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for (pbe = restore_pblist; pbe; pbe = pbe->next)
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copy_page(pbe->orig_address, pbe->address);
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ARM: fix broken hibernation
Normally, when a CPU wants to clear a cache line to zero in the external
L2 cache, it would generate bus cycles to write each word as it would do
with any other data access.
However, a Cortex A9 connected to a L2C-310 has a specific feature where
the CPU can detect this operation, and signal that it wants to zero an
entire cache line. This feature, known as Full Line of Zeros (FLZ),
involves a non-standard AXI signalling mechanism which only the L2C-310
can properly interpret.
There are separate enable bits in both the L2C-310 and the Cortex A9 -
the L2C-310 needs to be enabled and have the FLZ enable bit set in the
auxiliary control register before the Cortex A9 has this feature
enabled.
Unfortunately, the suspend code was not respecting this - it's not
obvious from the code:
swsusp_arch_suspend()
cpu_suspend() /* saves the Cortex A9 auxiliary control register */
arch_save_image()
soft_restart() /* turns off FLZ in Cortex A9, and disables L2C */
cpu_resume() /* restores the Cortex A9 registers, inc auxcr */
At this point, we end up with the L2C disabled, but the Cortex A9 with
FLZ enabled - which means any memset() or zeroing of a full cache line
will fail to take effect.
A similar issue exists in the resume path, but it's slightly more
complex:
swsusp_arch_suspend()
cpu_suspend() /* saves the Cortex A9 auxiliary control register */
arch_save_image() /* image with A9 auxcr saved */
...
swsusp_arch_resume()
call_with_stack()
arch_restore_image() /* restores image with A9 auxcr saved above */
soft_restart() /* turns off FLZ in Cortex A9, and disables L2C */
cpu_resume() /* restores the Cortex A9 registers, inc auxcr */
Again, here we end up with the L2C disabled, but Cortex A9 FLZ enabled.
There's no need to turn off the L2C in either of these two paths; there
are benefits from not doing so - for example, the page copies will be
faster with the L2C enabled.
Hence, fix this by providing a variant of soft_restart() which can be
used without turning the L2 cache controller off, and use it in both
of these paths to keep the L2C enabled across the respective resume
transitions.
Fixes: 8ef418c7178f ("ARM: l2c: trial at enabling some Cortex-A9 optimisations")
Reported-by: Sean Cross <xobs@kosagi.com>
Tested-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-04-01 15:20:39 +00:00
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_soft_restart(virt_to_phys(cpu_resume), false);
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2014-03-25 00:20:29 +00:00
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}
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static u64 resume_stack[PAGE_SIZE/2/sizeof(u64)] __nosavedata;
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/*
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* Resume from the hibernation image.
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* Due to the kernel heap / data restore, stack contents change underneath
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* and that would make function calls impossible; switch to a temporary
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* stack within the nosave region to avoid that problem.
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*/
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int swsusp_arch_resume(void)
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{
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call_with_stack(arch_restore_image, 0,
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resume_stack + ARRAY_SIZE(resume_stack));
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return 0;
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}
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