2018-07-24 12:48:32 +00:00
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// SPDX-License-Identifier: GPL-2.0
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//
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// Freescale ALSA SoC Machine driver utility
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//
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// Author: Timur Tabi <timur@freescale.com>
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//
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// Copyright 2010 Freescale Semiconductor, Inc.
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2012-03-16 08:56:40 +00:00
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2022-07-01 09:32:36 +00:00
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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2012-03-16 08:56:40 +00:00
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <sound/soc.h>
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#include "fsl_utils.h"
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/**
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* fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
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*
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* @ssi_np: pointer to the SSI device tree node
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* @name: name of the phandle pointing to the dma channel
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* @dai: ASoC DAI link pointer to be filled with platform_name
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* @dma_channel_id: dma channel id to be returned
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* @dma_id: dma id to be returned
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*
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* This function determines the dma and channel id for given SSI node. It
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* also discovers the platform_name for the ASoC DAI link.
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*/
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int fsl_asoc_get_dma_channel(struct device_node *ssi_np,
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const char *name,
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struct snd_soc_dai_link *dai,
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unsigned int *dma_channel_id,
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unsigned int *dma_id)
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{
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struct resource res;
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struct device_node *dma_channel_np, *dma_np;
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2018-02-11 21:53:20 +00:00
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const __be32 *iprop;
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2012-03-16 08:56:40 +00:00
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int ret;
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dma_channel_np = of_parse_phandle(ssi_np, name, 0);
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if (!dma_channel_np)
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return -EINVAL;
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if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) {
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of_node_put(dma_channel_np);
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return -EINVAL;
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}
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/* Determine the dev_name for the device_node. This code mimics the
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* behavior of of_device_make_bus_id(). We need this because ASoC uses
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* the dev_name() of the device to match the platform (DMA) device with
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* the CPU (SSI) device. It's all ugly and hackish, but it works (for
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* now).
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*
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* dai->platform name should already point to an allocated buffer.
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*/
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ret = of_address_to_resource(dma_channel_np, 0, &res);
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if (ret) {
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of_node_put(dma_channel_np);
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return ret;
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}
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2019-06-06 04:15:25 +00:00
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snprintf((char *)dai->platforms->name, DAI_NAME_SIZE, "%llx.%pOFn",
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2018-08-28 15:44:28 +00:00
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(unsigned long long) res.start, dma_channel_np);
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2012-03-16 08:56:40 +00:00
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iprop = of_get_property(dma_channel_np, "cell-index", NULL);
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if (!iprop) {
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of_node_put(dma_channel_np);
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return -EINVAL;
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}
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*dma_channel_id = be32_to_cpup(iprop);
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dma_np = of_get_parent(dma_channel_np);
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iprop = of_get_property(dma_np, "cell-index", NULL);
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if (!iprop) {
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of_node_put(dma_np);
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2019-02-26 08:17:50 +00:00
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of_node_put(dma_channel_np);
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2012-03-16 08:56:40 +00:00
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return -EINVAL;
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}
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*dma_id = be32_to_cpup(iprop);
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of_node_put(dma_np);
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of_node_put(dma_channel_np);
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return 0;
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}
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EXPORT_SYMBOL(fsl_asoc_get_dma_channel);
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2022-07-01 09:32:36 +00:00
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/**
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* fsl_asoc_get_pll_clocks - get two PLL clock source
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*
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* @dev: device pointer
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* @pll8k_clk: PLL clock pointer for 8kHz
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* @pll11k_clk: PLL clock pointer for 11kHz
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*
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* This function get two PLL clock source
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*/
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void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk,
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struct clk **pll11k_clk)
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{
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*pll8k_clk = devm_clk_get(dev, "pll8k");
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if (IS_ERR(*pll8k_clk))
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*pll8k_clk = NULL;
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*pll11k_clk = devm_clk_get(dev, "pll11k");
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if (IS_ERR(*pll11k_clk))
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*pll11k_clk = NULL;
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}
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EXPORT_SYMBOL(fsl_asoc_get_pll_clocks);
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/**
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* fsl_asoc_reparent_pll_clocks - set clock parent if necessary
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*
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* @dev: device pointer
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* @clk: root clock pointer
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* @pll8k_clk: PLL clock pointer for 8kHz
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* @pll11k_clk: PLL clock pointer for 11kHz
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* @ratio: target requency for root clock
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*
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* This function set root clock parent according to the target ratio
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*/
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void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk,
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struct clk *pll8k_clk,
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struct clk *pll11k_clk, u64 ratio)
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{
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2022-07-07 11:20:06 +00:00
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struct clk *p, *pll = NULL, *npll = NULL;
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2022-07-01 09:32:36 +00:00
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bool reparent = false;
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2022-08-22 18:42:38 +00:00
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int ret;
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2022-07-01 09:32:36 +00:00
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if (!clk || !pll8k_clk || !pll11k_clk)
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return;
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p = clk;
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while (p && pll8k_clk && pll11k_clk) {
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struct clk *pp = clk_get_parent(p);
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if (clk_is_match(pp, pll8k_clk) ||
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clk_is_match(pp, pll11k_clk)) {
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pll = pp;
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break;
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}
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p = pp;
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}
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npll = (do_div(ratio, 8000) ? pll11k_clk : pll8k_clk);
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reparent = (pll && !clk_is_match(pll, npll));
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if (reparent) {
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ret = clk_set_parent(p, npll);
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if (ret < 0)
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2022-07-11 02:39:50 +00:00
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dev_warn(dev, "failed to set parent:%d\n", ret);
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2022-07-01 09:32:36 +00:00
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}
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}
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EXPORT_SYMBOL(fsl_asoc_reparent_pll_clocks);
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2012-03-16 08:56:40 +00:00
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MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
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MODULE_DESCRIPTION("Freescale ASoC utility code");
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MODULE_LICENSE("GPL v2");
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