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linux/arch/powerpc/boot/dts/mpc8544ds.dts

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[POWERPC] 85xx: Add initial MPC8544 DS platform files. This patch provides the basic MPC8544 DS platform code and config. Follow-up patches will add peripherals such as PCI and SATA. Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-20 16:19:10 +00:00
/*
* MPC8544 DS Device Tree Source
*
[POWERPC] 85xx: Convert dts to v1 syntax Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-17 06:28:15 +00:00
* Copyright 2007, 2008 Freescale Semiconductor Inc.
[POWERPC] 85xx: Add initial MPC8544 DS platform files. This patch provides the basic MPC8544 DS platform code and config. Follow-up patches will add peripherals such as PCI and SATA. Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-20 16:19:10 +00:00
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
/include/ "fsl/mpc8544si-pre.dtsi"
[POWERPC] 85xx: Add initial MPC8544 DS platform files. This patch provides the basic MPC8544 DS platform code and config. Follow-up patches will add peripherals such as PCI and SATA. Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-20 16:19:10 +00:00
/ {
model = "MPC8544DS";
compatible = "MPC8544DS", "MPC85xxDS";
memory {
device_type = "memory";
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
reg = <0 0 0 0>; // Filled by U-Boot
[POWERPC] 85xx: Add initial MPC8544 DS platform files. This patch provides the basic MPC8544 DS platform code and config. Follow-up patches will add peripherals such as PCI and SATA. Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-20 16:19:10 +00:00
};
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
lbc: localbus@e0005000 {
reg = <0 0xe0005000 0 0x1000>;
};
[POWERPC] 85xx: Enable MSI support for 85xxds board This patch enabled MSI on 8544ds and 8572ds board. So far only one MSI interrupt can generate on 8544 board. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-05-23 08:32:48 +00:00
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
board_soc: soc: soc8544@e0000000 {
ranges = <0x0 0x0 0xe0000000 0x100000>;
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
};
[POWERPC] Add basic PCI/PCI Express support for 8544DS board Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-07-13 10:05:08 +00:00
[POWERPC] FSL: Added aliases node to device trees Added aliases nodes for kurobox, 83xx, 85xx, and 86xx platforms. This included added labels and cell-index properties for serial and pci nodes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-12 07:46:12 +00:00
pci0: pci@e0008000 {
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
reg = <0 0xe0008000 0 0x1000>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
clock-frequency = <66666666>;
[POWERPC] 85xx: Convert dts to v1 syntax Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-17 06:28:15 +00:00
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
interrupt-map = <
/* IDSEL 0x11 J17 Slot 1 */
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
/* IDSEL 0x12 J16 Slot 2 */
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>;
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
};
[POWERPC] Add basic PCI/PCI Express support for 8544DS board Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-07-13 10:05:08 +00:00
[POWERPC] FSL: Added aliases node to device trees Added aliases nodes for kurobox, 83xx, 85xx, and 86xx platforms. This included added labels and cell-index properties for serial and pci nodes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-12 07:46:12 +00:00
pci1: pcie@e0009000 {
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
reg = <0x0 0xe0009000 0x0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xe1010000 0x0 0x10000>;
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
pcie@0 {
[POWERPC] 85xx: Convert dts to v1 syntax Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-17 06:28:15 +00:00
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
[POWERPC] 85xx: Convert dts to v1 syntax Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-17 06:28:15 +00:00
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
[POWERPC] Add basic PCI/PCI Express support for 8544DS board Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-07-13 10:05:08 +00:00
};
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
};
[POWERPC] Add basic PCI/PCI Express support for 8544DS board Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-07-13 10:05:08 +00:00
[POWERPC] FSL: Added aliases node to device trees Added aliases nodes for kurobox, 83xx, 85xx, and 86xx platforms. This included added labels and cell-index properties for serial and pci nodes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-12 07:46:12 +00:00
pci2: pcie@e000a000 {
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
reg = <0x0 0xe000a000 0x0 0x1000>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0 0xe1020000 0x0 0x10000>;
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
pcie@0 {
[POWERPC] 85xx: Convert dts to v1 syntax Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-17 06:28:15 +00:00
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x10000000
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
[POWERPC] 85xx: Convert dts to v1 syntax Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-17 06:28:15 +00:00
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
[POWERPC] Add basic PCI/PCI Express support for 8544DS board Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-07-13 10:05:08 +00:00
};
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
};
[POWERPC] Add basic PCI/PCI Express support for 8544DS board Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-07-13 10:05:08 +00:00
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
board_pci3: pci3: pcie@e000b000 {
reg = <0x0 0xe000b000 0x0 0x1000>;
ranges = <0x2000000 0x0 0xb0000000 0 0xb0000000 0x0 0x100000
0x1000000 0x0 0x00000000 0 0xb0100000 0x0 0x100000>;
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
pcie@0 {
[POWERPC] 85xx: Convert dts to v1 syntax Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-17 06:28:15 +00:00
ranges = <0x2000000 0x0 0xb0000000
0x2000000 0x0 0xb0000000
0x0 0x100000
[POWERPC] Move PCI nodes to be sibilings with SOC nodes Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-09-12 23:23:46 +00:00
[POWERPC] 85xx: Convert dts to v1 syntax Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-17 06:28:15 +00:00
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
[POWERPC] Add basic PCI/PCI Express support for 8544DS board Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-07-13 10:05:08 +00:00
};
[POWERPC] 85xx: Add initial MPC8544 DS platform files. This patch provides the basic MPC8544 DS platform code and config. Follow-up patches will add peripherals such as PCI and SATA. Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-20 16:19:10 +00:00
};
};
powerpc/85xx: Rework MPC8544DS device tree Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-04 04:24:12 +00:00
/*
* mpc8544ds.dtsi must be last to ensure board_pci3 overrides pci3 settings
* for interrupt-map & interrupt-map-mask
*/
/include/ "fsl/mpc8544si-post.dtsi"
/include/ "mpc8544ds.dtsi"
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