2009-04-27 17:50:23 +00:00
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#include "amd64_edac.h"
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2010-09-02 16:33:24 +00:00
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#define EDAC_DCT_ATTR_SHOW(reg) \
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2012-03-21 17:00:44 +00:00
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static ssize_t amd64_##reg##_show(struct device *dev, \
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struct device_attribute *mattr, \
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char *data) \
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2010-09-02 16:33:24 +00:00
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{ \
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2012-03-21 17:00:44 +00:00
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struct mem_ctl_info *mci = to_mci(dev); \
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2010-09-02 16:33:24 +00:00
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struct amd64_pvt *pvt = mci->pvt_info; \
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return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
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2009-04-27 17:50:23 +00:00
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}
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2010-09-02 16:33:24 +00:00
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EDAC_DCT_ATTR_SHOW(dhar);
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EDAC_DCT_ATTR_SHOW(dbam0);
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EDAC_DCT_ATTR_SHOW(top_mem);
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EDAC_DCT_ATTR_SHOW(top_mem2);
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2009-04-27 17:50:23 +00:00
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2012-03-21 17:00:44 +00:00
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static ssize_t amd64_hole_show(struct device *dev,
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struct device_attribute *mattr,
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char *data)
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2009-04-27 17:50:23 +00:00
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{
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2012-03-21 17:00:44 +00:00
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struct mem_ctl_info *mci = to_mci(dev);
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2009-04-27 17:50:23 +00:00
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u64 hole_base = 0;
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u64 hole_offset = 0;
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u64 hole_size = 0;
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amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
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return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
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hole_size);
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}
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/*
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* update NUM_DBG_ATTRS in case you add new members
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*/
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2012-03-21 17:00:44 +00:00
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static DEVICE_ATTR(dhar, S_IRUGO, amd64_dhar_show, NULL);
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static DEVICE_ATTR(dbam, S_IRUGO, amd64_dbam0_show, NULL);
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static DEVICE_ATTR(topmem, S_IRUGO, amd64_top_mem_show, NULL);
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static DEVICE_ATTR(topmem2, S_IRUGO, amd64_top_mem2_show, NULL);
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static DEVICE_ATTR(dram_hole, S_IRUGO, amd64_hole_show, NULL);
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2015-02-04 10:48:53 +00:00
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static struct attribute *amd64_edac_dbg_attrs[] = {
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&dev_attr_dhar.attr,
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&dev_attr_dbam.attr,
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&dev_attr_topmem.attr,
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&dev_attr_topmem2.attr,
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&dev_attr_dram_hole.attr,
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NULL
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};
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const struct attribute_group amd64_edac_dbg_group = {
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.attrs = amd64_edac_dbg_attrs,
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};
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