2017-04-13 03:29:30 +00:00
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/*
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2018-09-28 14:17:09 +00:00
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* Copyright(c) 2017 - 2018 Intel Corporation.
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2017-04-13 03:29:30 +00:00
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* This file contains HFI1 support for VNIC SDMA functionality
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*/
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#include "sdma.h"
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#include "vnic.h"
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#define HFI1_VNIC_SDMA_Q_ACTIVE BIT(0)
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#define HFI1_VNIC_SDMA_Q_DEFERRED BIT(1)
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#define HFI1_VNIC_TXREQ_NAME_LEN 32
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#define HFI1_VNIC_SDMA_DESC_WTRMRK 64
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/*
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* struct vnic_txreq - VNIC transmit descriptor
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* @txreq: sdma transmit request
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* @sdma: vnic sdma pointer
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* @skb: skb to send
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* @pad: pad buffer
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* @plen: pad length
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* @pbc_val: pbc value
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*/
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struct vnic_txreq {
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struct sdma_txreq txreq;
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struct hfi1_vnic_sdma *sdma;
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struct sk_buff *skb;
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unsigned char pad[HFI1_VNIC_MAX_PAD];
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u16 plen;
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__le64 pbc_val;
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};
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static void vnic_sdma_complete(struct sdma_txreq *txreq,
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int status)
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{
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struct vnic_txreq *tx = container_of(txreq, struct vnic_txreq, txreq);
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struct hfi1_vnic_sdma *vnic_sdma = tx->sdma;
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sdma_txclean(vnic_sdma->dd, txreq);
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dev_kfree_skb_any(tx->skb);
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kmem_cache_free(vnic_sdma->dd->vnic.txreq_cache, tx);
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}
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static noinline int build_vnic_ulp_payload(struct sdma_engine *sde,
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struct vnic_txreq *tx)
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{
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int i, ret = 0;
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ret = sdma_txadd_kvaddr(
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sde->dd,
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&tx->txreq,
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tx->skb->data,
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skb_headlen(tx->skb));
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if (unlikely(ret))
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goto bail_txadd;
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for (i = 0; i < skb_shinfo(tx->skb)->nr_frags; i++) {
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2019-07-23 03:08:25 +00:00
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skb_frag_t *frag = &skb_shinfo(tx->skb)->frags[i];
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2017-04-13 03:29:30 +00:00
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/* combine physically continuous fragments later? */
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ret = sdma_txadd_page(sde->dd,
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&tx->txreq,
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skb_frag_page(frag),
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2019-07-30 14:40:33 +00:00
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skb_frag_off(frag),
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2017-04-13 03:29:30 +00:00
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skb_frag_size(frag));
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if (unlikely(ret))
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goto bail_txadd;
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}
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if (tx->plen)
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ret = sdma_txadd_kvaddr(sde->dd, &tx->txreq,
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tx->pad + HFI1_VNIC_MAX_PAD - tx->plen,
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tx->plen);
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bail_txadd:
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return ret;
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}
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static int build_vnic_tx_desc(struct sdma_engine *sde,
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struct vnic_txreq *tx,
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u64 pbc)
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{
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int ret = 0;
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u16 hdrbytes = 2 << 2; /* PBC */
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ret = sdma_txinit_ahg(
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&tx->txreq,
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0,
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hdrbytes + tx->skb->len + tx->plen,
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0,
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0,
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NULL,
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0,
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vnic_sdma_complete);
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if (unlikely(ret))
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goto bail_txadd;
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/* add pbc */
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tx->pbc_val = cpu_to_le64(pbc);
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ret = sdma_txadd_kvaddr(
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sde->dd,
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&tx->txreq,
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&tx->pbc_val,
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hdrbytes);
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if (unlikely(ret))
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goto bail_txadd;
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/* add the ulp payload */
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ret = build_vnic_ulp_payload(sde, tx);
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bail_txadd:
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return ret;
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}
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/* setup the last plen bypes of pad */
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static inline void hfi1_vnic_update_pad(unsigned char *pad, u8 plen)
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{
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pad[HFI1_VNIC_MAX_PAD - 1] = plen - OPA_VNIC_ICRC_TAIL_LEN;
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}
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int hfi1_vnic_send_dma(struct hfi1_devdata *dd, u8 q_idx,
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struct hfi1_vnic_vport_info *vinfo,
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struct sk_buff *skb, u64 pbc, u8 plen)
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{
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struct hfi1_vnic_sdma *vnic_sdma = &vinfo->sdma[q_idx];
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struct sdma_engine *sde = vnic_sdma->sde;
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struct vnic_txreq *tx;
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int ret = -ECOMM;
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if (unlikely(READ_ONCE(vnic_sdma->state) != HFI1_VNIC_SDMA_Q_ACTIVE))
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goto tx_err;
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if (unlikely(!sde || !sdma_running(sde)))
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goto tx_err;
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tx = kmem_cache_alloc(dd->vnic.txreq_cache, GFP_ATOMIC);
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if (unlikely(!tx)) {
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ret = -ENOMEM;
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goto tx_err;
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}
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tx->sdma = vnic_sdma;
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tx->skb = skb;
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hfi1_vnic_update_pad(tx->pad, plen);
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tx->plen = plen;
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ret = build_vnic_tx_desc(sde, tx, pbc);
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if (unlikely(ret))
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goto free_desc;
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2018-09-28 14:17:09 +00:00
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ret = sdma_send_txreq(sde, iowait_get_ib_work(&vnic_sdma->wait),
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&tx->txreq, vnic_sdma->pkts_sent);
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2017-04-13 03:29:30 +00:00
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/* When -ECOMM, sdma callback will be called with ABORT status */
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if (unlikely(ret && unlikely(ret != -ECOMM)))
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goto free_desc;
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2017-07-24 14:45:37 +00:00
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if (!ret) {
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vnic_sdma->pkts_sent = true;
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iowait_starve_clear(vnic_sdma->pkts_sent, &vnic_sdma->wait);
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}
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2017-04-13 03:29:30 +00:00
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return ret;
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free_desc:
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sdma_txclean(dd, &tx->txreq);
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kmem_cache_free(dd->vnic.txreq_cache, tx);
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tx_err:
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if (ret != -EBUSY)
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dev_kfree_skb_any(skb);
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2017-07-24 14:45:37 +00:00
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else
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vnic_sdma->pkts_sent = false;
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2017-04-13 03:29:30 +00:00
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return ret;
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}
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/*
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* hfi1_vnic_sdma_sleep - vnic sdma sleep function
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*
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* This function gets called from sdma_send_txreq() when there are not enough
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* sdma descriptors available to send the packet. It adds Tx queue's wait
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* structure to sdma engine's dmawait list to be woken up when descriptors
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* become available.
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*/
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static int hfi1_vnic_sdma_sleep(struct sdma_engine *sde,
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2018-09-28 14:17:09 +00:00
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struct iowait_work *wait,
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2017-04-13 03:29:30 +00:00
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struct sdma_txreq *txreq,
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2017-07-24 14:45:37 +00:00
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uint seq,
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bool pkts_sent)
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2017-04-13 03:29:30 +00:00
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{
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struct hfi1_vnic_sdma *vnic_sdma =
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2018-09-28 14:17:09 +00:00
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container_of(wait->iow, struct hfi1_vnic_sdma, wait);
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2017-04-13 03:29:30 +00:00
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2018-11-28 18:33:00 +00:00
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write_seqlock(&sde->waitlock);
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2018-11-28 18:32:48 +00:00
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if (sdma_progress(sde, seq, txreq)) {
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2018-11-28 18:33:00 +00:00
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write_sequnlock(&sde->waitlock);
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2018-11-28 18:32:48 +00:00
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return -EAGAIN;
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}
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2017-04-13 03:29:30 +00:00
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vnic_sdma->state = HFI1_VNIC_SDMA_Q_DEFERRED;
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2019-01-24 05:52:19 +00:00
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if (list_empty(&vnic_sdma->wait.list)) {
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iowait_get_priority(wait->iow);
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2018-09-28 14:17:09 +00:00
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iowait_queue(pkts_sent, wait->iow, &sde->dmawait);
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2019-01-24 05:52:19 +00:00
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}
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2018-11-28 18:33:00 +00:00
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write_sequnlock(&sde->waitlock);
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2017-04-13 03:29:30 +00:00
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return -EBUSY;
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}
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/*
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* hfi1_vnic_sdma_wakeup - vnic sdma wakeup function
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*
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* This function gets called when SDMA descriptors becomes available and Tx
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* queue's wait structure was previously added to sdma engine's dmawait list.
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* It notifies the upper driver about Tx queue wakeup.
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*/
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static void hfi1_vnic_sdma_wakeup(struct iowait *wait, int reason)
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{
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struct hfi1_vnic_sdma *vnic_sdma =
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container_of(wait, struct hfi1_vnic_sdma, wait);
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struct hfi1_vnic_vport_info *vinfo = vnic_sdma->vinfo;
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vnic_sdma->state = HFI1_VNIC_SDMA_Q_ACTIVE;
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if (__netif_subqueue_stopped(vinfo->netdev, vnic_sdma->q_idx))
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netif_wake_subqueue(vinfo->netdev, vnic_sdma->q_idx);
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};
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inline bool hfi1_vnic_sdma_write_avail(struct hfi1_vnic_vport_info *vinfo,
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u8 q_idx)
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{
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struct hfi1_vnic_sdma *vnic_sdma = &vinfo->sdma[q_idx];
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return (READ_ONCE(vnic_sdma->state) == HFI1_VNIC_SDMA_Q_ACTIVE);
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}
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void hfi1_vnic_sdma_init(struct hfi1_vnic_vport_info *vinfo)
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{
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int i;
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for (i = 0; i < vinfo->num_tx_q; i++) {
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struct hfi1_vnic_sdma *vnic_sdma = &vinfo->sdma[i];
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2018-09-28 14:17:09 +00:00
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iowait_init(&vnic_sdma->wait, 0, NULL, NULL,
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hfi1_vnic_sdma_sleep,
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2019-01-24 05:52:19 +00:00
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hfi1_vnic_sdma_wakeup, NULL, NULL);
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2017-04-13 03:29:30 +00:00
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vnic_sdma->sde = &vinfo->dd->per_sdma[i];
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vnic_sdma->dd = vinfo->dd;
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vnic_sdma->vinfo = vinfo;
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vnic_sdma->q_idx = i;
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vnic_sdma->state = HFI1_VNIC_SDMA_Q_ACTIVE;
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/* Add a free descriptor watermark for wakeups */
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if (vnic_sdma->sde->descq_cnt > HFI1_VNIC_SDMA_DESC_WTRMRK) {
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2018-09-28 14:17:09 +00:00
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struct iowait_work *work;
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2017-04-13 03:29:30 +00:00
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INIT_LIST_HEAD(&vnic_sdma->stx.list);
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vnic_sdma->stx.num_desc = HFI1_VNIC_SDMA_DESC_WTRMRK;
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2018-09-28 14:17:09 +00:00
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work = iowait_get_ib_work(&vnic_sdma->wait);
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list_add_tail(&vnic_sdma->stx.list, &work->tx_head);
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2017-04-13 03:29:30 +00:00
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}
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}
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}
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int hfi1_vnic_txreq_init(struct hfi1_devdata *dd)
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{
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char buf[HFI1_VNIC_TXREQ_NAME_LEN];
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snprintf(buf, sizeof(buf), "hfi1_%u_vnic_txreq_cache", dd->unit);
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dd->vnic.txreq_cache = kmem_cache_create(buf,
|
2017-08-22 01:26:45 +00:00
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sizeof(struct vnic_txreq),
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0, SLAB_HWCACHE_ALIGN,
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NULL);
|
2017-04-13 03:29:30 +00:00
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if (!dd->vnic.txreq_cache)
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return -ENOMEM;
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return 0;
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}
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void hfi1_vnic_txreq_deinit(struct hfi1_devdata *dd)
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{
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kmem_cache_destroy(dd->vnic.txreq_cache);
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dd->vnic.txreq_cache = NULL;
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}
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