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treewide: Add SPDX license identifier - Kbuild Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0 Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 12:03:44 +00:00
# SPDX-License-Identifier: GPL-2.0
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
####
# kbuild: Generic definitions
[PATCH] kbuild: more Makefile cleanups This adds the remaining changes which should have been part of the review process. - the define command is inappropriate (it's primarily for rule definitions) - execute commands in the current dir as all other commands - .*.tmp (but not .*.null) files are also removed up by "make clean" - printf has other side effects, just use "echo -e" - proper quoting - proper indentation Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-08 21:48:51 +00:00
# Convenient variables
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
comma := ,
kbuild: move "quote" to Kbuild.include to be consistent Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Michal Marek <mmarek@suse.cz>
2014-03-20 02:08:20 +00:00
quote := "
kbuild: introduce escsq to escapre single quotes This makes things a little bit more reader friendly and gvim is less confused. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-01-06 21:35:59 +00:00
squote := '
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
empty :=
space := $(empty) $(empty)
kbuild: fix if_change and friends to consider argument order Currently, arg-check is implemented as follows: arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \ $(filter-out $(cmd_$@), $(cmd_$(1))) ) This does not care about the order of arguments that appear in $(cmd_$(1)) and $(cmd_$@). So, if_changed and friends never rebuild the target if only the argument order is changed. This is a problem when the link order is changed. Apparently, obj-y += foo.o obj-y += bar.o and obj-y += bar.o obj-y += foo.o should be distinguished because the link order determines the probe order of drivers. So, built-in.o should be rebuilt when the order of objects is changed. This commit fixes arg-check to compare the old/current commands including the argument order. Of course, this change has a side effect; Kbuild will react to the change of compile option order. For example, "-DFOO -DBAR" and "-DBAR -DFOO" should give no difference to the build result, but false positive should be better than false negative. I am moving space_escape to the top of Kbuild.include just for a matter of preference. In practical terms, space_escape can be defined after arg-check because arg-check uses "=" flavor, not ":=". Having said that, collecting convenient variables in one place makes sense from the point of readability. Chaining "%%%SPACE%%%" to "_-_SPACE_-_" is also a matter of taste at this point. Actually, it can be arbitrary as long as it is an unlikely used string. The only problem I see in "%%%SPACE%%%" is that "%" is a special character in "$(patsubst ...)" context. This commit just uses "$(subst ...)" for arg-check, but I am fixing it now in case we might want to use it in $(patsubst ...) context in the future. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Marek <mmarek@suse.com>
2016-05-07 06:48:26 +00:00
space_escape := _-_SPACE_-_
Kbuild: fix # escaping in .cmd files for future Make I tried building using a freshly built Make (4.2.1-69-g8a731d1), but already the objtool build broke with orc_dump.c: In function ‘orc_dump’: orc_dump.c:106:2: error: ‘elf_getshnum’ is deprecated [-Werror=deprecated-declarations] if (elf_getshdrnum(elf, &nr_sections)) { Turns out that with that new Make, the backslash was not removed, so cpp didn't see a #include directive, grep found nothing, and -DLIBELF_USE_DEPRECATED was wrongly put in CFLAGS. Now, that new Make behaviour is documented in their NEWS file: * WARNING: Backward-incompatibility! Number signs (#) appearing inside a macro reference or function invocation no longer introduce comments and should not be escaped with backslashes: thus a call such as: foo := $(shell echo '#') is legal. Previously the number sign needed to be escaped, for example: foo := $(shell echo '\#') Now this latter will resolve to "\#". If you want to write makefiles portable to both versions, assign the number sign to a variable: C := \# foo := $(shell echo '$C') This was claimed to be fixed in 3.81, but wasn't, for some reason. To detect this change search for 'nocomment' in the .FEATURES variable. This also fixes up the two make-cmd instances to replace # with $(pound) rather than with \#. There might very well be other places that need similar fixup in preparation for whatever future Make release contains the above change, but at least this builds an x86_64 defconfig with the new make. Link: https://bugzilla.kernel.org/show_bug.cgi?id=197847 Cc: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-08 21:35:28 +00:00
pound := \#
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
kbuild: add test-{ge,gt,le,lt} macros GNU Make 4.4 introduced $(intcmp ...), which is useful to compare two integers without forking a new process. Add test-{ge,gt,le,lt} macros, which work more efficiently with GNU Make >= 4.4. For older Make versions, they fall back to the 'test' shell command. The first two parameters to $(intcmp ...) must not be empty. To avoid the syntax error, I appended '0' to them. Fortunately, '00' is treated as '0'. This is needed because CONFIG options may expand to an empty string when the kernel configuration is not included. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> # RISC-V Reviewed-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Nicolas Schier <nicolas@fjasle.eu>
2022-12-11 02:46:47 +00:00
###
# Comparison macros.
# Usage: $(call test-lt, $(CONFIG_LLD_VERSION), 150000)
#
# Use $(intcmp ...) if supported. (Make >= 4.4)
# Otherwise, fall back to the 'test' shell command.
ifeq ($(intcmp 1,0,,,y),y)
test-ge = $(intcmp $(strip $1)0, $(strip $2)0,,y,y)
test-gt = $(intcmp $(strip $1)0, $(strip $2)0,,,y)
else
test-ge = $(shell test $(strip $1)0 -ge $(strip $2)0 && echo y)
test-gt = $(shell test $(strip $1)0 -gt $(strip $2)0 && echo y)
endif
test-le = $(call test-ge, $2, $1)
test-lt = $(call test-gt, $2, $1)
kbuild: consistently decide when to rebuild a target Consistently decide when to rebuild a target across all of if_changed, if_changed_dep, if_changed_rule. PHONY targets are now treated alike (ignored) for all targets While add it make Kbuild.include almost readable by factoring out a few bits to some common variables and reuse this in Makefile.build. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-07-23 17:37:44 +00:00
###
# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
dot-target = $(dir $@).$(notdir $@)
kbuild: do not create *.prelink.o for Clang LTO or IBT When CONFIG_LTO_CLANG=y, additional intermediate *.prelink.o is created for each module. Also, objtool is postponed until LLVM IR is converted to ELF. CONFIG_X86_KERNEL_IBT works in a similar way to postpone objtool until objects are merged together. This commit stops generating *.prelink.o, so the build flow will look similar with/without LTO. The following figures show how the LTO build currently works, and how this commit is changing it. Current build flow ================== [1] single-object module $(LD) $(CC) +objtool $(LD) foo.c --------------------> foo.o -----> foo.prelink.o -----> foo.ko (LLVM IR) (ELF) | (ELF) | foo.mod.o --/ (LLVM IR) [2] multi-object module $(LD) $(CC) $(AR) +objtool $(LD) foo1.c -----> foo1.o -----> foo.o -----> foo.prelink.o -----> foo.ko | (archive) (ELF) | (ELF) foo2.c -----> foo2.o --/ | (LLVM IR) foo.mod.o --/ (LLVM IR) One confusion is that foo.o in multi-object module is an archive despite of its suffix. New build flow ============== [1] single-object module Since there is only one object, there is no need to keep the LLVM IR. Use $(CC)+$(LD) to generate an ELF object in one build rule. When LTO is disabled, $(LD) is unneeded because $(CC) produces an ELF object. $(CC)+$(LD)+objtool $(LD) foo.c ----------------------------> foo.o ---------> foo.ko (ELF) | (ELF) | foo.mod.o --/ (LLVM IR) [2] multi-object module Previously, $(AR) was used to combine LLVM IR files into an archive, but there was no technical reason to do so. Use $(LD) to merge them into a single ELF object. $(LD) $(CC) +objtool $(LD) foo1.c ---------> foo1.o ---------> foo.o ---------> foo.ko | (ELF) | (ELF) foo2.c ---------> foo2.o ----/ | (LLVM IR) foo.mod.o --/ (LLVM IR) Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Nicolas Schier <nicolas@fjasle.eu> Tested-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Sami Tolvanen <samitolvanen@google.com> Tested-by: Sedat Dilek <sedat.dilek@gmail.com> # LLVM-14 (x86-64) Acked-by: Josh Poimboeuf <jpoimboe@kernel.org>
2022-05-27 10:01:49 +00:00
###
# Name of target with a '.tmp_' as filename prefix. foo/bar.o => foo/.tmp_bar.o
tmp-target = $(dir $@).tmp_$(notdir $@)
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
###
kbuild: use -MMD instead of -MD to exclude system headers from dependency This omits system headers from the generated header dependency. System headers are not updated unless you upgrade the compiler. Nor do they contain CONFIG options, so fixdep does not need to parse them. Having said that, the effect of this optimization will be quite small because the kernel code generally does not include system headers except <stdarg.h>. Host programs include a lot of system headers, but there are not so many in the kernel tree. At first, keeping system headers in .*.cmd files might be useful to detect the compiler update, but there is no guarantee that <stdarg.h> is included from every file. So, I implemented a more reliable way in the previous commit. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-04-23 14:23:53 +00:00
# The temporary file to save gcc -MMD generated dependencies must not
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
# contain a comma
kbuild: consistently decide when to rebuild a target Consistently decide when to rebuild a target across all of if_changed, if_changed_dep, if_changed_rule. PHONY targets are now treated alike (ignored) for all targets While add it make Kbuild.include almost readable by factoring out a few bits to some common variables and reuse this in Makefile.build. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-07-23 17:37:44 +00:00
depfile = $(subst $(comma),_,$(dot-target).d)
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
kbuild: fix ia64 breakage after introducing make -rR kbuild used $¤(*F to get filename of target without extension. This was used in several places all over kbuild, but introducing make -rR broke his for all cases where we specified full path to target/prerequsite. It is assumed that make -rR disables old style suffix-rules which is why is suddenly failed. ia64 was impacted by this change because several div* routines in arch/ia64/lib are build using explicit paths and then kbuild failed. Thanks to David Mosberger-Tang <David.Mosberger@acm.org> for an explanation what was the root-cause and for testing on ia64. This patch also fixes two uses of $(*F) in arch/um Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-07-01 07:58:02 +00:00
###
# filename of target with directory and extension stripped
basetarget = $(basename $(notdir $@))
kbuild: add real-prereqs shorthand for $(filter-out FORCE,$^) In Kbuild, if_changed and friends must have FORCE as a prerequisite. Hence, $(filter-out FORCE,$^) or $(filter-out $(PHONY),$^) is a common idiom to get the names of all the prerequisites except phony targets. Add real-prereqs as a shorthand. Note: We cannot replace $(filter %.o,$^) in cmd_link_multi-m because $^ may include auto-generated dependencies from the .*.cmd file when a single object module is changed into a multi object module. Refer to commit 69ea912fda74 ("kbuild: remove unneeded link_multi_deps"). I added some comment to avoid accidental breakage. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org>
2019-01-17 10:02:43 +00:00
###
# real prerequisites without phony targets
real-prereqs = $(filter-out $(PHONY), $^)
kbuild: introduce escsq to escapre single quotes This makes things a little bit more reader friendly and gvim is less confused. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-01-06 21:35:59 +00:00
###
# Escape single quote for use in echo statements
escsq = $(subst $(squote),'\$(squote)',$1)
kbuild: add stringify helper to quote a string passed to C files Make $(squote)$(quote)...$(quote)$(squote) a helper macro. I will reuse it in the next commit. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2019-12-19 08:33:27 +00:00
###
# Quote a string to pass it to C files. foo => '"foo"'
stringify = $(squote)$(quote)$1$(quote)$(squote)
kbuild: add kbuild-file macro While building, installing, cleaning, Kbuild visits sub-directories and includes 'Kbuild' or 'Makefile' that exists there. Add 'kbuild-file' macro, and reuse it from scripts/Makefie.* Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Nicolas Schier <nicolas@fjasle.eu> Reviewed-by: Alexander Lobakin <alobakin@pm.me> Tested-by: Alexander Lobakin <alobakin@pm.me>
2022-11-18 19:15:50 +00:00
###
# The path to Kbuild or Makefile. Kbuild has precedence over Makefile.
kbuild-dir = $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
kbuild-file = $(or $(wildcard $(kbuild-dir)/Kbuild),$(kbuild-dir)/Makefile)
kbuild: introduce $(kecho) convenience echo There is a bunch of places in the build system where we do 'echo' to show some nice status lines. This means we still get output when running in silent mode. So declare a new KECHO variable that only does 'echo' when we are in a suitable verbose build mode. Signed-off-by: Mike Frysinger <vapier@gentoo.org> [sam: added Documentation] Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2008-11-06 08:31:34 +00:00
###
# Easy method for doing a status message
kecho := :
quiet_kecho := echo
silent_kecho := :
kecho := $($(quiet)kecho)
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
###
# filechk is used to check if the content of a generated file is updated.
# Sample usage:
kbuild: use assignment instead of define ... endef for filechk_* rules You do not have to use define ... endef for filechk_* rules. For simple cases, the use of assignment looks cleaner, IMHO. I updated the usage for scripts/Kbuild.include in case somebody misunderstands the 'define ... endif' is the requirement. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com>
2019-01-03 01:16:54 +00:00
#
# filechk_sample = echo $(KERNELRELEASE)
# version.h: FORCE
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
# $(call filechk,sample)
kbuild: use assignment instead of define ... endef for filechk_* rules You do not have to use define ... endef for filechk_* rules. For simple cases, the use of assignment looks cleaner, IMHO. I updated the usage for scripts/Kbuild.include in case somebody misunderstands the 'define ... endif' is the requirement. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com>
2019-01-03 01:16:54 +00:00
#
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
# The rule defined shall write to stdout the content of the new file.
# The existing file will be compared with the new one.
# - If no file exist it is created
# - If the content differ the new file is used
# - If they are equal no change, and no timestamp update
define filechk
kbuild: warn if FORCE is missing for if_changed(_dep,_rule) and filechk if_changed, if_changed_dep, and if_changed_rule must have FORCE as a prerequisite so the command line change is detected. Documentation/kbuild/makefiles.rst clearly explains it: Note: It is a typical mistake to forget the FORCE prerequisite. However, not all people follow the document. This mistake occurred again and again, so a compelling force is needed. Show a warning if FORCE is missing in the prerequisite of if_changed and friends. Same for filechk. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Tested-by: Nicolas Schier <n.schier@avm.de>
2021-08-13 06:30:05 +00:00
$(check-FORCE)
kbuild: remove *.tmp file when filechk fails Bartosz Golaszewski reports that when "make {menu,n,g,x}config" fails due to missing packages, a temporary file is left over, which is not ignored by git. For example, if GTK+ is not installed: $ make gconfig * * Unable to find the GTK+ installation. Please make sure that * the GTK+ 2.0 development package is correctly installed. * You need gtk+-2.0 gmodule-2.0 libglade-2.0 * scripts/kconfig/Makefile:208: recipe for target 'scripts/kconfig/gconf-cfg' failed make[1]: *** [scripts/kconfig/gconf-cfg] Error 1 Makefile:567: recipe for target 'gconfig' failed make: *** [gconfig] Error 2 $ git status HEAD detached at v5.4 Untracked files: (use "git add <file>..." to include in what will be committed) scripts/kconfig/gconf-cfg.tmp nothing added to commit but untracked files present (use "git add" to track) This is because the check scripts are run with filechk, which misses to clean up the temporary file on failure. When the line { $(filechk_$(1)); } > $@.tmp; ... fails, it exits immediately due to the 'set -e'. Use trap to make sure to delete the temporary file on exit. For extra safety, I replaced $@.tmp with $(dot-target).tmp to make it a hidden file. Reported-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-01-10 05:02:24 +00:00
$(Q)set -e; \
mkdir -p $(dir $@); \
trap "rm -f $(dot-target).tmp" EXIT; \
{ $(filechk_$(1)); } > $(dot-target).tmp; \
if [ ! -r $@ ] || ! cmp -s $@ $(dot-target).tmp; then \
$(kecho) ' UPD $@'; \
mv -f $(dot-target).tmp $@; \
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
fi
endef
[PATCH] kbuild: more Makefile cleanups This adds the remaining changes which should have been part of the review process. - the define command is inappropriate (it's primarily for rule definitions) - execute commands in the current dir as all other commands - .*.tmp (but not .*.null) files are also removed up by "make clean" - printf has other side effects, just use "echo -e" - proper quoting - proper indentation Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-08 21:48:51 +00:00
###
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj=
# Usage:
# $(Q)$(MAKE) $(build)=dir
kbuild: simplify build, clean, modbuiltin shorthands $(if $(KBUILD_SRC),$(srctree)/) was a useful strategy to omit a long absolute path for in-source-tree build prior to commit 890676c65d699db3ad82e7dddd0cf8fb449031af (kbuild: Use relative path when building in the source tree). Now $(srctree) is "." when building in the source tree. It would not be annoying to add "$(srctree)/" all the time. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Michal Marek <mmarek@suse.cz>
2014-09-09 11:03:58 +00:00
build := -f $(srctree)/scripts/Makefile.build obj
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst Move dtbs install rules to Makefile.dtbinst. This change is needed to implement support for dts vendor subdirs. The change makes Makefiles easier and smaller as no longer the dtbs_install rule needs to be defined. Another advantage is that install goals are not encoded in targets anymore (%.dtb_dtbinst_). Signed-off-by: Robert Richter <rrichter@cavium.com>
2014-09-03 13:29:24 +00:00
###
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.dtbinst obj=
# Usage:
# $(Q)$(MAKE) $(dtbinst)=dir
kbuild: prefix Makefile.dtbinst path with $(srctree) unconditionally $(srctree) always points to the top of the source tree whether KBUILD_SRC is set or not. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-12 04:52:54 +00:00
dtbinst := -f $(srctree)/scripts/Makefile.dtbinst obj
dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst Move dtbs install rules to Makefile.dtbinst. This change is needed to implement support for dts vendor subdirs. The change makes Makefiles easier and smaller as no longer the dtbs_install rule needs to be defined. Another advantage is that install goals are not encoded in targets anymore (%.dtb_dtbinst_). Signed-off-by: Robert Richter <rrichter@cavium.com>
2014-09-03 13:29:24 +00:00
kbuild: collect shorthands into scripts/Kbuild.include The shorthand "clean" is defined in both the top Makefile and scripts/Makefile.clean. Likewise, the "hdr-inst" is defined in both the top Makefile and scripts/Makefile.headersinst. To reduce code duplication, this commit collects them into scripts/Kbuild.include like the "build" and "modbuiltin" shorthands. It requires scripts/Makefile.clean to include scripts/Kbuild.include, but its impact on the performance of "make clean" should be negligible. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Michal Marek <mmarek@suse.cz>
2014-11-26 10:31:13 +00:00
###
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=
# Usage:
# $(Q)$(MAKE) $(clean)=dir
clean := -f $(srctree)/scripts/Makefile.clean obj
[PATCH] kbuild: improve option checking, Kbuild.include cleanup GNU binutils, root users, tmpfiles, external modules ro builds must be fixed to do the right thing now. Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Horst Schirmeier <horst@schirmeier.com> Cc: Jan Beulich <jbeulich@novell.com> Cc: Daniel Drake <dsd@gentoo.org> Cc: Andi Kleen <ak@suse.de> Cc: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Oleg Verych <olecom@flower.upol.cz> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-06 01:18:21 +00:00
# echo command.
# Short version is used, if $(quiet) equals `quiet_', otherwise full one.
[PATCH] kbuild, Kbuild.include: avoid using spaces in call arguments Do not use whitespace in arguments of functions in makefiles, as they propagate further without notice. Thus we get + echo ' y' instead of + echo y Fix misleading comments. Signed-off-by: Oleg Verych <olecom@flower.upol.cz> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-07 22:04:35 +00:00
echo-cmd = $(if $($(quiet)cmd_$(1)),\
[PATCH] kbuild: improve option checking, Kbuild.include cleanup GNU binutils, root users, tmpfiles, external modules ro builds must be fixed to do the right thing now. Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Horst Schirmeier <horst@schirmeier.com> Cc: Jan Beulich <jbeulich@novell.com> Cc: Daniel Drake <dsd@gentoo.org> Cc: Andi Kleen <ak@suse.de> Cc: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Oleg Verych <olecom@flower.upol.cz> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-06 01:18:21 +00:00
echo ' $(call escsq,$($(quiet)cmd_$(1)))$(echo-why)';)
kbuild: sink stdout from cmd for silent build When building with 'make -s', no output to stdout should be printed. As Arnd Bergmann reported [1], mkimage shows the detailed information of the generated images. I think this should be suppressed by the 'cmd' macro instead of by individual scripts. Insert 'exec >/dev/null;' in order to redirect stdout to /dev/null for silent builds. [Note about this implementation] 'exec >/dev/null;' may look somewhat tricky, but this has a reason. Appending '>/dev/null' at the end of command line is a common way for redirection, so I first tried this: cmd = @set -e; $(echo-cmd) $(cmd_$(1)) >/dev/null ... but it would not work if $(cmd_$(1)) itself contains a redirection. For example, cmd_wrap in scripts/Makefile.asm-generic redirects the output from the 'echo' command into the target file. It would be expanded into: echo "#include <asm-generic/$*.h>" > $@ >/dev/null Then, the target file gets empty because the string will go to /dev/null instead of $@. Next, I tried this: cmd = @set -e; $(echo-cmd) { $(cmd_$(1)); } >/dev/null The form above would be expanded into: { echo "#include <asm-generic/$*.h>" > $@; } >/dev/null This works as expected. However, it would be a syntax error if $(cmd_$(1)) is empty. When CONFIG_TRIM_UNUSED_KSYMS is disabled, $(call cmd,gen_ksymdeps) in scripts/Makefile.build would be expanded into: set -e; { ; } >/dev/null ..., which causes an syntax error. I also tried this: cmd = @set -e; $(echo-cmd) ( $(cmd_$(1)) ) >/dev/null ... but this causes a syntax error for the same reason. So, finally I adopted: cmd = @set -e; $(echo-cmd) exec >/dev/null; $(cmd_$(1)) [1]: https://lore.kernel.org/lkml/20210514135752.2910387-1-arnd@kernel.org/ Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2021-05-17 07:03:13 +00:00
# sink stdout for 'make -s'
redirect :=
quiet_redirect :=
silent_redirect := exec >/dev/null;
kbuild: remove the target in signal traps when interrupted When receiving some signal, GNU Make automatically deletes the target if it has already been changed by the interrupted recipe. If the target is possibly incomplete due to interruption, it must be deleted so that it will be remade from scratch on the next run of make. Otherwise, the target would remain corrupted permanently because its timestamp had already been updated. Thanks to this behavior of Make, you can stop the build any time by pressing Ctrl-C, and just run 'make' to resume it. Kbuild also relies on this feature, but it is equivalently important for any build systems that make decisions based on timestamps (if you want to support Ctrl-C reliably). However, this does not always work as claimed; Make immediately dies with Ctrl-C if its stderr goes into a pipe. [Test Makefile] foo: echo hello > $@ sleep 3 echo world >> $@ [Test Result] $ make # hit Ctrl-C echo hello > foo sleep 3 ^Cmake: *** Deleting file 'foo' make: *** [Makefile:3: foo] Interrupt $ make 2>&1 | cat # hit Ctrl-C echo hello > foo sleep 3 ^C$ # 'foo' is often left-over The reason is because SIGINT is sent to the entire process group. In this example, SIGINT kills 'cat', and 'make' writes the message to the closed pipe, then dies with SIGPIPE before cleaning the target. A typical bad scenario (as reported by [1], [2]) is to save build log by using the 'tee' command: $ make 2>&1 | tee log This can be problematic for any build systems based on Make, so I hope it will be fixed in GNU Make. The maintainer of GNU Make stated this is a long-standing issue and difficult to fix [3]. It has not been fixed yet as of writing. So, we cannot rely on Make cleaning the target. We can do it by ourselves, in signal traps. As far as I understand, Make takes care of SIGHUP, SIGINT, SIGQUIT, and SITERM for the target removal. I added the traps for them, and also for SIGPIPE just in case cmd_* rule prints something to stdout or stderr (but I did not observe an actual case where SIGPIPE was triggered). [Note 1] The trap handler might be worth explaining. rm -f $@; trap - $(sig); kill -s $(sig) $$ This lets the shell kill itself by the signal it caught, so the parent process can tell the child has exited on the signal. Generally, this is a proper manner for handling signals, in case the calling program (like Bash) may monitor WIFSIGNALED() and WTERMSIG() for WCE although this may not be a big deal here because GNU Make handles SIGHUP, SIGINT, SIGQUIT in WUE and SIGTERM in IUE. IUE - Immediate Unconditional Exit WUE - Wait and Unconditional Exit WCE - Wait and Cooperative Exit For details, see "Proper handling of SIGINT/SIGQUIT" [4]. [Note 2] Reverting 392885ee82d3 ("kbuild: let fixdep directly write to .*.cmd files") would directly address [1], but it only saves if_changed_dep. As reported in [2], all commands that use redirection can potentially leave an empty (i.e. broken) target. [Note 3] Another (even safer) approach might be to always write to a temporary file, and rename it to $@ at the end of the recipe. <command> > $(tmp-target) mv $(tmp-target) $@ It would require a lot of Makefile changes, and result in ugly code, so I did not take it. [Note 4] A little more thoughts about a pattern rule with multiple targets (or a grouped target). %.x %.y: %.z <recipe> When interrupted, GNU Make deletes both %.x and %.y, while this solution only deletes $@. Probably, this is not a big deal. The next run of make will execute the rule again to create $@ along with the other files. [1]: https://lore.kernel.org/all/YLeot94yAaM4xbMY@gmail.com/ [2]: https://lore.kernel.org/all/20220510221333.2770571-1-robh@kernel.org/ [3]: https://lists.gnu.org/archive/html/help-make/2021-06/msg00001.html [4]: https://www.cons.org/cracauer/sigint.html Fixes: 392885ee82d3 ("kbuild: let fixdep directly write to .*.cmd files") Reported-by: Ingo Molnar <mingo@kernel.org> Reported-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Tested-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Nicolas Schier <nicolas@fjasle.eu>
2022-08-07 00:48:09 +00:00
# Delete the target on interruption
#
# GNU Make automatically deletes the target if it has already been changed by
# the interrupted recipe. So, you can safely stop the build by Ctrl-C (Make
# will delete incomplete targets), and resume it later.
#
# However, this does not work when the stderr is piped to another program, like
# $ make >&2 | tee log
# Make dies with SIGPIPE before cleaning the targets.
#
# To address it, we clean the target in signal traps.
#
# Make deletes the target when it catches SIGHUP, SIGINT, SIGQUIT, SIGTERM.
# So, we cover them, and also SIGPIPE just in case.
#
# Of course, this is unneeded for phony targets.
delete-on-interrupt = \
$(if $(filter-out $(PHONY), $@), \
$(foreach sig, HUP INT QUIT TERM PIPE, \
trap 'rm -f $@; trap - $(sig); kill -s $(sig) $$$$' $(sig);))
[PATCH] kbuild: improve option checking, Kbuild.include cleanup GNU binutils, root users, tmpfiles, external modules ro builds must be fixed to do the right thing now. Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Horst Schirmeier <horst@schirmeier.com> Cc: Jan Beulich <jbeulich@novell.com> Cc: Daniel Drake <dsd@gentoo.org> Cc: Andi Kleen <ak@suse.de> Cc: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Oleg Verych <olecom@flower.upol.cz> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-06 01:18:21 +00:00
# printing commands
kbuild: remove the target in signal traps when interrupted When receiving some signal, GNU Make automatically deletes the target if it has already been changed by the interrupted recipe. If the target is possibly incomplete due to interruption, it must be deleted so that it will be remade from scratch on the next run of make. Otherwise, the target would remain corrupted permanently because its timestamp had already been updated. Thanks to this behavior of Make, you can stop the build any time by pressing Ctrl-C, and just run 'make' to resume it. Kbuild also relies on this feature, but it is equivalently important for any build systems that make decisions based on timestamps (if you want to support Ctrl-C reliably). However, this does not always work as claimed; Make immediately dies with Ctrl-C if its stderr goes into a pipe. [Test Makefile] foo: echo hello > $@ sleep 3 echo world >> $@ [Test Result] $ make # hit Ctrl-C echo hello > foo sleep 3 ^Cmake: *** Deleting file 'foo' make: *** [Makefile:3: foo] Interrupt $ make 2>&1 | cat # hit Ctrl-C echo hello > foo sleep 3 ^C$ # 'foo' is often left-over The reason is because SIGINT is sent to the entire process group. In this example, SIGINT kills 'cat', and 'make' writes the message to the closed pipe, then dies with SIGPIPE before cleaning the target. A typical bad scenario (as reported by [1], [2]) is to save build log by using the 'tee' command: $ make 2>&1 | tee log This can be problematic for any build systems based on Make, so I hope it will be fixed in GNU Make. The maintainer of GNU Make stated this is a long-standing issue and difficult to fix [3]. It has not been fixed yet as of writing. So, we cannot rely on Make cleaning the target. We can do it by ourselves, in signal traps. As far as I understand, Make takes care of SIGHUP, SIGINT, SIGQUIT, and SITERM for the target removal. I added the traps for them, and also for SIGPIPE just in case cmd_* rule prints something to stdout or stderr (but I did not observe an actual case where SIGPIPE was triggered). [Note 1] The trap handler might be worth explaining. rm -f $@; trap - $(sig); kill -s $(sig) $$ This lets the shell kill itself by the signal it caught, so the parent process can tell the child has exited on the signal. Generally, this is a proper manner for handling signals, in case the calling program (like Bash) may monitor WIFSIGNALED() and WTERMSIG() for WCE although this may not be a big deal here because GNU Make handles SIGHUP, SIGINT, SIGQUIT in WUE and SIGTERM in IUE. IUE - Immediate Unconditional Exit WUE - Wait and Unconditional Exit WCE - Wait and Cooperative Exit For details, see "Proper handling of SIGINT/SIGQUIT" [4]. [Note 2] Reverting 392885ee82d3 ("kbuild: let fixdep directly write to .*.cmd files") would directly address [1], but it only saves if_changed_dep. As reported in [2], all commands that use redirection can potentially leave an empty (i.e. broken) target. [Note 3] Another (even safer) approach might be to always write to a temporary file, and rename it to $@ at the end of the recipe. <command> > $(tmp-target) mv $(tmp-target) $@ It would require a lot of Makefile changes, and result in ugly code, so I did not take it. [Note 4] A little more thoughts about a pattern rule with multiple targets (or a grouped target). %.x %.y: %.z <recipe> When interrupted, GNU Make deletes both %.x and %.y, while this solution only deletes $@. Probably, this is not a big deal. The next run of make will execute the rule again to create $@ along with the other files. [1]: https://lore.kernel.org/all/YLeot94yAaM4xbMY@gmail.com/ [2]: https://lore.kernel.org/all/20220510221333.2770571-1-robh@kernel.org/ [3]: https://lists.gnu.org/archive/html/help-make/2021-06/msg00001.html [4]: https://www.cons.org/cracauer/sigint.html Fixes: 392885ee82d3 ("kbuild: let fixdep directly write to .*.cmd files") Reported-by: Ingo Molnar <mingo@kernel.org> Reported-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Tested-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Nicolas Schier <nicolas@fjasle.eu>
2022-08-07 00:48:09 +00:00
cmd = @set -e; $(echo-cmd) $($(quiet)redirect) $(delete-on-interrupt) $(cmd_$(1))
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
###
[PATCH] kbuild: improve option checking, Kbuild.include cleanup GNU binutils, root users, tmpfiles, external modules ro builds must be fixed to do the right thing now. Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Horst Schirmeier <horst@schirmeier.com> Cc: Jan Beulich <jbeulich@novell.com> Cc: Daniel Drake <dsd@gentoo.org> Cc: Andi Kleen <ak@suse.de> Cc: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Oleg Verych <olecom@flower.upol.cz> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-06 01:18:21 +00:00
# if_changed - execute command if any prerequisite is newer than
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
# target, or command line has changed
# if_changed_dep - as if_changed, but uses fixdep to reveal dependencies
# including used config symbols
# if_changed_rule - as if_changed but execute rule instead
docs: kbuild: convert docs to ReST and rename to *.rst The kbuild documentation clearly shows that the documents there are written at different times: some use markdown, some use their own peculiar logic to split sections. Convert everything to ReST without affecting too much the author's style and avoiding adding uneeded markups. The conversion is actually: - add blank lines and identation in order to identify paragraphs; - fix tables markups; - add some lists markups; - mark literal blocks; - adjust title markups. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2019-06-12 17:52:48 +00:00
# See Documentation/kbuild/makefiles.rst for more info
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
ifneq ($(KBUILD_NOCMDDEP),1)
kbuild: rename arg-check to cmd-check I prefer 'cmd-check' for consistency. We have 'echo-cmd', 'cmd', 'cmd_and_fixdep', etc. in this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-22 16:07:03 +00:00
# Check if both commands are the same including their order. Result is empty
kbuild: fix if_change and friends to consider argument order Currently, arg-check is implemented as follows: arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \ $(filter-out $(cmd_$@), $(cmd_$(1))) ) This does not care about the order of arguments that appear in $(cmd_$(1)) and $(cmd_$@). So, if_changed and friends never rebuild the target if only the argument order is changed. This is a problem when the link order is changed. Apparently, obj-y += foo.o obj-y += bar.o and obj-y += bar.o obj-y += foo.o should be distinguished because the link order determines the probe order of drivers. So, built-in.o should be rebuilt when the order of objects is changed. This commit fixes arg-check to compare the old/current commands including the argument order. Of course, this change has a side effect; Kbuild will react to the change of compile option order. For example, "-DFOO -DBAR" and "-DBAR -DFOO" should give no difference to the build result, but false positive should be better than false negative. I am moving space_escape to the top of Kbuild.include just for a matter of preference. In practical terms, space_escape can be defined after arg-check because arg-check uses "=" flavor, not ":=". Having said that, collecting convenient variables in one place makes sense from the point of readability. Chaining "%%%SPACE%%%" to "_-_SPACE_-_" is also a matter of taste at this point. Actually, it can be arbitrary as long as it is an unlikely used string. The only problem I see in "%%%SPACE%%%" is that "%" is a special character in "$(patsubst ...)" context. This commit just uses "$(subst ...)" for arg-check, but I am fixing it now in case we might want to use it in $(patsubst ...) context in the future. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Marek <mmarek@suse.com>
2016-05-07 06:48:26 +00:00
# string if equal. User may override this check using make KBUILD_NOCMDDEP=1
kbuild: rename arg-check to cmd-check I prefer 'cmd-check' for consistency. We have 'echo-cmd', 'cmd', 'cmd_and_fixdep', etc. in this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-22 16:07:03 +00:00
cmd-check = $(filter-out $(subst $(space),$(space_escape),$(strip $(cmd_$@))), \
kbuild: fix if_change and friends to consider argument order Currently, arg-check is implemented as follows: arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \ $(filter-out $(cmd_$@), $(cmd_$(1))) ) This does not care about the order of arguments that appear in $(cmd_$(1)) and $(cmd_$@). So, if_changed and friends never rebuild the target if only the argument order is changed. This is a problem when the link order is changed. Apparently, obj-y += foo.o obj-y += bar.o and obj-y += bar.o obj-y += foo.o should be distinguished because the link order determines the probe order of drivers. So, built-in.o should be rebuilt when the order of objects is changed. This commit fixes arg-check to compare the old/current commands including the argument order. Of course, this change has a side effect; Kbuild will react to the change of compile option order. For example, "-DFOO -DBAR" and "-DBAR -DFOO" should give no difference to the build result, but false positive should be better than false negative. I am moving space_escape to the top of Kbuild.include just for a matter of preference. In practical terms, space_escape can be defined after arg-check because arg-check uses "=" flavor, not ":=". Having said that, collecting convenient variables in one place makes sense from the point of readability. Chaining "%%%SPACE%%%" to "_-_SPACE_-_" is also a matter of taste at this point. Actually, it can be arbitrary as long as it is an unlikely used string. The only problem I see in "%%%SPACE%%%" is that "%" is a special character in "$(patsubst ...)" context. This commit just uses "$(subst ...)" for arg-check, but I am fixing it now in case we might want to use it in $(patsubst ...) context in the future. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Marek <mmarek@suse.com>
2016-05-07 06:48:26 +00:00
$(subst $(space),$(space_escape),$(strip $(cmd_$1))))
kbuild: make KBUILD_NOCMDDEP=1 handle empty built-in.o Based on a patch by Rabin Vincent. Fix building with KBUILD_NOCMDDEP=1, which currently does not work because it does not build built-in.o with no dependencies: LD fs/notify/built-in.o ld: cannot find fs/notify/dnotify/built-in.o: No such file or directory ld: cannot find fs/notify/inotify/built-in.o: No such file or directory ld: cannot find fs/notify/fanotify/built-in.o: No such file or directory Reported-and-tested-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Michal Marek <mmarek@suse.cz>
2011-05-16 14:37:34 +00:00
else
kbuild: rename arg-check to cmd-check I prefer 'cmd-check' for consistency. We have 'echo-cmd', 'cmd', 'cmd_and_fixdep', etc. in this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-22 16:07:03 +00:00
cmd-check = $(if $(strip $(cmd_$@)),,1)
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
endif
kbuild: Fix handling of backslashes in *.cmd files Commit c353acba ("kbuild: make: fix if_changed when command contains backslashes") attempted to handle backslashes in *.cmd files, but it only handled double backslashes for some reason. Changing make-cmd to also handle single backslashes fixes rebuilds with dash, but it breaks bash again. The reason is that the two shells disagree about the interpretation of backslash sequences in the echo builtin. The way out of this is to print the command with printf '%s\n'. While at it, document what the individual parts of make-cmd do and why. Reported-and-tested-by: Konstantin Khlebnikov <koct9i@gmail.com> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Michal Marek <mmarek@suse.cz>
2014-08-07 19:39:57 +00:00
# Replace >$< with >$$< to preserve $ when reloading the .cmd file
# (needed for make)
Kbuild: fix # escaping in .cmd files for future Make I tried building using a freshly built Make (4.2.1-69-g8a731d1), but already the objtool build broke with orc_dump.c: In function ‘orc_dump’: orc_dump.c:106:2: error: ‘elf_getshnum’ is deprecated [-Werror=deprecated-declarations] if (elf_getshdrnum(elf, &nr_sections)) { Turns out that with that new Make, the backslash was not removed, so cpp didn't see a #include directive, grep found nothing, and -DLIBELF_USE_DEPRECATED was wrongly put in CFLAGS. Now, that new Make behaviour is documented in their NEWS file: * WARNING: Backward-incompatibility! Number signs (#) appearing inside a macro reference or function invocation no longer introduce comments and should not be escaped with backslashes: thus a call such as: foo := $(shell echo '#') is legal. Previously the number sign needed to be escaped, for example: foo := $(shell echo '\#') Now this latter will resolve to "\#". If you want to write makefiles portable to both versions, assign the number sign to a variable: C := \# foo := $(shell echo '$C') This was claimed to be fixed in 3.81, but wasn't, for some reason. To detect this change search for 'nocomment' in the .FEATURES variable. This also fixes up the two make-cmd instances to replace # with $(pound) rather than with \#. There might very well be other places that need similar fixup in preparation for whatever future Make release contains the above change, but at least this builds an x86_64 defconfig with the new make. Link: https://bugzilla.kernel.org/show_bug.cgi?id=197847 Cc: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-08 21:35:28 +00:00
# Replace >#< with >$(pound)< to avoid starting a comment in the .cmd file
kbuild: Fix handling of backslashes in *.cmd files Commit c353acba ("kbuild: make: fix if_changed when command contains backslashes") attempted to handle backslashes in *.cmd files, but it only handled double backslashes for some reason. Changing make-cmd to also handle single backslashes fixes rebuilds with dash, but it breaks bash again. The reason is that the two shells disagree about the interpretation of backslash sequences in the echo builtin. The way out of this is to print the command with printf '%s\n'. While at it, document what the individual parts of make-cmd do and why. Reported-and-tested-by: Konstantin Khlebnikov <koct9i@gmail.com> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Michal Marek <mmarek@suse.cz>
2014-08-07 19:39:57 +00:00
# (needed for make)
# Replace >'< with >'\''< to be able to enclose the whole string in '...'
# (needed for the shell)
Kbuild: fix # escaping in .cmd files for future Make I tried building using a freshly built Make (4.2.1-69-g8a731d1), but already the objtool build broke with orc_dump.c: In function ‘orc_dump’: orc_dump.c:106:2: error: ‘elf_getshnum’ is deprecated [-Werror=deprecated-declarations] if (elf_getshdrnum(elf, &nr_sections)) { Turns out that with that new Make, the backslash was not removed, so cpp didn't see a #include directive, grep found nothing, and -DLIBELF_USE_DEPRECATED was wrongly put in CFLAGS. Now, that new Make behaviour is documented in their NEWS file: * WARNING: Backward-incompatibility! Number signs (#) appearing inside a macro reference or function invocation no longer introduce comments and should not be escaped with backslashes: thus a call such as: foo := $(shell echo '#') is legal. Previously the number sign needed to be escaped, for example: foo := $(shell echo '\#') Now this latter will resolve to "\#". If you want to write makefiles portable to both versions, assign the number sign to a variable: C := \# foo := $(shell echo '$C') This was claimed to be fixed in 3.81, but wasn't, for some reason. To detect this change search for 'nocomment' in the .FEATURES variable. This also fixes up the two make-cmd instances to replace # with $(pound) rather than with \#. There might very well be other places that need similar fixup in preparation for whatever future Make release contains the above change, but at least this builds an x86_64 defconfig with the new make. Link: https://bugzilla.kernel.org/show_bug.cgi?id=197847 Cc: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-08 21:35:28 +00:00
make-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1)))))
kbuild: consolidate command line escaping While the recent change to also escape # symbols when storing C-file compilation command lines was helpful, it should be in effect for all command lines, as much as the dollar escaping should be in effect for C-source compilation commands. Additionally, for better readability and maintenance, consolidating all the escaping (single quotes, dollars, and now sharps) was also desirable. Signed-Off-By: Jan Beulich <jbeulich@novell.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-01-30 09:04:27 +00:00
kbuild: drop $(wildcard $^) check in if_changed* for faster rebuild The incremental build of Linux kernel is pretty slow when lots of objects are compiled. The rebuild of allmodconfig may take a few minutes even when none of the objects needs to be rebuilt. The time-consuming part in the incremental build is the evaluation of if_changed* macros since they are used in the recipes to compile C and assembly source files into objects. I notice the following code in if_changed* is expensive: $(filter-out $(PHONY) $(wildcard $^),$^) In the incremental build, every object has its .*.cmd file, which contains the auto-generated list of included headers. So, $^ are expanded into the long list of the source file + included headers, and $(wildcard $^) checks whether they exist. It may not be clear why this check exists there. Here is the record of my research. [1] The first code addition into Kbuild This code dates back to 2002. It is the pre-git era. So, I copy-pasted it from the historical git tree. | commit 4a6db0791528c220655b063cf13fefc8470dbfee (HEAD) | Author: Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de> | Date: Mon Jun 17 00:22:37 2002 -0500 | | kbuild: Handle removed headers | | New and old way to handle dependencies would choke when a file | #include'd by other files was removed, since the dependency on it was | still recorded, but since it was gone, make has no idea what to do about | it (and would complain with "No rule to make <file> ...") | | We now add targets for all the previously included files, so make will | just ignore them if they disappear. | | diff --git a/Rules.make b/Rules.make | index 6ef827d3df39..7db5301ea7db 100644 | --- a/Rules.make | +++ b/Rules.make | @@ -446,7 +446,7 @@ if_changed = $(if $(strip $? \ | # execute the command and also postprocess generated .d dependencies | # file | | -if_changed_dep = $(if $(strip $? \ | +if_changed_dep = $(if $(strip $? $(filter-out FORCE $(wildcard $^),$^)\ | $(filter-out $(cmd_$(1)),$(cmd_$@))\ | $(filter-out $(cmd_$@),$(cmd_$(1)))),\ | @set -e; \ | diff --git a/scripts/fixdep.c b/scripts/fixdep.c | index b5d7bee8efc7..db45bd1888c0 100644 | --- a/scripts/fixdep.c | +++ b/scripts/fixdep.c | @@ -292,7 +292,7 @@ void parse_dep_file(void *map, size_t len) | exit(1); | } | memcpy(s, m, p-m); s[p-m] = 0; | - printf("%s: \\\n", target); | + printf("deps_%s := \\\n", target); | m = p+1; | | clear_config(); | @@ -314,7 +314,8 @@ void parse_dep_file(void *map, size_t len) | } | m = p + 1; | } | - printf("\n"); | + printf("\n%s: $(deps_%s)\n\n", target, target); | + printf("$(deps_%s):\n", target); | } | | void print_deps(void) The "No rule to make <file> ..." error can be solved by passing -MP to the compiler, but I think the detection of header removal is a good feature. When a header is removed, all source files that previously included it should be re-compiled. This makes sure we has correctly got rid of #include directives of it. This is also related with the behavior of $?. The GNU Make manual says: $? The names of all the prerequisites that are newer than the target, with spaces between them. This does not explain whether a non-existent prerequisite is considered to be newer than the target. At this point of time, GNU Make 3.7x was used, where the $? did not include non-existent prerequisites. Therefore, $(filter-out FORCE $(wildcard $^),$^) was useful to detect the header removal, and to rebuild the related objects if it is the case. [2] Change of $? behavior Later, the behavior of $? was changed (fixed) to include prerequisites that did not exist. First, GNU Make commit 64e16d6c00a5 ("Various changes getting ready for the release of 3.81.") changed it, but in the release test of 3.81, it turned out to break the kernel build. See these: - http://lists.gnu.org/archive/html/bug-make/2006-03/msg00003.html - https://savannah.gnu.org/bugs/?16002 - https://savannah.gnu.org/bugs/?16051 Then, GNU Make commit 6d8d9b74d9c5 ("Numerous updates to tests for issues found on Cygwin and Windows.") reverted it for the 3.81 release to give Linux kernel time to adjust to the new behavior. After the 3.81 release, GNU Make commit 7595f38f62af ("Fixed a number of documentation bugs, plus some build/install issues:") re-added it. [3] Adjustment to the new $? behavior on Kbuild side Meanwhile, the kernel build was changed by commit 4f1933620f57 ("kbuild: change kbuild to not rely on incorrect GNU make behavior") to adjust to the new $? behavior. [4] GNU Make 3.82 released in 2010 GNU Make 3.82 was the first release that integrated the correct $? behavior. At this point, Kbuild dealt with GNU Make versions with different $? behaviors. 3.81 or older: $? does not contain any non-existent prerequisite. $(filter-out $(PHONY) $(wildcard $^),$^) was useful to detect removed include headers. 3.82 or newer: $? contains non-existent prerequisites. When a header is removed, it appears in $?. $(filter-out $(PHONY) $(wildcard $^),$^) became a redundant check. With the correct $? behavior, we could have dropped the expensive check for 3.82 or later, but we did not. (Maybe nobody noticed this optimization.) [5] The .SECONDARY special target trips up $? Some time later, I noticed $? did not work as expected under some circumstances. As above, $? should contain non-existent prerequisites, but the ones specified as SECONDARY do not appear in $?. I asked this in GNU Make ML, and it seems a bug: https://lists.gnu.org/archive/html/bug-make/2019-01/msg00001.html Since commit 8e9b61b293d9 ("kbuild: move .SECONDARY special target to Kbuild.include"), all files, including headers listed in .*.cmd files, are treated as secondary. So, we are back into the incorrect $? behavior. If we Kbuild want to react to the header removal, we need to keep $(filter-out $(PHONY) $(wildcard $^),$^) but this makes the rebuild so slow. [Summary] - I believe noticing the header removal and recompiling related objects is a nice feature for the build system. - If $? worked correctly, $(filter-out $(PHONY),$?) would be enough to detect the header removal. - Currently, $? does not work correctly when used with .SECONDARY, and Kbuild is hit by this bug. - I filed a bug report for this, but not fixed yet as of writing. - Currently, the header removal is detected by the following expensive code: $(filter-out $(PHONY) $(wildcard $^),$^) - I do not want to revert commit 8e9b61b293d9 ("kbuild: move .SECONDARY special target to Kbuild.include"). Specifying .SECONDARY globally is clean, and it matches to the Kbuild policy. This commit proactively removes the expensive check since it makes the incremental build faster. A downside is Kbuild will no longer be able to notice the header removal. You can confirm it by the full-build followed by a header removal, and then re-build. $ make defconfig all [ full build ] $ rm include/linux/device.h $ make CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#11) Building modules, stage 2. MODPOST 12 modules Previously, Kbuild noticed a missing header and emits a build error. Now, Kbuild is fine with it. This is an unusual corner-case, not a big deal. Once the $? bug is fixed in GNU Make, everything will work fine. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-07 15:09:44 +00:00
# Find any prerequisites that are newer than target or that do not exist.
# (This is not true for now; $? should contain any non-existent prerequisites,
# but it does not work as expected when .SECONDARY is present. This seems a bug
# of GNU Make.)
kbuild: consistently decide when to rebuild a target Consistently decide when to rebuild a target across all of if_changed, if_changed_dep, if_changed_rule. PHONY targets are now treated alike (ignored) for all targets While add it make Kbuild.include almost readable by factoring out a few bits to some common variables and reuse this in Makefile.build. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-07-23 17:37:44 +00:00
# PHONY targets skipped in both cases.
kbuild: rename any-prereq to newer-prereqs GNU Make manual says: $? The names of all the prerequisites that are newer than the target, with spaces between them. To reflect this, rename any-prereq to newer-prereqs, which is clearer and more intuitive. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-07 15:09:45 +00:00
newer-prereqs = $(filter-out $(PHONY),$?)
kbuild: consistently decide when to rebuild a target Consistently decide when to rebuild a target across all of if_changed, if_changed_dep, if_changed_rule. PHONY targets are now treated alike (ignored) for all targets While add it make Kbuild.include almost readable by factoring out a few bits to some common variables and reuse this in Makefile.build. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-07-23 17:37:44 +00:00
kbuild: warn if FORCE is missing for if_changed(_dep,_rule) and filechk if_changed, if_changed_dep, and if_changed_rule must have FORCE as a prerequisite so the command line change is detected. Documentation/kbuild/makefiles.rst clearly explains it: Note: It is a typical mistake to forget the FORCE prerequisite. However, not all people follow the document. This mistake occurred again and again, so a compelling force is needed. Show a warning if FORCE is missing in the prerequisite of if_changed and friends. Same for filechk. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Tested-by: Nicolas Schier <n.schier@avm.de>
2021-08-13 06:30:05 +00:00
# It is a typical mistake to forget the FORCE prerequisite. Check it here so
# no more breakage will slip in.
check-FORCE = $(if $(filter FORCE, $^),,$(warning FORCE prerequisite is missing))
if-changed-cond = $(newer-prereqs)$(cmd-check)$(check-FORCE)
kbuild: macrofy the condition of if_changed and friends Add a new macro that expands into $(newer-prereqs)$(cmd-check). It makes it easier to add common code for if_changed, if_changed_dep, and if_changed_rule. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2021-08-13 06:30:04 +00:00
[PATCH] kbuild: improve option checking, Kbuild.include cleanup GNU binutils, root users, tmpfiles, external modules ro builds must be fixed to do the right thing now. Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Horst Schirmeier <horst@schirmeier.com> Cc: Jan Beulich <jbeulich@novell.com> Cc: Daniel Drake <dsd@gentoo.org> Cc: Andi Kleen <ak@suse.de> Cc: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Oleg Verych <olecom@flower.upol.cz> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-06 01:18:21 +00:00
# Execute command if command has changed or prerequisite(s) are updated.
kbuild: add cmd_and_savecmd macro Separate out the command execution part of if_changed, as we did for if_changed_dep. This allows us to reuse it in if_changed_rule. define rule_foo $(call cmd_and_savecmd,foo) $(call cmd,bar) endef Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Nicolas Schier <n.schier@avm.de> Tested-by: Sedat Dilek <sedat.dilek@gmail.com> # LLVM-14 (x86-64)
2022-05-27 10:01:54 +00:00
if_changed = $(if $(if-changed-cond),$(cmd_and_savecmd),@:)
cmd_and_savecmd = \
kbuild: refactor if_changed '@set -e; $(echo-cmd) $(cmd_$(1)' can be replaced with '$(cmd)'. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-30 01:05:29 +00:00
$(cmd); \
kbuild: add cmd_and_savecmd macro Separate out the command execution part of if_changed, as we did for if_changed_dep. This allows us to reuse it in if_changed_rule. define rule_foo $(call cmd_and_savecmd,foo) $(call cmd,bar) endef Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Nicolas Schier <n.schier@avm.de> Tested-by: Sedat Dilek <sedat.dilek@gmail.com> # LLVM-14 (x86-64)
2022-05-27 10:01:54 +00:00
printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
[PATCH] kbuild: improve option checking, Kbuild.include cleanup GNU binutils, root users, tmpfiles, external modules ro builds must be fixed to do the right thing now. Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Horst Schirmeier <horst@schirmeier.com> Cc: Jan Beulich <jbeulich@novell.com> Cc: Daniel Drake <dsd@gentoo.org> Cc: Andi Kleen <ak@suse.de> Cc: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Oleg Verych <olecom@flower.upol.cz> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-06 01:18:21 +00:00
# Execute the command and also postprocess generated .d dependencies file.
kbuild: macrofy the condition of if_changed and friends Add a new macro that expands into $(newer-prereqs)$(cmd-check). It makes it easier to add common code for if_changed, if_changed_dep, and if_changed_rule. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2021-08-13 06:30:04 +00:00
if_changed_dep = $(if $(if-changed-cond),$(cmd_and_fixdep),@:)
kbuild: add fine grained build dependencies for exported symbols Like with kconfig options, we now have the ability to compile in and out individual EXPORT_SYMBOL() declarations based on the content of include/generated/autoksyms.h. However we don't want the entire world to be rebuilt whenever that file is touched. Let's apply the same build dependency trick used for CONFIG_* symbols where the time stamp of empty files whose paths matching those symbols is used to trigger fine grained rebuilds. In our case the key is the symbol name passed to EXPORT_SYMBOL(). However, unlike config options, we cannot just use fixdep to parse the source code for EXPORT_SYMBOL(ksym) because several variants exist and parsing them all in a separate tool, and keeping it in synch, is not trivially maintainable. Furthermore, there are variants such as EXPORT_SYMBOL_GPL(pci_user_read_config_##size); that are instanciated via a macro for which we can't easily determine the actual exported symbol name(s) short of actually running the preprocessor on them. Storing the symbol name string in a special ELF section doesn't work for targets that output assembly or preprocessed source. So the best way is really to leverage the preprocessor by having it output actual symbol names anchored by a special sequence that can be easily filtered out. Then the list of symbols is simply fed to fixdep to be merged with the other dependencies. That implies the preprocessor is executed twice for each source file. A previous attempt relied on a warning pragma for each EXPORT_SYMBOL() instance that was filtered apart from stderr by the build system with a sed script during the actual compilation pass. Unfortunately the preprocessor/compiler diagnostic output isn't stable between versions and this solution, although more efficient, was deemed too fragile. Because of the lowercasing performed by fixdep, there might be name collisions triggering spurious rebuilds for similar symbols. But this shouldn't be a big issue in practice. (This is the case for CONFIG_* symbols and I didn't want to be different here, whatever the original reason for doing so.) To avoid needless build overhead, the exported symbol name gathering is performed only when CONFIG_TRIM_UNUSED_KSYMS is selected. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Rusty Russell <rusty@rustcorp.com.au>
2016-01-22 18:41:57 +00:00
kbuild: de-duplicate fixdep usage The generation and postprocessing of automatic dependency rules is duplicated in rule_cc_o_c, rule_as_o_S and if_changed_dep. Since this is not a trivial one-liner action, it is now abstracted under cmd_and_fixdep to simplify things and make future changes in this area easier. In the rule_cc_o_c and rule_as_o_S cases that means the order of some commands has been altered, namely fixdep and related file manipulations are executed earlier, but they didn't depend on those commands that now execute later. Signed-off-by: Nicolas Pitre <nico@linaro.org>
2016-02-17 20:50:06 +00:00
cmd_and_fixdep = \
kbuild: change if_changed_rule for multi-line recipe The 'define' ... 'endef' directive is useful to confine a series of shell commands into a single macro: define foo [action1] [action2] [action3] endif Each action is executed in a separate subshell. However, rule_cc_o_c and rule_as_o_S in scripts/Makefile.build are written as follows (with a trailing semicolon in each cmd_*): define rule_cc_o_c [action1] ; \ [action2] ; \ [action3] ; endef All shell commands are concatenated with '; \' so that it looks like a single command from the Makefile point of view. This does not exploit the benefits of 'define' ... 'endef' form because a single shell command can be more simply written, like this: rule_cc_o_c = \ [action1] ; \ [action2] ; \ [action3] ; I guess the intention for the command concatenation was to let the '@set -e' in if_changed_rule cover all the commands. We can improve the readability by moving '@set -e' to the 'cmd' macro. The combo of $(call echo-cmd,*) $(cmd_*) in rule_cc_o_c and rule_as_o_S have been replaced with $(call cmd,*). The trailing back-slashes have been removed. Here is a note about the performance: the commands in rule_cc_o_c and rule_as_o_S were previously executed all together in a single subshell, but now each line in a separate subshell. This means Make will spawn extra subshells [1]. I measured the build performance for x86_64_defconfig + CONFIG_MODVERSIONS + CONFIG_TRIM_UNUSED_KSYMS and I saw slight performance regression, but I believe code readability and maintainability wins. [1] Precisely, GNU Make may optimize this by executing the command directly instead of forking a subshell, if no shell special characters are found in the command line and omitting the subshell will not change the behavior. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-30 01:05:27 +00:00
$(cmd); \
kbuild: let fixdep directly write to .*.cmd files Currently, fixdep writes dependencies to .*.tmp, which is renamed to .*.cmd after everything succeeds. This is a very safe way to avoid corrupted .*.cmd files. The if_changed_dep has carried this safety mechanism since it was added in 2002. If fixdep fails for some reasons or a user terminates the build while fixdep is running, the incomplete output from the fixdep could be troublesome. This is my insight about some bad scenarios: [1] If the compiler succeeds to generate *.o file, but fixdep fails to write necessary dependencies to .*.cmd file, Make will miss to rebuild the object when headers or CONFIG options are changed. In this case, fixdep should not generate .*.cmd file at all so that 'arg-check' will surely trigger the rebuild of the object. [2] A partially constructed .*.cmd file may not be a syntactically correct makefile. The next time Make runs, it would include it, then fail to parse it. Once this happens, 'make clean' is be the only way to fix it. In fact, [1] is no longer a problem since commit 9c2af1c7377a ("kbuild: add .DELETE_ON_ERROR special target"). Make deletes a target file on any failure in its recipe. Because fixdep is a part of the recipe of *.o target, if it fails, the *.o is deleted anyway. However, I am a bit worried about the slight possibility of [2]. So, here is a solution. Let fixdep directly write to a .*.cmd file, but allow makefiles to include it only when its corresponding target exists. This effectively reverts commit 2982c953570b ("kbuild: remove redundant $(wildcard ...) for cmd_files calculation"), and commit 00d78ab2ba75 ("kbuild: remove dead code in cmd_files calculation in top Makefile") because now we must check the presence of targets. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-30 01:05:22 +00:00
scripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(dot-target).cmd;\
kbuild: remove trailing semicolon from cmd_* passed to if_changed_rule With the change of rule_cc_o_c / rule_as_o_S in the last commit, each command is executed in a separate subshell. Rip off unneeded semicolons. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-11-30 01:05:28 +00:00
rm -f $(depfile)
kbuild: add fine grained build dependencies for exported symbols Like with kconfig options, we now have the ability to compile in and out individual EXPORT_SYMBOL() declarations based on the content of include/generated/autoksyms.h. However we don't want the entire world to be rebuilt whenever that file is touched. Let's apply the same build dependency trick used for CONFIG_* symbols where the time stamp of empty files whose paths matching those symbols is used to trigger fine grained rebuilds. In our case the key is the symbol name passed to EXPORT_SYMBOL(). However, unlike config options, we cannot just use fixdep to parse the source code for EXPORT_SYMBOL(ksym) because several variants exist and parsing them all in a separate tool, and keeping it in synch, is not trivially maintainable. Furthermore, there are variants such as EXPORT_SYMBOL_GPL(pci_user_read_config_##size); that are instanciated via a macro for which we can't easily determine the actual exported symbol name(s) short of actually running the preprocessor on them. Storing the symbol name string in a special ELF section doesn't work for targets that output assembly or preprocessed source. So the best way is really to leverage the preprocessor by having it output actual symbol names anchored by a special sequence that can be easily filtered out. Then the list of symbols is simply fed to fixdep to be merged with the other dependencies. That implies the preprocessor is executed twice for each source file. A previous attempt relied on a warning pragma for each EXPORT_SYMBOL() instance that was filtered apart from stderr by the build system with a sed script during the actual compilation pass. Unfortunately the preprocessor/compiler diagnostic output isn't stable between versions and this solution, although more efficient, was deemed too fragile. Because of the lowercasing performed by fixdep, there might be name collisions triggering spurious rebuilds for similar symbols. But this shouldn't be a big issue in practice. (This is the case for CONFIG_* symbols and I didn't want to be different here, whatever the original reason for doing so.) To avoid needless build overhead, the exported symbol name gathering is performed only when CONFIG_TRIM_UNUSED_KSYMS is selected. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Rusty Russell <rusty@rustcorp.com.au>
2016-01-22 18:41:57 +00:00
kbuild: introduce Kbuild.include Kbuild.include is a placeholder for definitions originally present in both the top-level Makefile and scripts/Makefile.build. There were a slight difference in the filechk definition, so the most videly used version was kept and usr/Makefile was adopted for this syntax. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ---
2005-07-25 20:10:36 +00:00
# Usage: $(call if_changed_rule,foo)
[PATCH] kbuild: more Makefile cleanups This adds the remaining changes which should have been part of the review process. - the define command is inappropriate (it's primarily for rule definitions) - execute commands in the current dir as all other commands - .*.tmp (but not .*.null) files are also removed up by "make clean" - printf has other side effects, just use "echo -e" - proper quoting - proper indentation Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-02-08 21:48:51 +00:00
# Will check if $(cmd_foo) or any of the prerequisites changed,
# and if so will execute $(rule_foo).
kbuild: macrofy the condition of if_changed and friends Add a new macro that expands into $(newer-prereqs)$(cmd-check). It makes it easier to add common code for if_changed, if_changed_dep, and if_changed_rule. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2021-08-13 06:30:04 +00:00
if_changed_rule = $(if $(if-changed-cond),$(rule_$(1)),@:)
kbuild: consistently decide when to rebuild a target Consistently decide when to rebuild a target across all of if_changed, if_changed_dep, if_changed_rule. PHONY targets are now treated alike (ignored) for all targets While add it make Kbuild.include almost readable by factoring out a few bits to some common variables and reuse this in Makefile.build. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-07-23 17:37:44 +00:00
kbuild: make V=2 tell why a target is rebuild tell why a a target got build enabled by make V=2 Output (listed in the order they are checked): (1) - due to target is PHONY (2) - due to target missing (3) - due to: file1.h file2.h (4) - due to command line change (5) - due to missing .cmd file (6) - due to target not in $(targets) (1) We always build PHONY targets (2) No target, so we better build it (3) Prerequisite is newer than target (4) The command line stored in the file named dir/.target.cmd differed from actual command line. This happens when compiler options changes (5) No dir/.target.cmd file (used to store command line) (6) No dir/.target.cmd file and target not listed in $(targets) This is a good hint that there is a bug in the kbuild file This patch is inspired by a patch from: Milton Miller <miltonm@bga.com> Cc: Milton Miller <miltonm@bga.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-08-08 19:35:14 +00:00
###
kbuild: trivial cleanups on the comments This is a bunch of trivial fixes and cleanups. Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-02 02:31:06 +00:00
# why - tell why a target got built
kbuild: make V=2 tell why a target is rebuild tell why a a target got build enabled by make V=2 Output (listed in the order they are checked): (1) - due to target is PHONY (2) - due to target missing (3) - due to: file1.h file2.h (4) - due to command line change (5) - due to missing .cmd file (6) - due to target not in $(targets) (1) We always build PHONY targets (2) No target, so we better build it (3) Prerequisite is newer than target (4) The command line stored in the file named dir/.target.cmd differed from actual command line. This happens when compiler options changes (5) No dir/.target.cmd file (used to store command line) (6) No dir/.target.cmd file and target not listed in $(targets) This is a good hint that there is a bug in the kbuild file This patch is inspired by a patch from: Milton Miller <miltonm@bga.com> Cc: Milton Miller <miltonm@bga.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-08-08 19:35:14 +00:00
# enabled by make V=2
# Output (listed in the order they are checked):
# (1) - due to target is PHONY
# (2) - due to target missing
# (3) - due to: file1.h file2.h
# (4) - due to command line change
# (5) - due to missing .cmd file
# (6) - due to target not in $(targets)
# (1) PHONY targets are always build
# (2) No target, so we better build it
# (3) Prerequisite is newer than target
# (4) The command line stored in the file named dir/.target.cmd
# differed from actual command line. This happens when compiler
# options changes
# (5) No dir/.target.cmd file (used to store command line)
# (6) No dir/.target.cmd file and target not listed in $(targets)
# This is a good hint that there is a bug in the kbuild file
ifeq ($(KBUILD_VERBOSE),2)
why = \
$(if $(filter $@, $(PHONY)),- due to target is PHONY, \
$(if $(wildcard $@), \
kbuild: rename any-prereq to newer-prereqs GNU Make manual says: $? The names of all the prerequisites that are newer than the target, with spaces between them. To reflect this, rename any-prereq to newer-prereqs, which is clearer and more intuitive. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-11-07 15:09:45 +00:00
$(if $(newer-prereqs),- due to: $(newer-prereqs), \
kbuild: rename arg-check to cmd-check I prefer 'cmd-check' for consistency. We have 'echo-cmd', 'cmd', 'cmd_and_fixdep', etc. in this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-22 16:07:03 +00:00
$(if $(cmd-check), \
kbuild: make V=2 tell why a target is rebuild tell why a a target got build enabled by make V=2 Output (listed in the order they are checked): (1) - due to target is PHONY (2) - due to target missing (3) - due to: file1.h file2.h (4) - due to command line change (5) - due to missing .cmd file (6) - due to target not in $(targets) (1) We always build PHONY targets (2) No target, so we better build it (3) Prerequisite is newer than target (4) The command line stored in the file named dir/.target.cmd differed from actual command line. This happens when compiler options changes (5) No dir/.target.cmd file (used to store command line) (6) No dir/.target.cmd file and target not listed in $(targets) This is a good hint that there is a bug in the kbuild file This patch is inspired by a patch from: Milton Miller <miltonm@bga.com> Cc: Milton Miller <miltonm@bga.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2006-08-08 19:35:14 +00:00
$(if $(cmd_$@),- due to command line change, \
$(if $(filter $@, $(targets)), \
- due to missing .cmd file, \
- due to $(notdir $@) not in $$(targets) \
) \
) \
) \
), \
- due to target missing \
) \
)
echo-why = $(call escsq, $(strip $(why)))
endif
modsign: Handle signing key in source tree Since commit 1329e8cc69 ("modsign: Extract signing cert from CONFIG_MODULE_SIG_KEY if needed"), the build system has carefully coped with the signing key being specified as a relative path in either the source or or the build trees. However, the actual signing of modules has not worked if the filename is relative to the source tree. Fix that by moving the config_filename helper into scripts/Kbuild.include so that it can be used from elsewhere, and then using it in the top-level Makefile to find the signing key file. Kill the intermediate $(MODPUBKEY) and $(MODSECKEY) variables too, while we're at it. There's no need for them. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: David Howells <dhowells@redhat.com>
2015-08-14 15:17:16 +00:00
###############################################################################
kbuild: add .DELETE_ON_ERROR special target If Make gets a fatal signal while a shell is executing, it may delete the target file that the recipe was supposed to update. This is needed to make sure that it is remade from scratch when Make is next run; if Make is interrupted after the recipe has begun to write the target file, it results in an incomplete file whose time stamp is newer than that of the prerequisites files. Make automatically deletes the incomplete file on interrupt unless the target is marked .PRECIOUS. The situation is just the same as when the shell fails for some reasons. Usually when a recipe line fails, if it has changed the target file at all, the file is corrupted, or at least it is not completely updated. Yet the file’s time stamp says that it is now up to date, so the next time Make runs, it will not try to update that file. However, Make does not cater to delete the incomplete target file in this case. We need to add .DELETE_ON_ERROR somewhere in the Makefile to request it. scripts/Kbuild.include seems a suitable place to add it because it is included from almost all sub-makes. Please note .DELETE_ON_ERROR is not effective for phony targets. The external module building should never ever touch the kernel tree. The following recipe fails if include/generated/autoconf.h is missing. However, include/config/auto.conf is not deleted since it is a phony target. PHONY += include/config/auto.conf include/config/auto.conf: $(Q)test -e include/generated/autoconf.h -a -e $@ || ( \ echo >&2; \ echo >&2 " ERROR: Kernel configuration is invalid."; \ echo >&2 " include/generated/autoconf.h or $@ are missing.";\ echo >&2 " Run 'make oldconfig && make prepare' on kernel src to fix it."; \ echo >&2 ; \ /bin/false) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-20 07:46:33 +00:00
# delete partially updated (i.e. corrupted) files on error
.DELETE_ON_ERROR:
kbuild: move .SECONDARY special target to Kbuild.include In commit 54a702f70589 ("kbuild: mark $(targets) as .SECONDARY and remove .PRECIOUS markers"), I missed one important feature of the .SECONDARY target: .SECONDARY with no prerequisites causes all targets to be treated as secondary. ... which agrees with the policy of Kbuild. Let's move it to scripts/Kbuild.include, with no prerequisites. Note: If an intermediate file is generated by $(call if_changed,...), you still need to add it to "targets" so its .*.cmd file is included. The arm/arm64 crypto files are generated by $(call cmd,shipped), so they do not need to be added to "targets", but need to be added to "clean-files" so "make clean" can properly clean them away. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-01 00:27:15 +00:00
# do not delete intermediate files automatically
.SECONDARY:
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