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217 lines
6.2 KiB
C
217 lines
6.2 KiB
C
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/*
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* Shared Atheros AR9170 Header
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*
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* EEPROM layout
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*
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* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, see
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* http://www.gnu.org/licenses/.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* Copyright (c) 2007-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __CARL9170_SHARED_EEPROM_H
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#define __CARL9170_SHARED_EEPROM_H
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#define AR9170_EEPROM_START 0x1600
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#define AR5416_MAX_CHAINS 2
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#define AR5416_MODAL_SPURS 5
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struct ar9170_eeprom_modal {
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__le32 antCtrlChain[AR5416_MAX_CHAINS];
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__le32 antCtrlCommon;
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s8 antennaGainCh[AR5416_MAX_CHAINS];
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u8 switchSettling;
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u8 txRxAttenCh[AR5416_MAX_CHAINS];
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u8 rxTxMarginCh[AR5416_MAX_CHAINS];
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s8 adcDesiredSize;
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s8 pgaDesiredSize;
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u8 xlnaGainCh[AR5416_MAX_CHAINS];
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u8 txEndToXpaOff;
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u8 txEndToRxOn;
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u8 txFrameToXpaOn;
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u8 thresh62;
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s8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
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u8 xpdGain;
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u8 xpd;
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s8 iqCalICh[AR5416_MAX_CHAINS];
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s8 iqCalQCh[AR5416_MAX_CHAINS];
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u8 pdGainOverlap;
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u8 ob;
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u8 db;
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u8 xpaBiasLvl;
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u8 pwrDecreaseFor2Chain;
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u8 pwrDecreaseFor3Chain;
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u8 txFrameToDataStart;
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u8 txFrameToPaOn;
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u8 ht40PowerIncForPdadc;
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u8 bswAtten[AR5416_MAX_CHAINS];
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u8 bswMargin[AR5416_MAX_CHAINS];
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u8 swSettleHt40;
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u8 reserved[22];
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struct spur_channel {
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__le16 spurChan;
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u8 spurRangeLow;
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u8 spurRangeHigh;
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} __packed spur_channels[AR5416_MODAL_SPURS];
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} __packed;
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#define AR5416_NUM_PD_GAINS 4
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#define AR5416_PD_GAIN_ICEPTS 5
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struct ar9170_calibration_data_per_freq {
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u8 pwr_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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u8 vpd_pdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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} __packed;
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#define AR5416_NUM_5G_CAL_PIERS 8
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#define AR5416_NUM_2G_CAL_PIERS 4
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#define AR5416_NUM_5G_TARGET_PWRS 8
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#define AR5416_NUM_2G_CCK_TARGET_PWRS 3
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#define AR5416_NUM_2G_OFDM_TARGET_PWRS 4
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#define AR5416_MAX_NUM_TGT_PWRS 8
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struct ar9170_calibration_target_power_legacy {
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u8 freq;
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u8 power[4];
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} __packed;
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struct ar9170_calibration_target_power_ht {
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u8 freq;
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u8 power[8];
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} __packed;
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#define AR5416_NUM_CTLS 24
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struct ar9170_calctl_edges {
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u8 channel;
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#define AR9170_CALCTL_EDGE_FLAGS 0xC0
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u8 power_flags;
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} __packed;
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#define AR5416_NUM_BAND_EDGES 8
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struct ar9170_calctl_data {
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struct ar9170_calctl_edges
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control_edges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
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} __packed;
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struct ar9170_eeprom {
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__le16 length;
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__le16 checksum;
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__le16 version;
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u8 operating_flags;
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#define AR9170_OPFLAG_5GHZ 1
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#define AR9170_OPFLAG_2GHZ 2
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u8 misc;
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__le16 reg_domain[2];
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u8 mac_address[6];
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u8 rx_mask;
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u8 tx_mask;
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__le16 rf_silent;
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__le16 bluetooth_options;
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__le16 device_capabilities;
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__le32 build_number;
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u8 deviceType;
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u8 reserved[33];
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u8 customer_data[64];
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struct ar9170_eeprom_modal
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modal_header[2];
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u8 cal_freq_pier_5G[AR5416_NUM_5G_CAL_PIERS];
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u8 cal_freq_pier_2G[AR5416_NUM_2G_CAL_PIERS];
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struct ar9170_calibration_data_per_freq
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cal_pier_data_5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS],
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cal_pier_data_2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
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/* power calibration data */
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struct ar9170_calibration_target_power_legacy
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cal_tgt_pwr_5G[AR5416_NUM_5G_TARGET_PWRS];
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struct ar9170_calibration_target_power_ht
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cal_tgt_pwr_5G_ht20[AR5416_NUM_5G_TARGET_PWRS],
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cal_tgt_pwr_5G_ht40[AR5416_NUM_5G_TARGET_PWRS];
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struct ar9170_calibration_target_power_legacy
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cal_tgt_pwr_2G_cck[AR5416_NUM_2G_CCK_TARGET_PWRS],
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cal_tgt_pwr_2G_ofdm[AR5416_NUM_2G_OFDM_TARGET_PWRS];
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struct ar9170_calibration_target_power_ht
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cal_tgt_pwr_2G_ht20[AR5416_NUM_2G_OFDM_TARGET_PWRS],
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cal_tgt_pwr_2G_ht40[AR5416_NUM_2G_OFDM_TARGET_PWRS];
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/* conformance testing limits */
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u8 ctl_index[AR5416_NUM_CTLS];
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struct ar9170_calctl_data
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ctl_data[AR5416_NUM_CTLS];
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u8 pad;
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__le16 subsystem_id;
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} __packed;
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#define AR9170_LED_MODE_POWER_ON 0x0001
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#define AR9170_LED_MODE_RESERVED 0x0002
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#define AR9170_LED_MODE_DISABLE_STATE 0x0004
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#define AR9170_LED_MODE_OFF_IN_PSM 0x0008
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/* AR9170_LED_MODE BIT is set */
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#define AR9170_LED_MODE_FREQUENCY_S 4
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#define AR9170_LED_MODE_FREQUENCY 0x0030
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#define AR9170_LED_MODE_FREQUENCY_1HZ 0x0000
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#define AR9170_LED_MODE_FREQUENCY_0_5HZ 0x0010
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#define AR9170_LED_MODE_FREQUENCY_0_25HZ 0x0020
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#define AR9170_LED_MODE_FREQUENCY_0_125HZ 0x0030
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/* AR9170_LED_MODE BIT is not set */
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#define AR9170_LED_MODE_CONN_STATE_S 4
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#define AR9170_LED_MODE_CONN_STATE 0x0030
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#define AR9170_LED_MODE_CONN_STATE_FORCE_OFF 0x0000
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#define AR9170_LED_MODE_CONN_STATE_FORCE_ON 0x0010
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/* Idle off / Active on */
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#define AR9170_LED_MODE_CONN_STATE_IOFF_AON 0x0020
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/* Idle on / Active off */
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#define AR9170_LED_MODE_CONN_STATE_ION_AOFF 0x0010
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#define AR9170_LED_MODE_MODE 0x0040
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#define AR9170_LED_MODE_RESERVED2 0x0080
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#define AR9170_LED_MODE_TON_SCAN_S 8
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#define AR9170_LED_MODE_TON_SCAN 0x0f00
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#define AR9170_LED_MODE_TOFF_SCAN_S 12
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#define AR9170_LED_MODE_TOFF_SCAN 0xf000
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struct ar9170_led_mode {
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__le16 led;
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};
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#endif /* __CARL9170_SHARED_EEPROM_H */
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