[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 20:45:02 +00:00
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/*
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2008-08-05 15:14:15 +00:00
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* arch/arm/mach-loki/include/mach/irqs.h
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[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 20:45:02 +00:00
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*
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* IRQ definitions for Marvell Loki (88RC8480) SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H
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#include "loki.h" /* need GPIO_MAX */
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/*
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* Interrupt Controller
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*/
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#define IRQ_LOKI_PCIE_A_CPU_DRBL 0
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#define IRQ_LOKI_CPU_PCIE_A_DRBL 1
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#define IRQ_LOKI_PCIE_B_CPU_DRBL 2
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#define IRQ_LOKI_CPU_PCIE_B_DRBL 3
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#define IRQ_LOKI_COM_A_ERR 6
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#define IRQ_LOKI_COM_A_IN 7
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#define IRQ_LOKI_COM_A_OUT 8
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#define IRQ_LOKI_COM_B_ERR 9
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#define IRQ_LOKI_COM_B_IN 10
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#define IRQ_LOKI_COM_B_OUT 11
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#define IRQ_LOKI_DMA_A 12
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#define IRQ_LOKI_DMA_B 13
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#define IRQ_LOKI_SAS_A 14
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#define IRQ_LOKI_SAS_B 15
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#define IRQ_LOKI_DDR 16
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#define IRQ_LOKI_XOR 17
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#define IRQ_LOKI_BRIDGE 18
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#define IRQ_LOKI_PCIE_A_ERR 20
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#define IRQ_LOKI_PCIE_A_INT 21
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#define IRQ_LOKI_PCIE_B_ERR 22
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#define IRQ_LOKI_PCIE_B_INT 23
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#define IRQ_LOKI_GBE_A_INT 24
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#define IRQ_LOKI_GBE_B_INT 25
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#define IRQ_LOKI_DEV_ERR 26
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#define IRQ_LOKI_UART0 27
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#define IRQ_LOKI_UART1 28
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#define IRQ_LOKI_TWSI 29
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#define IRQ_LOKI_GPIO_23_0 30
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#define IRQ_LOKI_GPIO_25_24 31
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/*
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* Loki General Purpose Pins
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*/
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#define IRQ_LOKI_GPIO_START 32
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#define NR_GPIO_IRQS GPIO_MAX
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#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
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#endif
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