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linux/arch/blackfin/mach-bf561/include/mach/portmux.h

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Blackfin: mass clean up of copyright/licensing info Bill Gatliff & David Brownell pointed out we were missing some copyrights, and licensing terms in some of the files in ./arch/blackfin, so this fixes things, and cleans them up. It also removes: - verbose GPL text(refer to the top level ./COPYING file) - file names (you are looking at the file) - bug url (it's in the ./MAINTAINERS file) - "or later" on GPL-2, when we did not have that right It also allows some Blackfin-specific assembly files to be under a BSD like license (for people to use them outside of Linux). Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-24 14:11:24 +00:00
/*
* Copyright 2007-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
Blackfin arch: Add Support for Peripheral PortMux and resouce allocation Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-12 04:32:52 +00:00
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
[Blackfin] arch: Fix gpio label handling early serial init also utilizes the peripheral request api - however at this point bfin_gpio_init didn't allocate memory for the labels. So we always have two zombies (allocated pin functions without labels) This happens before the initcalls - We now allocate memory statically. Define MAX_RESOURCES individually for each cpu. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-12-24 12:07:03 +00:00
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
Blackfin arch: Add Support for Peripheral PortMux and resouce allocation Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-12 04:32:52 +00:00
#define P_PPI0_CLK (P_DONTCARE)
#define P_PPI0_FS1 (P_DONTCARE)
#define P_PPI0_FS2 (P_DONTCARE)
#define P_PPI0_FS3 (P_DONTCARE)
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
#define P_PPI0_D0 (P_DONTCARE)
#define P_PPI0_D1 (P_DONTCARE)
#define P_PPI0_D2 (P_DONTCARE)
#define P_PPI0_D3 (P_DONTCARE)
#define P_PPI0_D4 (P_DONTCARE)
#define P_PPI0_D5 (P_DONTCARE)
#define P_PPI0_D6 (P_DONTCARE)
#define P_PPI0_D7 (P_DONTCARE)
#define P_PPI1_CLK (P_DONTCARE)
#define P_PPI1_FS1 (P_DONTCARE)
#define P_PPI1_FS2 (P_DONTCARE)
#define P_PPI1_FS3 (P_DONTCARE)
#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
#define P_PPI1_D0 (P_DONTCARE)
#define P_PPI1_D1 (P_DONTCARE)
#define P_PPI1_D2 (P_DONTCARE)
#define P_PPI1_D3 (P_DONTCARE)
#define P_PPI1_D4 (P_DONTCARE)
#define P_PPI1_D5 (P_DONTCARE)
#define P_PPI1_D6 (P_DONTCARE)
#define P_PPI1_D7 (P_DONTCARE)
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
#define P_SPORT1_DRPRI (P_DONTCARE)
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
#define P_SPORT0_DRPRI (P_DONTCARE)
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
#define P_TMR11 (P_DONTCARE)
#define P_TMR10 (P_DONTCARE)
#define P_TMR9 (P_DONTCARE)
#define P_TMR8 (P_DONTCARE)
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
#define P_SPI0_MOSI (P_DONTCARE)
Blackfin arch: fix bugs report by Andy Liu <yjhsou@gmail.com>, AD1836 can't be probed in BF561-EZ Cc: Andy Liu <yjhsou@gmail.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-08-05 07:43:03 +00:00
#define P_SPI0_MISO (P_DONTCARE)
Blackfin arch: Add Support for Peripheral PortMux and resouce allocation Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-12 04:32:52 +00:00
#define P_SPI0_SCK (P_DONTCARE)
Blackfin arch: Fix bug - Run "reboot" hangs bf518-ezbrd [Mike Frysinger <vapier.adi@gmail.com>: - setup P_DEFAULT_BOOT_SPI_CS for every arch based on the default bootrom behavior and convert all our boards to it - revert previous anomaly change ... bf51x is not affected by anomaly 05000353] Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-02-04 08:49:45 +00:00
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
Blackfin arch: Add Support for Peripheral PortMux and resouce allocation Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-12 04:32:52 +00:00
#endif /* _MACH_PORTMUX_H_ */
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