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374 lines
10 KiB
ArmAsm
374 lines
10 KiB
ArmAsm
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/* head-mmu-fr451.S: FR451 mmu-linux specific bits of initialisation
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <linux/linkage.h>
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#include <asm/ptrace.h>
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#include <asm/page.h>
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#include <asm/mem-layout.h>
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#include <asm/spr-regs.h>
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#include <asm/mb86943a.h>
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#include "head.inc"
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#define __400_DBR0 0xfe000e00
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#define __400_DBR1 0xfe000e08
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#define __400_DBR2 0xfe000e10
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#define __400_DBR3 0xfe000e18
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#define __400_DAM0 0xfe000f00
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#define __400_DAM1 0xfe000f08
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#define __400_DAM2 0xfe000f10
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#define __400_DAM3 0xfe000f18
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#define __400_LGCR 0xfe000010
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#define __400_LCR 0xfe000100
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#define __400_LSBR 0xfe000c00
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.section .text.init,"ax"
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.balign 4
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###############################################################################
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#
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# describe the position and layout of the SDRAM controller registers
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#
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# ENTRY: EXIT:
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# GR5 - cacheline size
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# GR11 - displacement of 2nd SDRAM addr reg from GR14
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# GR12 - displacement of 3rd SDRAM addr reg from GR14
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# GR13 - displacement of 4th SDRAM addr reg from GR14
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# GR14 - address of 1st SDRAM addr reg
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# GR15 - amount to shift address by to match SDRAM addr reg
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# GR26 &__head_reference [saved]
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# GR30 LED address [saved]
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# CC0 - T if DBR0 is present
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# CC1 - T if DBR1 is present
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# CC2 - T if DBR2 is present
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# CC3 - T if DBR3 is present
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#
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###############################################################################
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.globl __head_fr451_describe_sdram
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__head_fr451_describe_sdram:
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sethi.p %hi(__400_DBR0),gr14
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setlo %lo(__400_DBR0),gr14
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setlos.p #__400_DBR1-__400_DBR0,gr11
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setlos #__400_DBR2-__400_DBR0,gr12
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setlos.p #__400_DBR3-__400_DBR0,gr13
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setlos #32,gr5 ; cacheline size
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setlos.p #0,gr15 ; amount to shift addr reg by
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setlos #0x00ff,gr4
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movgs gr4,cccr ; extant DARS/DAMK regs
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bralr
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###############################################################################
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#
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# rearrange the bus controller registers
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#
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# ENTRY: EXIT:
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# GR26 &__head_reference [saved]
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# GR30 LED address revised LED address
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#
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###############################################################################
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.globl __head_fr451_set_busctl
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__head_fr451_set_busctl:
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sethi.p %hi(__400_LGCR),gr4
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setlo %lo(__400_LGCR),gr4
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sethi.p %hi(__400_LSBR),gr10
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setlo %lo(__400_LSBR),gr10
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sethi.p %hi(__400_LCR),gr11
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setlo %lo(__400_LCR),gr11
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# set the bus controller
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ldi @(gr4,#0),gr5
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ori gr5,#0xff,gr5 ; make sure all chip-selects are enabled
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sti gr5,@(gr4,#0)
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sethi.p %hi(__region_CS1),gr4
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setlo %lo(__region_CS1),gr4
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sethi.p %hi(__region_CS1_M),gr5
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setlo %lo(__region_CS1_M),gr5
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sethi.p %hi(__region_CS1_C),gr6
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setlo %lo(__region_CS1_C),gr6
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sti gr4,@(gr10,#1*0x08)
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sti gr5,@(gr10,#1*0x08+0x100)
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sti gr6,@(gr11,#1*0x08)
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sethi.p %hi(__region_CS2),gr4
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setlo %lo(__region_CS2),gr4
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sethi.p %hi(__region_CS2_M),gr5
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setlo %lo(__region_CS2_M),gr5
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sethi.p %hi(__region_CS2_C),gr6
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setlo %lo(__region_CS2_C),gr6
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sti gr4,@(gr10,#2*0x08)
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sti gr5,@(gr10,#2*0x08+0x100)
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sti gr6,@(gr11,#2*0x08)
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sethi.p %hi(__region_CS3),gr4
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setlo %lo(__region_CS3),gr4
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sethi.p %hi(__region_CS3_M),gr5
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setlo %lo(__region_CS3_M),gr5
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sethi.p %hi(__region_CS3_C),gr6
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setlo %lo(__region_CS3_C),gr6
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sti gr4,@(gr10,#3*0x08)
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sti gr5,@(gr10,#3*0x08+0x100)
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sti gr6,@(gr11,#3*0x08)
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sethi.p %hi(__region_CS4),gr4
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setlo %lo(__region_CS4),gr4
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sethi.p %hi(__region_CS4_M),gr5
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setlo %lo(__region_CS4_M),gr5
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sethi.p %hi(__region_CS4_C),gr6
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setlo %lo(__region_CS4_C),gr6
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sti gr4,@(gr10,#4*0x08)
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sti gr5,@(gr10,#4*0x08+0x100)
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sti gr6,@(gr11,#4*0x08)
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sethi.p %hi(__region_CS5),gr4
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setlo %lo(__region_CS5),gr4
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sethi.p %hi(__region_CS5_M),gr5
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setlo %lo(__region_CS5_M),gr5
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sethi.p %hi(__region_CS5_C),gr6
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setlo %lo(__region_CS5_C),gr6
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sti gr4,@(gr10,#5*0x08)
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sti gr5,@(gr10,#5*0x08+0x100)
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sti gr6,@(gr11,#5*0x08)
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sethi.p %hi(__region_CS6),gr4
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setlo %lo(__region_CS6),gr4
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sethi.p %hi(__region_CS6_M),gr5
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setlo %lo(__region_CS6_M),gr5
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sethi.p %hi(__region_CS6_C),gr6
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setlo %lo(__region_CS6_C),gr6
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sti gr4,@(gr10,#6*0x08)
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sti gr5,@(gr10,#6*0x08+0x100)
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sti gr6,@(gr11,#6*0x08)
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sethi.p %hi(__region_CS7),gr4
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setlo %lo(__region_CS7),gr4
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sethi.p %hi(__region_CS7_M),gr5
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setlo %lo(__region_CS7_M),gr5
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sethi.p %hi(__region_CS7_C),gr6
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setlo %lo(__region_CS7_C),gr6
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sti gr4,@(gr10,#7*0x08)
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sti gr5,@(gr10,#7*0x08+0x100)
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sti gr6,@(gr11,#7*0x08)
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membar
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bar
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# adjust LED bank address
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#ifdef CONFIG_MB93091_VDK
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sethi.p %hi(__region_CS2 + 0x01200004),gr30
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setlo %lo(__region_CS2 + 0x01200004),gr30
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#endif
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bralr
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###############################################################################
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#
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# determine the total SDRAM size
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#
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# ENTRY: EXIT:
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# GR25 - SDRAM size
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# GR26 &__head_reference [saved]
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# GR30 LED address [saved]
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#
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###############################################################################
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.globl __head_fr451_survey_sdram
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__head_fr451_survey_sdram:
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sethi.p %hi(__400_DAM0),gr11
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setlo %lo(__400_DAM0),gr11
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sethi.p %hi(__400_DBR0),gr12
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setlo %lo(__400_DBR0),gr12
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sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
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setlo %lo(0xfe000000),gr17
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setlos #0,gr25
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ldi @(gr12,#0x00),gr4 ; DAR0
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subcc gr4,gr17,gr0,icc0
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beq icc0,#0,__head_no_DCS0
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ldi @(gr11,#0x00),gr6 ; DAM0: bits 31:20 match addr 31:20
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add gr25,gr6,gr25
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addi gr25,#1,gr25
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__head_no_DCS0:
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ldi @(gr12,#0x08),gr4 ; DAR1
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subcc gr4,gr17,gr0,icc0
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beq icc0,#0,__head_no_DCS1
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ldi @(gr11,#0x08),gr6 ; DAM1: bits 31:20 match addr 31:20
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add gr25,gr6,gr25
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addi gr25,#1,gr25
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__head_no_DCS1:
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ldi @(gr12,#0x10),gr4 ; DAR2
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subcc gr4,gr17,gr0,icc0
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beq icc0,#0,__head_no_DCS2
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ldi @(gr11,#0x10),gr6 ; DAM2: bits 31:20 match addr 31:20
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add gr25,gr6,gr25
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addi gr25,#1,gr25
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__head_no_DCS2:
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ldi @(gr12,#0x18),gr4 ; DAR3
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subcc gr4,gr17,gr0,icc0
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beq icc0,#0,__head_no_DCS3
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ldi @(gr11,#0x18),gr6 ; DAM3: bits 31:20 match addr 31:20
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add gr25,gr6,gr25
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addi gr25,#1,gr25
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__head_no_DCS3:
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bralr
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###############################################################################
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#
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# set the protection map with the I/DAMPR registers
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#
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# ENTRY: EXIT:
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# GR25 SDRAM size [saved]
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# GR26 &__head_reference [saved]
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# GR30 LED address [saved]
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#
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#
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# Using this map:
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# REGISTERS ADDRESS RANGE VIEW
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# =============== ====================== ===============================
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# IAMPR0/DAMPR0 0xC0000000-0xCFFFFFFF Cached kernel RAM Window
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# DAMPR11 0xE0000000-0xFFFFFFFF Uncached I/O
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#
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###############################################################################
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.globl __head_fr451_set_protection
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__head_fr451_set_protection:
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movsg lr,gr27
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# set the I/O region protection registers for FR451 in MMU mode
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#define PGPROT_IO xAMPRx_L|xAMPRx_M|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V
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sethi.p %hi(__region_IO),gr5
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setlo %lo(__region_IO),gr5
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setlos #PGPROT_IO|xAMPRx_SS_512Mb,gr4
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or gr4,gr5,gr4
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movgs gr5,damlr11 ; General I/O tile
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movgs gr4,dampr11
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# need to open a window onto at least part of the RAM for the kernel's use
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sethi.p %hi(__sdram_base),gr8
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setlo %lo(__sdram_base),gr8 ; physical address
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sethi.p %hi(__page_offset),gr9
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setlo %lo(__page_offset),gr9 ; virtual address
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setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_256Mb|xAMPRx_S_KERNEL|xAMPRx_V,gr11
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or gr8,gr11,gr8
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movgs gr9,iamlr0 ; mapped from real address 0
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movgs gr8,iampr0 ; cached kernel memory at 0xC0000000
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movgs gr9,damlr0
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movgs gr8,dampr0
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# set a temporary mapping for the kernel running at address 0 until we've turned on the MMU
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sethi.p %hi(__sdram_base),gr9
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setlo %lo(__sdram_base),gr9 ; virtual address
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and.p gr4,gr11,gr4
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and gr5,gr11,gr5
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or.p gr4,gr11,gr4
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or gr5,gr11,gr5
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movgs gr9,iamlr1 ; mapped from real address 0
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movgs gr8,iampr1 ; cached kernel memory at 0x00000000
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movgs gr9,damlr1
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movgs gr8,dampr1
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# we use DAMR2-10 for kmap_atomic(), cache flush and TLB management
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# since the DAMLR regs are not going to change, we can set them now
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# also set up IAMLR2 to the same as DAMLR5
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sethi.p %hi(KMAP_ATOMIC_PRIMARY_FRAME),gr4
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setlo %lo(KMAP_ATOMIC_PRIMARY_FRAME),gr4
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sethi.p %hi(PAGE_SIZE),gr5
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setlo %lo(PAGE_SIZE),gr5
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movgs gr4,damlr2
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movgs gr4,iamlr2
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add gr4,gr5,gr4
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movgs gr4,damlr3
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add gr4,gr5,gr4
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movgs gr4,damlr4
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add gr4,gr5,gr4
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movgs gr4,damlr5
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add gr4,gr5,gr4
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movgs gr4,damlr6
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add gr4,gr5,gr4
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movgs gr4,damlr7
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add gr4,gr5,gr4
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movgs gr4,damlr8
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add gr4,gr5,gr4
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movgs gr4,damlr9
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add gr4,gr5,gr4
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movgs gr4,damlr10
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movgs gr0,dampr2
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movgs gr0,dampr4
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movgs gr0,dampr5
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movgs gr0,dampr6
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movgs gr0,dampr7
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movgs gr0,dampr8
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movgs gr0,dampr9
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movgs gr0,dampr10
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movgs gr0,iamlr3
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movgs gr0,iamlr4
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movgs gr0,iamlr5
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movgs gr0,iamlr6
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movgs gr0,iamlr7
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movgs gr0,iampr2
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movgs gr0,iampr3
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movgs gr0,iampr4
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movgs gr0,iampr5
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movgs gr0,iampr6
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movgs gr0,iampr7
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# start in TLB context 0 with the swapper's page tables
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movgs gr0,cxnr
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sethi.p %hi(swapper_pg_dir),gr4
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||
|
|
setlo %lo(swapper_pg_dir),gr4
|
||
|
|
sethi.p %hi(__page_offset),gr5
|
||
|
|
setlo %lo(__page_offset),gr5
|
||
|
|
sub gr4,gr5,gr4
|
||
|
|
movgs gr4,ttbr
|
||
|
|
setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr5
|
||
|
|
or gr4,gr5,gr4
|
||
|
|
movgs gr4,dampr3
|
||
|
|
|
||
|
|
# the FR451 also has an extra trap base register
|
||
|
|
movsg tbr,gr4
|
||
|
|
movgs gr4,btbr
|
||
|
|
|
||
|
|
LEDS 0x3300
|
||
|
|
jmpl @(gr27,gr0)
|
||
|
|
|
||
|
|
###############################################################################
|
||
|
|
#
|
||
|
|
# finish setting up the protection registers
|
||
|
|
#
|
||
|
|
###############################################################################
|
||
|
|
.globl __head_fr451_finalise_protection
|
||
|
|
__head_fr451_finalise_protection:
|
||
|
|
# turn on the timers as appropriate
|
||
|
|
movgs gr0,timerh
|
||
|
|
movgs gr0,timerl
|
||
|
|
movgs gr0,timerd
|
||
|
|
movsg hsr0,gr4
|
||
|
|
sethi.p %hi(HSR0_ETMI),gr5
|
||
|
|
setlo %lo(HSR0_ETMI),gr5
|
||
|
|
or gr4,gr5,gr4
|
||
|
|
movgs gr4,hsr0
|
||
|
|
|
||
|
|
# clear the TLB entry cache
|
||
|
|
movgs gr0,iamlr1
|
||
|
|
movgs gr0,iampr1
|
||
|
|
movgs gr0,damlr1
|
||
|
|
movgs gr0,dampr1
|
||
|
|
|
||
|
|
# clear the PGE cache
|
||
|
|
sethi.p %hi(__flush_tlb_all),gr4
|
||
|
|
setlo %lo(__flush_tlb_all),gr4
|
||
|
|
jmpl @(gr4,gr0)
|