2008-02-08 12:19:31 +00:00
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/* MN10300 MMU context allocation and management
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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2010-10-27 16:28:49 +00:00
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#ifdef CONFIG_MN10300_TLB_USE_PIDR
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2008-02-08 12:19:31 +00:00
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/*
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* list of the MMU contexts last allocated on each CPU
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*/
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unsigned long mmu_context_cache[NR_CPUS] = {
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2010-10-27 16:28:49 +00:00
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[0 ... NR_CPUS - 1] =
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MMU_CONTEXT_FIRST_VERSION * 2 - (1 - MMU_CONTEXT_TLBPID_LOCK_NR),
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2008-02-08 12:19:31 +00:00
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};
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2010-10-27 16:28:49 +00:00
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#endif /* CONFIG_MN10300_TLB_USE_PIDR */
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2008-02-08 12:19:31 +00:00
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/*
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* preemptively set a TLB entry
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*/
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MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies. We do this via make_coherent() by making the pages
uncacheable.
This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().
Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():
On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
to construct a pointer to the pte again. Passing a pte_t * is much
more elegant. Maybe we might even replace the pte argument with the
pte_t?
Ben Herrenschmidt would also like the pte pointer for PowerPC:
Passing the ptep in there is exactly what I want. I want that
-instead- of the PTE value, because I have issue on some ppc cases,
for I$/D$ coherency, where set_pte_at() may decide to mask out the
_PAGE_EXEC.
So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.
Includes a fix from Stephen Rothwell:
sparc: fix fallout from update_mmu_cache API change
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-18 16:40:18 +00:00
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
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2008-02-08 12:19:31 +00:00
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{
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unsigned long pteu, ptel, cnx, flags;
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MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies. We do this via make_coherent() by making the pages
uncacheable.
This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().
Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():
On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
to construct a pointer to the pte again. Passing a pte_t * is much
more elegant. Maybe we might even replace the pte argument with the
pte_t?
Ben Herrenschmidt would also like the pte pointer for PowerPC:
Passing the ptep in there is exactly what I want. I want that
-instead- of the PTE value, because I have issue on some ppc cases,
for I$/D$ coherency, where set_pte_at() may decide to mask out the
_PAGE_EXEC.
So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.
Includes a fix from Stephen Rothwell:
sparc: fix fallout from update_mmu_cache API change
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-18 16:40:18 +00:00
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pte_t pte = *ptep;
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2008-02-08 12:19:31 +00:00
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addr &= PAGE_MASK;
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ptel = pte_val(pte) & ~(xPTEL_UNUSED1 | xPTEL_UNUSED2);
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/* make sure the context doesn't migrate and defend against
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* interference from vmalloc'd regions */
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local_irq_save(flags);
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2010-10-27 16:28:49 +00:00
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cnx = ~MMU_NO_CONTEXT;
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#ifdef CONFIG_MN10300_TLB_USE_PIDR
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2008-02-08 12:19:31 +00:00
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cnx = mm_context(vma->vm_mm);
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2010-10-27 16:28:49 +00:00
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#endif
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2008-02-08 12:19:31 +00:00
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if (cnx != MMU_NO_CONTEXT) {
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2010-10-27 16:28:49 +00:00
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pteu = addr;
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#ifdef CONFIG_MN10300_TLB_USE_PIDR
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pteu |= cnx & MMU_CONTEXT_TLBPID_MASK;
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#endif
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2008-02-08 12:19:31 +00:00
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if (!(pte_val(pte) & _PAGE_NX)) {
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IPTEU = pteu;
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if (IPTEL & xPTEL_V)
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IPTEL = ptel;
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}
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DPTEU = pteu;
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if (DPTEL & xPTEL_V)
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DPTEL = ptel;
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}
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local_irq_restore(flags);
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}
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