2012-12-18 17:53:14 +00:00
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright (C) 2013 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#define pr_fmt(fmt) "psci: " fmt
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#include <linux/init.h>
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#include <linux/of.h>
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2013-10-24 19:30:14 +00:00
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#include <linux/smp.h>
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2012-12-18 17:53:14 +00:00
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#include <asm/compiler.h>
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2013-10-24 19:30:15 +00:00
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#include <asm/cpu_ops.h>
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2012-12-18 17:53:14 +00:00
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#include <asm/errno.h>
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#include <asm/psci.h>
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2013-10-24 19:30:14 +00:00
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#include <asm/smp_plat.h>
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2012-12-18 17:53:14 +00:00
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2013-10-24 19:30:14 +00:00
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#define PSCI_POWER_STATE_TYPE_STANDBY 0
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#define PSCI_POWER_STATE_TYPE_POWER_DOWN 1
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struct psci_power_state {
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u16 id;
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u8 type;
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u8 affinity_level;
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};
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struct psci_operations {
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int (*cpu_suspend)(struct psci_power_state state,
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unsigned long entry_point);
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int (*cpu_off)(struct psci_power_state state);
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int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
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int (*migrate)(unsigned long cpuid);
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};
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static struct psci_operations psci_ops;
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2012-12-18 17:53:14 +00:00
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static int (*invoke_psci_fn)(u64, u64, u64, u64);
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enum psci_function {
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PSCI_FN_CPU_SUSPEND,
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PSCI_FN_CPU_ON,
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PSCI_FN_CPU_OFF,
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PSCI_FN_MIGRATE,
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PSCI_FN_MAX,
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};
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static u32 psci_function_id[PSCI_FN_MAX];
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#define PSCI_RET_SUCCESS 0
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#define PSCI_RET_EOPNOTSUPP -1
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#define PSCI_RET_EINVAL -2
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#define PSCI_RET_EPERM -3
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static int psci_to_linux_errno(int errno)
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{
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switch (errno) {
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case PSCI_RET_SUCCESS:
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return 0;
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case PSCI_RET_EOPNOTSUPP:
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return -EOPNOTSUPP;
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case PSCI_RET_EINVAL:
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return -EINVAL;
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case PSCI_RET_EPERM:
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return -EPERM;
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};
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return -EINVAL;
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}
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#define PSCI_POWER_STATE_ID_MASK 0xffff
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#define PSCI_POWER_STATE_ID_SHIFT 0
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#define PSCI_POWER_STATE_TYPE_MASK 0x1
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#define PSCI_POWER_STATE_TYPE_SHIFT 16
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#define PSCI_POWER_STATE_AFFL_MASK 0x3
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#define PSCI_POWER_STATE_AFFL_SHIFT 24
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static u32 psci_power_state_pack(struct psci_power_state state)
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{
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return ((state.id & PSCI_POWER_STATE_ID_MASK)
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<< PSCI_POWER_STATE_ID_SHIFT) |
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((state.type & PSCI_POWER_STATE_TYPE_MASK)
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<< PSCI_POWER_STATE_TYPE_SHIFT) |
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((state.affinity_level & PSCI_POWER_STATE_AFFL_MASK)
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<< PSCI_POWER_STATE_AFFL_SHIFT);
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}
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/*
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* The following two functions are invoked via the invoke_psci_fn pointer
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* and will not be inlined, allowing us to piggyback on the AAPCS.
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*/
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static noinline int __invoke_psci_fn_hvc(u64 function_id, u64 arg0, u64 arg1,
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u64 arg2)
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{
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asm volatile(
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__asmeq("%0", "x0")
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__asmeq("%1", "x1")
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__asmeq("%2", "x2")
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__asmeq("%3", "x3")
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"hvc #0\n"
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: "+r" (function_id)
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: "r" (arg0), "r" (arg1), "r" (arg2));
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return function_id;
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}
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static noinline int __invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
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u64 arg2)
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{
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asm volatile(
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__asmeq("%0", "x0")
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__asmeq("%1", "x1")
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__asmeq("%2", "x2")
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__asmeq("%3", "x3")
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"smc #0\n"
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: "+r" (function_id)
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: "r" (arg0), "r" (arg1), "r" (arg2));
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return function_id;
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}
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static int psci_cpu_suspend(struct psci_power_state state,
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unsigned long entry_point)
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{
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int err;
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u32 fn, power_state;
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fn = psci_function_id[PSCI_FN_CPU_SUSPEND];
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power_state = psci_power_state_pack(state);
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err = invoke_psci_fn(fn, power_state, entry_point, 0);
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return psci_to_linux_errno(err);
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}
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static int psci_cpu_off(struct psci_power_state state)
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{
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int err;
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u32 fn, power_state;
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fn = psci_function_id[PSCI_FN_CPU_OFF];
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power_state = psci_power_state_pack(state);
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err = invoke_psci_fn(fn, power_state, 0, 0);
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return psci_to_linux_errno(err);
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}
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static int psci_cpu_on(unsigned long cpuid, unsigned long entry_point)
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{
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int err;
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u32 fn;
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fn = psci_function_id[PSCI_FN_CPU_ON];
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err = invoke_psci_fn(fn, cpuid, entry_point, 0);
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return psci_to_linux_errno(err);
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}
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static int psci_migrate(unsigned long cpuid)
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{
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int err;
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u32 fn;
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fn = psci_function_id[PSCI_FN_MIGRATE];
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err = invoke_psci_fn(fn, cpuid, 0, 0);
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return psci_to_linux_errno(err);
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}
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static const struct of_device_id psci_of_match[] __initconst = {
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{ .compatible = "arm,psci", },
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{},
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};
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int __init psci_init(void)
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{
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struct device_node *np;
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const char *method;
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u32 id;
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int err = 0;
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np = of_find_matching_node(NULL, psci_of_match);
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if (!np)
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return -ENODEV;
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pr_info("probing function IDs from device-tree\n");
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if (of_property_read_string(np, "method", &method)) {
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pr_warning("missing \"method\" property\n");
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err = -ENXIO;
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goto out_put_node;
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}
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if (!strcmp("hvc", method)) {
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invoke_psci_fn = __invoke_psci_fn_hvc;
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} else if (!strcmp("smc", method)) {
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invoke_psci_fn = __invoke_psci_fn_smc;
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} else {
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pr_warning("invalid \"method\" property: %s\n", method);
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err = -EINVAL;
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goto out_put_node;
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}
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if (!of_property_read_u32(np, "cpu_suspend", &id)) {
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psci_function_id[PSCI_FN_CPU_SUSPEND] = id;
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psci_ops.cpu_suspend = psci_cpu_suspend;
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}
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if (!of_property_read_u32(np, "cpu_off", &id)) {
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psci_function_id[PSCI_FN_CPU_OFF] = id;
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psci_ops.cpu_off = psci_cpu_off;
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}
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if (!of_property_read_u32(np, "cpu_on", &id)) {
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psci_function_id[PSCI_FN_CPU_ON] = id;
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psci_ops.cpu_on = psci_cpu_on;
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}
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if (!of_property_read_u32(np, "migrate", &id)) {
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psci_function_id[PSCI_FN_MIGRATE] = id;
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psci_ops.migrate = psci_migrate;
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}
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out_put_node:
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of_node_put(np);
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return err;
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}
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2013-10-24 19:30:14 +00:00
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#ifdef CONFIG_SMP
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2013-10-24 19:30:15 +00:00
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static int __init cpu_psci_cpu_init(struct device_node *dn, unsigned int cpu)
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2013-10-24 19:30:14 +00:00
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{
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return 0;
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}
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2013-10-24 19:30:15 +00:00
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static int __init cpu_psci_cpu_prepare(unsigned int cpu)
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{
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if (!psci_ops.cpu_on) {
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pr_err("no cpu_on method, not booting CPU%d\n", cpu);
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return -ENODEV;
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}
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return 0;
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}
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arm64: factor out spin-table boot method
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-24 19:30:16 +00:00
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static int cpu_psci_cpu_boot(unsigned int cpu)
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{
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int err = psci_ops.cpu_on(cpu_logical_map(cpu), __pa(secondary_entry));
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if (err)
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pr_err("psci: failed to boot CPU%d (%d)\n", cpu, err);
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return err;
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}
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2013-10-24 19:30:15 +00:00
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const struct cpu_operations cpu_psci_ops = {
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.name = "psci",
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2013-10-24 19:30:15 +00:00
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.cpu_init = cpu_psci_cpu_init,
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.cpu_prepare = cpu_psci_cpu_prepare,
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arm64: factor out spin-table boot method
The arm64 kernel has an internal holding pen, which is necessary for
some systems where we can't bring CPUs online individually and must hold
multiple CPUs in a safe area until the kernel is able to handle them.
The current SMP infrastructure for arm64 is closely coupled to this
holding pen, and alternative boot methods must launch CPUs into the pen,
where they sit before they are launched into the kernel proper.
With PSCI (and possibly other future boot methods), we can bring CPUs
online individually, and need not perform the secondary_holding_pen
dance. Instead, this patch factors the holding pen management code out
to the spin-table boot method code, as it is the only boot method
requiring the pen.
A new entry point for secondaries, secondary_entry is added for other
boot methods to use, which bypasses the holding pen and its associated
overhead when bringing CPUs online. The smp.pen.text section is also
removed, as the pen can live in head.text without problem.
The cpu_operations structure is extended with two new functions,
cpu_boot and cpu_postboot, for bringing a cpu into the kernel and
performing any post-boot cleanup required by a bootmethod (e.g.
resetting the secondary_holding_pen_release to INVALID_HWID).
Documentation is added for cpu_operations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-24 19:30:16 +00:00
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.cpu_boot = cpu_psci_cpu_boot,
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2013-10-24 19:30:14 +00:00
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};
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#endif
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