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27 lines
1.4 KiB
C
27 lines
1.4 KiB
C
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/* $Id: dcu.h,v 1.2 2001/03/01 23:23:33 davem Exp $ */
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#ifndef _SPARC64_DCU_H
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#define _SPARC64_DCU_H
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/* UltraSparc-III Data Cache Unit Control Register */
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#define DCU_CP 0x0002000000000000 /* Physical Cache Enable w/o mmu*/
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#define DCU_CV 0x0001000000000000 /* Virtual Cache Enable w/o mmu */
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#define DCU_ME 0x0000800000000000 /* NC-store Merging Enable */
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#define DCU_RE 0x0000400000000000 /* RAW bypass Enable */
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#define DCU_PE 0x0000200000000000 /* PCache Enable */
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#define DCU_HPE 0x0000100000000000 /* HW prefetch Enable */
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#define DCU_SPE 0x0000080000000000 /* SW prefetch Enable */
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#define DCU_SL 0x0000040000000000 /* Secondary load steering Enab */
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#define DCU_WE 0x0000020000000000 /* WCache enable */
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#define DCU_PM 0x000001fe00000000 /* PA Watchpoint Byte Mask */
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#define DCU_VM 0x00000001fe000000 /* VA Watchpoint Byte Mask */
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#define DCU_PR 0x0000000001000000 /* PA Watchpoint Read Enable */
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#define DCU_PW 0x0000000000800000 /* PA Watchpoint Write Enable */
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#define DCU_VR 0x0000000000400000 /* VA Watchpoint Read Enable */
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#define DCU_VW 0x0000000000200000 /* VA Watchpoint Write Enable */
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#define DCU_DM 0x0000000000000008 /* DMMU Enable */
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#define DCU_IM 0x0000000000000004 /* IMMU Enable */
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#define DCU_DC 0x0000000000000002 /* Data Cache Enable */
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#define DCU_IC 0x0000000000000001 /* Instruction Cache Enable */
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#endif /* _SPARC64_DCU_H */
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