2005-04-16 22:20:36 +00:00
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/*
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*
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* Support for the mpeg transport stream transfers
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* PCI function #2 of the cx2388x.
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*
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* (c) 2004 Jelle Foks <jelle@foks.8m.com>
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* (c) 2004 Chris Pascoe <c.pascoe@itee.uq.edu.au>
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* (c) 2004 Gerd Knorr <kraxel@bytesex.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <asm/delay.h>
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#include "cx88.h"
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/* ------------------------------------------------------------------ */
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MODULE_DESCRIPTION("mpeg driver for cx2388x based TV cards");
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MODULE_AUTHOR("Jelle Foks <jelle@foks.8m.com>");
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MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
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MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
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MODULE_LICENSE("GPL");
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static unsigned int debug = 0;
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module_param(debug,int,0644);
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MODULE_PARM_DESC(debug,"enable debug messages [mpeg]");
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#define dprintk(level,fmt, arg...) if (debug >= level) \
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printk(KERN_DEBUG "%s/2: " fmt, dev->core->name , ## arg)
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/* ------------------------------------------------------------------ */
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static int cx8802_start_dma(struct cx8802_dev *dev,
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struct cx88_dmaqueue *q,
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struct cx88_buffer *buf)
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{
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struct cx88_core *core = dev->core;
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2006-04-10 12:27:08 +00:00
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dprintk(1, "cx8802_start_dma w: %d, h: %d, f: %d\n", dev->width, dev->height, buf->vb.field);
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2005-04-16 22:20:36 +00:00
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/* setup fifo + format */
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cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
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dev->ts_packet_size, buf->risc.dma);
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/* write TS length to chip */
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cx_write(MO_TS_LNGTH, buf->vb.width);
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/* FIXME: this needs a review.
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* also: move to cx88-blackbird + cx88-dvb source files? */
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if (cx88_boards[core->board].dvb) {
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/* negedge driven & software reset */
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2005-07-08 00:58:39 +00:00
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cx_write(TS_GEN_CNTRL, 0x0040 | dev->ts_gen_cntrl);
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2005-04-16 22:20:36 +00:00
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udelay(100);
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cx_write(MO_PINMUX_IO, 0x00);
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2005-07-08 00:58:42 +00:00
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cx_write(TS_HW_SOP_CNTRL,0x47<<16|188<<4|0x01);
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2005-09-09 20:03:41 +00:00
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switch (core->board) {
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case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
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case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
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case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
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2006-04-07 05:21:31 +00:00
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case CX88_BOARD_PCHDTV_HD5500:
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2005-07-12 20:58:44 +00:00
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cx_write(TS_SOP_STAT, 1<<13);
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2005-09-09 20:03:41 +00:00
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break;
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2006-01-09 17:25:02 +00:00
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case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
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case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
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cx_write(MO_PINMUX_IO, 0x88); /* Enable MPEG parallel IO and video signal pins */
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udelay(100);
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break;
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2005-09-09 20:03:41 +00:00
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default:
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2005-07-12 20:58:44 +00:00
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cx_write(TS_SOP_STAT, 0x00);
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2005-09-09 20:03:41 +00:00
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break;
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2005-07-08 00:58:39 +00:00
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}
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2005-04-16 22:20:36 +00:00
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cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl);
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udelay(100);
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}
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if (cx88_boards[core->board].blackbird) {
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cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */
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cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */
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udelay(100);
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cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */
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cx_write(TS_VALERR_CNTRL, 0x2000);
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cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */
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udelay(100);
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}
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/* reset counter */
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cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);
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q->count = 1;
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/* enable irqs */
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2006-04-10 12:27:08 +00:00
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dprintk( 1, "setting the interrupt mask\n" );
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2005-04-16 22:20:36 +00:00
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cx_set(MO_PCI_INTMSK, core->pci_irqmask | 0x04);
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2005-06-24 05:05:03 +00:00
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cx_set(MO_TS_INTMSK, 0x1f0011);
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2005-04-16 22:20:36 +00:00
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/* start dma */
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2005-06-24 05:05:03 +00:00
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cx_set(MO_DEV_CNTRL2, (1<<5));
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cx_set(MO_TS_DMACNTRL, 0x11);
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2005-04-16 22:20:36 +00:00
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return 0;
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}
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static int cx8802_stop_dma(struct cx8802_dev *dev)
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{
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struct cx88_core *core = dev->core;
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2006-04-10 12:27:08 +00:00
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dprintk( 1, "cx8802_stop_dma\n" );
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2005-04-16 22:20:36 +00:00
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/* stop dma */
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cx_clear(MO_TS_DMACNTRL, 0x11);
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/* disable irqs */
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cx_clear(MO_PCI_INTMSK, 0x000004);
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cx_clear(MO_TS_INTMSK, 0x1f0011);
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/* Reset the controller */
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cx_write(TS_GEN_CNTRL, 0xcd);
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return 0;
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}
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static int cx8802_restart_queue(struct cx8802_dev *dev,
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struct cx88_dmaqueue *q)
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{
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struct cx88_buffer *buf;
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struct list_head *item;
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2005-06-24 05:05:03 +00:00
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dprintk( 0, "cx8802_restart_queue\n" );
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2005-04-16 22:20:36 +00:00
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if (list_empty(&q->active))
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2005-06-24 05:05:03 +00:00
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{
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dprintk( 0, "cx8802_restart_queue: queue is empty\n" );
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2005-04-16 22:20:36 +00:00
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return 0;
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2005-06-24 05:05:03 +00:00
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}
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2005-04-16 22:20:36 +00:00
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buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
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dprintk(2,"restart_queue [%p/%d]: restart dma\n",
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buf, buf->vb.i);
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cx8802_start_dma(dev, q, buf);
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list_for_each(item,&q->active) {
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buf = list_entry(item, struct cx88_buffer, vb.queue);
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buf->count = q->count++;
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}
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mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
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return 0;
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}
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/* ------------------------------------------------------------------ */
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2006-03-10 15:29:15 +00:00
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int cx8802_buf_prepare(struct videobuf_queue *q, struct cx8802_dev *dev,
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struct cx88_buffer *buf, enum v4l2_field field)
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2005-04-16 22:20:36 +00:00
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{
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int size = dev->ts_packet_size * dev->ts_packet_count;
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int rc;
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dprintk(1, "%s: %p\n", __FUNCTION__, buf);
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if (0 != buf->vb.baddr && buf->vb.bsize < size)
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return -EINVAL;
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if (STATE_NEEDS_INIT == buf->vb.state) {
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buf->vb.width = dev->ts_packet_size;
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buf->vb.height = dev->ts_packet_count;
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buf->vb.size = size;
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2005-11-09 05:36:17 +00:00
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buf->vb.field = field /*V4L2_FIELD_TOP*/;
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2005-04-16 22:20:36 +00:00
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2006-03-10 15:29:15 +00:00
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if (0 != (rc = videobuf_iolock(q,&buf->vb,NULL)))
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2005-04-16 22:20:36 +00:00
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goto fail;
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cx88_risc_databuffer(dev->pci, &buf->risc,
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buf->vb.dma.sglist,
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buf->vb.width, buf->vb.height);
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}
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buf->vb.state = STATE_PREPARED;
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return 0;
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fail:
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2006-03-10 15:29:15 +00:00
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cx88_free_buffer(q,buf);
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2005-04-16 22:20:36 +00:00
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return rc;
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}
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void cx8802_buf_queue(struct cx8802_dev *dev, struct cx88_buffer *buf)
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{
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struct cx88_buffer *prev;
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2006-03-10 15:29:15 +00:00
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struct cx88_dmaqueue *cx88q = &dev->mpegq;
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2005-04-16 22:20:36 +00:00
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2005-06-24 05:05:03 +00:00
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dprintk( 1, "cx8802_buf_queue\n" );
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2005-04-16 22:20:36 +00:00
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/* add jump to stopper */
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buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
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2006-03-10 15:29:15 +00:00
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buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
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2005-04-16 22:20:36 +00:00
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2006-03-10 15:29:15 +00:00
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if (list_empty(&cx88q->active)) {
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2006-04-10 12:27:08 +00:00
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dprintk( 1, "queue is empty - first active\n" );
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2006-03-10 15:29:15 +00:00
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list_add_tail(&buf->vb.queue,&cx88q->active);
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cx8802_start_dma(dev, cx88q, buf);
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2005-04-16 22:20:36 +00:00
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buf->vb.state = STATE_ACTIVE;
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2006-03-10 15:29:15 +00:00
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buf->count = cx88q->count++;
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mod_timer(&cx88q->timeout, jiffies+BUFFER_TIMEOUT);
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2006-04-10 12:27:08 +00:00
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dprintk(1,"[%p/%d] %s - first active\n",
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2005-04-16 22:20:36 +00:00
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buf, buf->vb.i, __FUNCTION__);
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} else {
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2005-06-24 05:05:03 +00:00
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dprintk( 1, "queue is not empty - append to active\n" );
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2006-03-10 15:29:15 +00:00
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prev = list_entry(cx88q->active.prev, struct cx88_buffer, vb.queue);
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list_add_tail(&buf->vb.queue,&cx88q->active);
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2005-04-16 22:20:36 +00:00
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buf->vb.state = STATE_ACTIVE;
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2006-03-10 15:29:15 +00:00
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buf->count = cx88q->count++;
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2005-04-16 22:20:36 +00:00
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prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
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2005-06-24 05:05:03 +00:00
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dprintk( 1, "[%p/%d] %s - append to active\n",
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2005-04-16 22:20:36 +00:00
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buf, buf->vb.i, __FUNCTION__);
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}
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}
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/* ----------------------------------------------------------- */
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static void do_cancel_buffers(struct cx8802_dev *dev, char *reason, int restart)
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{
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struct cx88_dmaqueue *q = &dev->mpegq;
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struct cx88_buffer *buf;
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unsigned long flags;
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spin_lock_irqsave(&dev->slock,flags);
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while (!list_empty(&q->active)) {
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buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
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list_del(&buf->vb.queue);
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buf->vb.state = STATE_ERROR;
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wake_up(&buf->vb.done);
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dprintk(1,"[%p/%d] %s - dma=0x%08lx\n",
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buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
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}
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if (restart)
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2005-06-24 05:05:03 +00:00
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{
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2006-04-10 12:27:08 +00:00
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dprintk(1, "restarting queue\n" );
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2005-04-16 22:20:36 +00:00
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cx8802_restart_queue(dev,q);
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2005-06-24 05:05:03 +00:00
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}
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2005-04-16 22:20:36 +00:00
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spin_unlock_irqrestore(&dev->slock,flags);
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}
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void cx8802_cancel_buffers(struct cx8802_dev *dev)
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{
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struct cx88_dmaqueue *q = &dev->mpegq;
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2005-06-24 05:05:03 +00:00
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dprintk( 1, "cx8802_cancel_buffers" );
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2005-04-16 22:20:36 +00:00
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del_timer_sync(&q->timeout);
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cx8802_stop_dma(dev);
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do_cancel_buffers(dev,"cancel",0);
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}
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static void cx8802_timeout(unsigned long data)
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{
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struct cx8802_dev *dev = (struct cx8802_dev*)data;
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2005-06-24 05:05:03 +00:00
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dprintk(0, "%s\n",__FUNCTION__);
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2005-04-16 22:20:36 +00:00
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if (debug)
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cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
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cx8802_stop_dma(dev);
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do_cancel_buffers(dev,"timeout",1);
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}
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2005-07-12 20:58:44 +00:00
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static char *cx88_mpeg_irqs[32] = {
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"ts_risci1", NULL, NULL, NULL,
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"ts_risci2", NULL, NULL, NULL,
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"ts_oflow", NULL, NULL, NULL,
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"ts_sync", NULL, NULL, NULL,
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"opc_err", "par_err", "rip_err", "pci_abort",
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"ts_err?",
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};
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2005-04-16 22:20:36 +00:00
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static void cx8802_mpeg_irq(struct cx8802_dev *dev)
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{
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struct cx88_core *core = dev->core;
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u32 status, mask, count;
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2005-06-24 05:05:03 +00:00
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dprintk( 1, "cx8802_mpeg_irq\n" );
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2005-04-16 22:20:36 +00:00
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status = cx_read(MO_TS_INTSTAT);
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mask = cx_read(MO_TS_INTMSK);
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if (0 == (status & mask))
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return;
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cx_write(MO_TS_INTSTAT, status);
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2005-07-12 20:58:44 +00:00
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|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
if (debug || (status & mask & ~0xff))
|
|
|
|
cx88_print_irqbits(core->name, "irq mpeg ",
|
|
|
|
cx88_mpeg_irqs, status, mask);
|
|
|
|
|
|
|
|
/* risc op code error */
|
|
|
|
if (status & (1 << 16)) {
|
|
|
|
printk(KERN_WARNING "%s: mpeg risc op code error\n",core->name);
|
|
|
|
cx_clear(MO_TS_DMACNTRL, 0x11);
|
|
|
|
cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* risc1 y */
|
|
|
|
if (status & 0x01) {
|
2005-06-24 05:05:03 +00:00
|
|
|
dprintk( 1, "wake up\n" );
|
2005-04-16 22:20:36 +00:00
|
|
|
spin_lock(&dev->slock);
|
|
|
|
count = cx_read(MO_TS_GPCNT);
|
|
|
|
cx88_wakeup(dev->core, &dev->mpegq, count);
|
|
|
|
spin_unlock(&dev->slock);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* risc2 y */
|
|
|
|
if (status & 0x10) {
|
|
|
|
spin_lock(&dev->slock);
|
|
|
|
cx8802_restart_queue(dev,&dev->mpegq);
|
|
|
|
spin_unlock(&dev->slock);
|
|
|
|
}
|
|
|
|
|
2005-11-09 05:37:43 +00:00
|
|
|
/* other general errors */
|
|
|
|
if (status & 0x1f0100) {
|
2005-06-24 05:05:03 +00:00
|
|
|
dprintk( 0, "general errors: 0x%08x\n", status & 0x1f0100 );
|
2005-11-09 05:37:43 +00:00
|
|
|
spin_lock(&dev->slock);
|
2005-04-16 22:20:36 +00:00
|
|
|
cx8802_stop_dma(dev);
|
2005-11-09 05:37:43 +00:00
|
|
|
cx8802_restart_queue(dev,&dev->mpegq);
|
|
|
|
spin_unlock(&dev->slock);
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2005-06-24 05:05:03 +00:00
|
|
|
#define MAX_IRQ_LOOP 10
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
static irqreturn_t cx8802_irq(int irq, void *dev_id, struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
struct cx8802_dev *dev = dev_id;
|
|
|
|
struct cx88_core *core = dev->core;
|
|
|
|
u32 status;
|
|
|
|
int loop, handled = 0;
|
|
|
|
|
2005-06-24 05:05:03 +00:00
|
|
|
for (loop = 0; loop < MAX_IRQ_LOOP; loop++) {
|
2005-04-16 22:20:36 +00:00
|
|
|
status = cx_read(MO_PCI_INTSTAT) & (core->pci_irqmask | 0x04);
|
|
|
|
if (0 == status)
|
|
|
|
goto out;
|
2005-06-24 05:05:03 +00:00
|
|
|
dprintk( 1, "cx8802_irq\n" );
|
|
|
|
dprintk( 1, " loop: %d/%d\n", loop, MAX_IRQ_LOOP );
|
|
|
|
dprintk( 1, " status: %d\n", status );
|
2005-04-16 22:20:36 +00:00
|
|
|
handled = 1;
|
|
|
|
cx_write(MO_PCI_INTSTAT, status);
|
|
|
|
|
|
|
|
if (status & core->pci_irqmask)
|
|
|
|
cx88_core_irq(core,status);
|
|
|
|
if (status & 0x04)
|
|
|
|
cx8802_mpeg_irq(dev);
|
|
|
|
};
|
2005-06-24 05:05:03 +00:00
|
|
|
if (MAX_IRQ_LOOP == loop) {
|
|
|
|
dprintk( 0, "clearing mask\n" );
|
2005-04-16 22:20:36 +00:00
|
|
|
printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
|
|
|
|
core->name);
|
|
|
|
cx_write(MO_PCI_INTMSK,0);
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
return IRQ_RETVAL(handled);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ----------------------------------------------------------- */
|
|
|
|
/* exported stuff */
|
|
|
|
|
|
|
|
int cx8802_init_common(struct cx8802_dev *dev)
|
|
|
|
{
|
|
|
|
struct cx88_core *core = dev->core;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
/* pci init */
|
|
|
|
if (pci_enable_device(dev->pci))
|
|
|
|
return -EIO;
|
|
|
|
pci_set_master(dev->pci);
|
|
|
|
if (!pci_dma_supported(dev->pci,0xffffffff)) {
|
|
|
|
printk("%s/2: Oops: no 32bit PCI DMA ???\n",dev->core->name);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev);
|
2005-11-09 05:37:43 +00:00
|
|
|
pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER, &dev->pci_lat);
|
|
|
|
printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, "
|
2005-04-16 22:20:36 +00:00
|
|
|
"latency: %d, mmio: 0x%lx\n", dev->core->name,
|
|
|
|
pci_name(dev->pci), dev->pci_rev, dev->pci->irq,
|
|
|
|
dev->pci_lat,pci_resource_start(dev->pci,0));
|
|
|
|
|
|
|
|
/* initialize driver struct */
|
|
|
|
spin_lock_init(&dev->slock);
|
|
|
|
|
|
|
|
/* init dma queue */
|
|
|
|
INIT_LIST_HEAD(&dev->mpegq.active);
|
|
|
|
INIT_LIST_HEAD(&dev->mpegq.queued);
|
|
|
|
dev->mpegq.timeout.function = cx8802_timeout;
|
|
|
|
dev->mpegq.timeout.data = (unsigned long)dev;
|
|
|
|
init_timer(&dev->mpegq.timeout);
|
|
|
|
cx88_risc_stopper(dev->pci,&dev->mpegq.stopper,
|
|
|
|
MO_TS_DMACNTRL,0x11,0x00);
|
|
|
|
|
|
|
|
/* get irq */
|
|
|
|
err = request_irq(dev->pci->irq, cx8802_irq,
|
|
|
|
SA_SHIRQ | SA_INTERRUPT, dev->core->name, dev);
|
|
|
|
if (err < 0) {
|
|
|
|
printk(KERN_ERR "%s: can't get IRQ %d\n",
|
|
|
|
dev->core->name, dev->pci->irq);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
cx_set(MO_PCI_INTMSK, core->pci_irqmask);
|
|
|
|
|
|
|
|
/* everything worked */
|
|
|
|
pci_set_drvdata(dev->pci,dev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cx8802_fini_common(struct cx8802_dev *dev)
|
|
|
|
{
|
2005-06-24 05:05:03 +00:00
|
|
|
dprintk( 2, "cx8802_fini_common\n" );
|
2005-04-16 22:20:36 +00:00
|
|
|
cx8802_stop_dma(dev);
|
|
|
|
pci_disable_device(dev->pci);
|
|
|
|
|
|
|
|
/* unregister stuff */
|
|
|
|
free_irq(dev->pci->irq, dev);
|
|
|
|
pci_set_drvdata(dev->pci, NULL);
|
|
|
|
|
|
|
|
/* free memory */
|
|
|
|
btcx_riscmem_free(dev->pci,&dev->mpegq.stopper);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ----------------------------------------------------------- */
|
|
|
|
|
|
|
|
int cx8802_suspend_common(struct pci_dev *pci_dev, pm_message_t state)
|
|
|
|
{
|
2005-11-09 05:37:43 +00:00
|
|
|
struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
|
2005-04-16 22:20:36 +00:00
|
|
|
struct cx88_core *core = dev->core;
|
|
|
|
|
|
|
|
/* stop mpeg dma */
|
|
|
|
spin_lock(&dev->slock);
|
|
|
|
if (!list_empty(&dev->mpegq.active)) {
|
2005-06-24 05:05:03 +00:00
|
|
|
dprintk( 2, "suspend\n" );
|
2005-04-16 22:20:36 +00:00
|
|
|
printk("%s: suspend mpeg\n", core->name);
|
|
|
|
cx8802_stop_dma(dev);
|
|
|
|
del_timer(&dev->mpegq.timeout);
|
|
|
|
}
|
|
|
|
spin_unlock(&dev->slock);
|
|
|
|
|
|
|
|
/* FIXME -- shutdown device */
|
|
|
|
cx88_shutdown(dev->core);
|
|
|
|
|
|
|
|
pci_save_state(pci_dev);
|
|
|
|
if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) {
|
|
|
|
pci_disable_device(pci_dev);
|
|
|
|
dev->state.disabled = 1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cx8802_resume_common(struct pci_dev *pci_dev)
|
|
|
|
{
|
2005-09-09 20:03:55 +00:00
|
|
|
struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
|
2005-04-16 22:20:36 +00:00
|
|
|
struct cx88_core *core = dev->core;
|
2005-09-09 20:03:55 +00:00
|
|
|
int err;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
if (dev->state.disabled) {
|
2005-09-09 20:03:55 +00:00
|
|
|
err=pci_enable_device(pci_dev);
|
|
|
|
if (err) {
|
|
|
|
printk(KERN_ERR "%s: can't enable device\n",
|
|
|
|
dev->core->name);
|
|
|
|
return err;
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
dev->state.disabled = 0;
|
|
|
|
}
|
2005-09-09 20:03:55 +00:00
|
|
|
err=pci_set_power_state(pci_dev, PCI_D0);
|
|
|
|
if (err) {
|
|
|
|
printk(KERN_ERR "%s: can't enable device\n",
|
|
|
|
dev->core->name);
|
|
|
|
pci_disable_device(pci_dev);
|
|
|
|
dev->state.disabled = 1;
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
pci_restore_state(pci_dev);
|
|
|
|
|
|
|
|
/* FIXME: re-initialize hardware */
|
|
|
|
cx88_reset(dev->core);
|
|
|
|
|
|
|
|
/* restart video+vbi capture */
|
|
|
|
spin_lock(&dev->slock);
|
|
|
|
if (!list_empty(&dev->mpegq.active)) {
|
|
|
|
printk("%s: resume mpeg\n", core->name);
|
|
|
|
cx8802_restart_queue(dev,&dev->mpegq);
|
|
|
|
}
|
|
|
|
spin_unlock(&dev->slock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ----------------------------------------------------------- */
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(cx8802_buf_prepare);
|
|
|
|
EXPORT_SYMBOL(cx8802_buf_queue);
|
|
|
|
EXPORT_SYMBOL(cx8802_cancel_buffers);
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(cx8802_init_common);
|
|
|
|
EXPORT_SYMBOL(cx8802_fini_common);
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(cx8802_suspend_common);
|
|
|
|
EXPORT_SYMBOL(cx8802_resume_common);
|
|
|
|
|
|
|
|
/* ----------------------------------------------------------- */
|
|
|
|
/*
|
|
|
|
* Local variables:
|
|
|
|
* c-basic-offset: 8
|
|
|
|
* End:
|
2005-06-24 05:05:03 +00:00
|
|
|
* kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|