2014-06-30 22:15:37 +00:00
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/*
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2015-12-01 16:24:06 +00:00
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* Copyright (C) 2014-2015 Broadcom Corporation
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2014-06-30 22:15:37 +00:00
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* Copyright 2014 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/sched.h>
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#include <asm/smp.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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/* Size of mapped Cortex A9 SCU address space */
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#define CORTEX_A9_SCU_SIZE 0x58
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#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */
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#define BOOT_ADDR_CPUID_MASK 0x3
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/* Name of device node property defining secondary boot register location */
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#define OF_SECONDARY_BOOT "secondary-boot-reg"
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2015-12-01 16:24:06 +00:00
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#define MPIDR_CPUID_BITMASK 0x3
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2014-06-30 22:15:37 +00:00
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/* I/O address of register used to coordinate secondary core startup */
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2015-12-01 16:24:06 +00:00
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static u32 secondary_boot_addr;
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2014-06-30 22:15:37 +00:00
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/*
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* Enable the Cortex A9 Snoop Control Unit
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*
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* By the time this is called we already know there are multiple
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* cores present. We assume we're running on a Cortex A9 processor,
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* so any trouble getting the base address register or getting the
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* SCU base is a problem.
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*
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* Return 0 if successful or an error code otherwise.
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*/
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static int __init scu_a9_enable(void)
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{
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unsigned long config_base;
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void __iomem *scu_base;
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if (!scu_a9_has_base()) {
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pr_err("no configuration base address register!\n");
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return -ENXIO;
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}
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/* Config base address register value is zero for uniprocessor */
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config_base = scu_a9_get_base();
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if (!config_base) {
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pr_err("hardware reports only one core\n");
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return -ENOENT;
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}
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scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
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if (!scu_base) {
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pr_err("failed to remap config base (%lu/%u) for SCU\n",
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config_base, CORTEX_A9_SCU_SIZE);
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return -ENOMEM;
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}
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scu_enable(scu_base);
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iounmap(scu_base); /* That's the last we'll need of this */
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return 0;
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}
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static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
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{
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static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
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2015-12-01 16:24:06 +00:00
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struct device_node *cpus_node = NULL;
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struct device_node *cpu_node = NULL;
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2014-06-30 22:15:37 +00:00
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int ret;
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/*
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* This function is only called via smp_ops->smp_prepare_cpu().
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* That only happens if a "/cpus" device tree node exists
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* and has an "enable-method" property that selects the SMP
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* operations defined herein.
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*/
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2015-12-01 16:24:06 +00:00
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cpus_node = of_find_node_by_path("/cpus");
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if (!cpus_node)
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return;
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for_each_child_of_node(cpus_node, cpu_node) {
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u32 cpuid;
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if (of_node_cmp(cpu_node->type, "cpu"))
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continue;
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if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
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pr_debug("%s: missing reg property\n",
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cpu_node->full_name);
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ret = -ENOENT;
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goto out;
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}
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/*
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* "secondary-boot-reg" property should be defined only
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* for secondary cpu
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*/
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if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
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/*
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* Our secondary enable method requires a
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* "secondary-boot-reg" property to specify a register
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* address used to request the ROM code boot a secondary
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* core. If we have any trouble getting this we fall
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* back to uniprocessor mode.
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*/
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if (of_property_read_u32(cpu_node,
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OF_SECONDARY_BOOT,
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&secondary_boot_addr)) {
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pr_warn("%s: no" OF_SECONDARY_BOOT "property\n",
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cpu_node->name);
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ret = -ENOENT;
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goto out;
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}
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}
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2014-06-30 22:15:37 +00:00
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}
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/*
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2015-12-01 16:24:06 +00:00
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* Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
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2014-06-30 22:15:37 +00:00
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* returned, the SoC reported a uniprocessor configuration.
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* We bail on any other error.
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*/
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ret = scu_a9_enable();
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out:
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2015-12-01 16:24:06 +00:00
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of_node_put(cpu_node);
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of_node_put(cpus_node);
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2014-06-30 22:15:37 +00:00
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if (ret) {
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/* Update the CPU present map to reflect uniprocessor mode */
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pr_warn("disabling SMP\n");
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init_cpu_present(&only_cpu_0);
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}
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}
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/*
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* The ROM code has the secondary cores looping, waiting for an event.
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* When an event occurs each core examines the bottom two bits of the
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* secondary boot register. When a core finds those bits contain its
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* own core id, it performs initialization, including computing its boot
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* address by clearing the boot register value's bottom two bits. The
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* core signals that it is beginning its execution by writing its boot
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* address back to the secondary boot register, and finally jumps to
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* that address.
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*
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* So to start a core executing we need to:
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* - Encode the (hardware) CPU id with the bottom bits of the secondary
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* start address.
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* - Write that value into the secondary boot register.
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* - Generate an event to wake up the secondary CPU(s).
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* - Wait for the secondary boot register to be re-written, which
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* indicates the secondary core has started.
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*/
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2015-12-01 16:24:06 +00:00
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static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
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2014-06-30 22:15:37 +00:00
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{
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void __iomem *boot_reg;
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phys_addr_t boot_func;
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u64 start_clock;
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u32 cpu_id;
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u32 boot_val;
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bool timeout = false;
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cpu_id = cpu_logical_map(cpu);
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if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
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pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
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return -EINVAL;
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}
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2015-12-01 16:24:06 +00:00
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if (!secondary_boot_addr) {
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2014-06-30 22:15:37 +00:00
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pr_err("required secondary boot register not specified\n");
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return -EINVAL;
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}
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2015-12-01 16:24:06 +00:00
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boot_reg = ioremap_nocache(
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(phys_addr_t)secondary_boot_addr, sizeof(u32));
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2014-06-30 22:15:37 +00:00
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if (!boot_reg) {
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pr_err("unable to map boot register for cpu %u\n", cpu_id);
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2015-12-01 16:24:06 +00:00
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return -ENOMEM;
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2014-06-30 22:15:37 +00:00
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}
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/*
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* Secondary cores will start in secondary_startup(),
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* defined in "arch/arm/kernel/head.S"
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*/
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boot_func = virt_to_phys(secondary_startup);
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BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
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BUG_ON(boot_func > (phys_addr_t)U32_MAX);
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/* The core to start is encoded in the low bits */
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boot_val = (u32)boot_func | cpu_id;
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writel_relaxed(boot_val, boot_reg);
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sev();
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/* The low bits will be cleared once the core has started */
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start_clock = local_clock();
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while (!timeout && readl_relaxed(boot_reg) == boot_val)
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timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
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iounmap(boot_reg);
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if (!timeout)
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return 0;
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pr_err("timeout waiting for cpu %u to start\n", cpu_id);
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2015-12-01 16:24:06 +00:00
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return -ENXIO;
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2014-06-30 22:15:37 +00:00
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}
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static struct smp_operations bcm_smp_ops __initdata = {
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.smp_prepare_cpus = bcm_smp_prepare_cpus,
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2015-12-01 16:24:06 +00:00
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.smp_boot_secondary = kona_boot_secondary,
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2014-06-30 22:15:37 +00:00
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};
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CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
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&bcm_smp_ops);
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