2017-11-06 17:11:51 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2011-11-17 15:17:04 +00:00
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/*
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* Drivers for CSR SiRFprimaII onboard UARTs.
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*/
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#include <linux/bitops.h>
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2015-04-29 06:45:09 +00:00
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#include <linux/log2.h>
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serial: sirf: use hrtimer for data rx
when the serial works as a bluetooth sink, due to audio realtime
requirement, the driver should have something similar with ALSA:
1. one big DMA buffer to easy the schedule jitter
2. split this big DMA buffer to multiple small periods, for each
period, we get a DMA interrupt, then push the data to userspace.
the small periods will easy the audio latency.
so ALSA generally uses a cyclic chained DMA.
but for sirfsoc, the dma hardware has the limitation: we have
only two loops in the cyclic mode, so we can only support two
small periods to switch. if we make the DMA buffer too big, we
get long latency, if we make the DMA buffer too little, we get
miss in scheduling for audio realtime.
so this patch moves to use a hrtimer to simulate the cyclic
DMA, then we can have a big buffer, and also have a timely
data push to users as the hrtimer can generate in small period
then actual HW interrupts.
with this patch, we also delete a lot of complex codes to handle
loop buffers, and RX timeout interrupt since the RX work can be
completely handled from hrtimer interrupt.
tests show using this way will make our bad audio streaming be-
come smooth.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-26 09:36:00 +00:00
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#include <linux/hrtimer.h>
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2013-08-12 10:15:35 +00:00
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struct sirfsoc_uart_param {
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const char *uart_name;
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const char *port_name;
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};
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struct sirfsoc_register {
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/* hardware uart specific */
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u32 sirfsoc_line_ctrl;
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u32 sirfsoc_divisor;
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/* uart - usp common */
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u32 sirfsoc_tx_rx_en;
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u32 sirfsoc_int_en_reg;
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u32 sirfsoc_int_st_reg;
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2015-05-14 06:45:21 +00:00
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u32 sirfsoc_int_en_clr_reg;
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2013-08-12 10:15:35 +00:00
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u32 sirfsoc_tx_dma_io_ctrl;
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u32 sirfsoc_tx_dma_io_len;
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u32 sirfsoc_tx_fifo_ctrl;
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u32 sirfsoc_tx_fifo_level_chk;
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u32 sirfsoc_tx_fifo_op;
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u32 sirfsoc_tx_fifo_status;
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u32 sirfsoc_tx_fifo_data;
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u32 sirfsoc_rx_dma_io_ctrl;
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u32 sirfsoc_rx_dma_io_len;
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u32 sirfsoc_rx_fifo_ctrl;
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u32 sirfsoc_rx_fifo_level_chk;
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u32 sirfsoc_rx_fifo_op;
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u32 sirfsoc_rx_fifo_status;
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u32 sirfsoc_rx_fifo_data;
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u32 sirfsoc_afc_ctrl;
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u32 sirfsoc_swh_dma_io;
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/* hardware usp specific */
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u32 sirfsoc_mode1;
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u32 sirfsoc_mode2;
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u32 sirfsoc_tx_frame_ctrl;
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u32 sirfsoc_rx_frame_ctrl;
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u32 sirfsoc_async_param_reg;
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};
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2015-04-29 06:45:09 +00:00
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typedef u32 (*fifo_full_mask)(struct uart_port *port);
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typedef u32 (*fifo_empty_mask)(struct uart_port *port);
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struct sirfsoc_fifo_status {
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fifo_full_mask ff_full;
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fifo_empty_mask ff_empty;
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};
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struct sirfsoc_int_en {
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u32 sirfsoc_rx_done_en;
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u32 sirfsoc_tx_done_en;
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u32 sirfsoc_rx_oflow_en;
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u32 sirfsoc_tx_allout_en;
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u32 sirfsoc_rx_io_dma_en;
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u32 sirfsoc_tx_io_dma_en;
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u32 sirfsoc_rxfifo_full_en;
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u32 sirfsoc_txfifo_empty_en;
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u32 sirfsoc_rxfifo_thd_en;
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u32 sirfsoc_txfifo_thd_en;
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u32 sirfsoc_frm_err_en;
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u32 sirfsoc_rxd_brk_en;
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u32 sirfsoc_rx_timeout_en;
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u32 sirfsoc_parity_err_en;
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u32 sirfsoc_cts_en;
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u32 sirfsoc_rts_en;
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};
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struct sirfsoc_int_status {
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u32 sirfsoc_rx_done;
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u32 sirfsoc_tx_done;
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u32 sirfsoc_rx_oflow;
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u32 sirfsoc_tx_allout;
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u32 sirfsoc_rx_io_dma;
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u32 sirfsoc_tx_io_dma;
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u32 sirfsoc_rxfifo_full;
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u32 sirfsoc_txfifo_empty;
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u32 sirfsoc_rxfifo_thd;
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u32 sirfsoc_txfifo_thd;
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u32 sirfsoc_frm_err;
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u32 sirfsoc_rxd_brk;
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u32 sirfsoc_rx_timeout;
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u32 sirfsoc_parity_err;
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u32 sirfsoc_cts;
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u32 sirfsoc_rts;
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};
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enum sirfsoc_uart_type {
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SIRF_REAL_UART,
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SIRF_USP_UART,
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};
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struct sirfsoc_uart_register {
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struct sirfsoc_register uart_reg;
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struct sirfsoc_int_en uart_int_en;
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struct sirfsoc_int_status uart_int_st;
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struct sirfsoc_fifo_status fifo_status;
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struct sirfsoc_uart_param uart_param;
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enum sirfsoc_uart_type uart_type;
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};
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2011-11-17 15:17:04 +00:00
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2016-06-07 18:06:11 +00:00
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static u32 uart_usp_ff_full_mask(struct uart_port *port)
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2013-08-12 10:15:35 +00:00
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{
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2015-04-29 06:45:09 +00:00
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u32 full_bit;
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full_bit = ilog2(port->fifosize);
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return (1 << full_bit);
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2013-08-12 10:15:35 +00:00
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}
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2015-04-29 06:45:09 +00:00
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2016-06-07 18:06:11 +00:00
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static u32 uart_usp_ff_empty_mask(struct uart_port *port)
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2013-08-12 10:15:35 +00:00
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{
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u32 empty_bit;
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2015-05-26 09:35:59 +00:00
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empty_bit = ilog2(port->fifosize) + 1;
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2015-04-29 06:45:09 +00:00
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return (1 << empty_bit);
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2013-08-12 10:15:35 +00:00
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}
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struct sirfsoc_uart_register sirfsoc_usp = {
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.uart_reg = {
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.sirfsoc_mode1 = 0x0000,
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.sirfsoc_mode2 = 0x0004,
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.sirfsoc_tx_frame_ctrl = 0x0008,
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.sirfsoc_rx_frame_ctrl = 0x000c,
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.sirfsoc_tx_rx_en = 0x0010,
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.sirfsoc_int_en_reg = 0x0014,
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.sirfsoc_int_st_reg = 0x0018,
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.sirfsoc_async_param_reg = 0x0024,
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.sirfsoc_tx_dma_io_ctrl = 0x0100,
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.sirfsoc_tx_dma_io_len = 0x0104,
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.sirfsoc_tx_fifo_ctrl = 0x0108,
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.sirfsoc_tx_fifo_level_chk = 0x010c,
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.sirfsoc_tx_fifo_op = 0x0110,
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.sirfsoc_tx_fifo_status = 0x0114,
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.sirfsoc_tx_fifo_data = 0x0118,
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.sirfsoc_rx_dma_io_ctrl = 0x0120,
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.sirfsoc_rx_dma_io_len = 0x0124,
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.sirfsoc_rx_fifo_ctrl = 0x0128,
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.sirfsoc_rx_fifo_level_chk = 0x012c,
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.sirfsoc_rx_fifo_op = 0x0130,
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.sirfsoc_rx_fifo_status = 0x0134,
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.sirfsoc_rx_fifo_data = 0x0138,
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2015-05-14 06:45:21 +00:00
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.sirfsoc_int_en_clr_reg = 0x140,
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2013-08-12 10:15:35 +00:00
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},
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.uart_int_en = {
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.sirfsoc_rx_done_en = BIT(0),
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.sirfsoc_tx_done_en = BIT(1),
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.sirfsoc_rx_oflow_en = BIT(2),
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.sirfsoc_tx_allout_en = BIT(3),
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.sirfsoc_rx_io_dma_en = BIT(4),
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.sirfsoc_tx_io_dma_en = BIT(5),
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.sirfsoc_rxfifo_full_en = BIT(6),
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.sirfsoc_txfifo_empty_en = BIT(7),
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.sirfsoc_rxfifo_thd_en = BIT(8),
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.sirfsoc_txfifo_thd_en = BIT(9),
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.sirfsoc_frm_err_en = BIT(10),
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.sirfsoc_rx_timeout_en = BIT(11),
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.sirfsoc_rxd_brk_en = BIT(15),
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},
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.uart_int_st = {
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.sirfsoc_rx_done = BIT(0),
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.sirfsoc_tx_done = BIT(1),
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.sirfsoc_rx_oflow = BIT(2),
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.sirfsoc_tx_allout = BIT(3),
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.sirfsoc_rx_io_dma = BIT(4),
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.sirfsoc_tx_io_dma = BIT(5),
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.sirfsoc_rxfifo_full = BIT(6),
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.sirfsoc_txfifo_empty = BIT(7),
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.sirfsoc_rxfifo_thd = BIT(8),
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.sirfsoc_txfifo_thd = BIT(9),
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.sirfsoc_frm_err = BIT(10),
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.sirfsoc_rx_timeout = BIT(11),
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.sirfsoc_rxd_brk = BIT(15),
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},
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.fifo_status = {
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2015-04-29 06:45:09 +00:00
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.ff_full = uart_usp_ff_full_mask,
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.ff_empty = uart_usp_ff_empty_mask,
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2013-08-12 10:15:35 +00:00
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},
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.uart_param = {
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.uart_name = "ttySiRF",
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.port_name = "sirfsoc-uart",
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},
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};
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struct sirfsoc_uart_register sirfsoc_uart = {
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.uart_reg = {
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.sirfsoc_line_ctrl = 0x0040,
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.sirfsoc_tx_rx_en = 0x004c,
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.sirfsoc_divisor = 0x0050,
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.sirfsoc_int_en_reg = 0x0054,
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.sirfsoc_int_st_reg = 0x0058,
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2015-05-14 06:45:21 +00:00
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.sirfsoc_int_en_clr_reg = 0x0060,
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2013-08-12 10:15:35 +00:00
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.sirfsoc_tx_dma_io_ctrl = 0x0100,
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.sirfsoc_tx_dma_io_len = 0x0104,
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.sirfsoc_tx_fifo_ctrl = 0x0108,
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.sirfsoc_tx_fifo_level_chk = 0x010c,
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.sirfsoc_tx_fifo_op = 0x0110,
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.sirfsoc_tx_fifo_status = 0x0114,
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.sirfsoc_tx_fifo_data = 0x0118,
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.sirfsoc_rx_dma_io_ctrl = 0x0120,
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.sirfsoc_rx_dma_io_len = 0x0124,
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.sirfsoc_rx_fifo_ctrl = 0x0128,
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.sirfsoc_rx_fifo_level_chk = 0x012c,
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.sirfsoc_rx_fifo_op = 0x0130,
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.sirfsoc_rx_fifo_status = 0x0134,
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.sirfsoc_rx_fifo_data = 0x0138,
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.sirfsoc_afc_ctrl = 0x0140,
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.sirfsoc_swh_dma_io = 0x0148,
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},
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.uart_int_en = {
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.sirfsoc_rx_done_en = BIT(0),
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.sirfsoc_tx_done_en = BIT(1),
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.sirfsoc_rx_oflow_en = BIT(2),
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.sirfsoc_tx_allout_en = BIT(3),
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.sirfsoc_rx_io_dma_en = BIT(4),
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.sirfsoc_tx_io_dma_en = BIT(5),
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.sirfsoc_rxfifo_full_en = BIT(6),
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.sirfsoc_txfifo_empty_en = BIT(7),
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.sirfsoc_rxfifo_thd_en = BIT(8),
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.sirfsoc_txfifo_thd_en = BIT(9),
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.sirfsoc_frm_err_en = BIT(10),
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.sirfsoc_rxd_brk_en = BIT(11),
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.sirfsoc_rx_timeout_en = BIT(12),
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.sirfsoc_parity_err_en = BIT(13),
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.sirfsoc_cts_en = BIT(14),
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.sirfsoc_rts_en = BIT(15),
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},
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.uart_int_st = {
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.sirfsoc_rx_done = BIT(0),
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.sirfsoc_tx_done = BIT(1),
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.sirfsoc_rx_oflow = BIT(2),
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.sirfsoc_tx_allout = BIT(3),
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.sirfsoc_rx_io_dma = BIT(4),
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.sirfsoc_tx_io_dma = BIT(5),
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.sirfsoc_rxfifo_full = BIT(6),
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.sirfsoc_txfifo_empty = BIT(7),
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.sirfsoc_rxfifo_thd = BIT(8),
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.sirfsoc_txfifo_thd = BIT(9),
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.sirfsoc_frm_err = BIT(10),
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.sirfsoc_rxd_brk = BIT(11),
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.sirfsoc_rx_timeout = BIT(12),
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.sirfsoc_parity_err = BIT(13),
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.sirfsoc_cts = BIT(14),
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.sirfsoc_rts = BIT(15),
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},
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.fifo_status = {
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.ff_full = uart_usp_ff_full_mask,
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.ff_empty = uart_usp_ff_empty_mask,
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2013-08-12 10:15:35 +00:00
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},
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.uart_param = {
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.uart_name = "ttySiRF",
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.port_name = "sirfsoc_uart",
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},
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};
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/* uart io ctrl */
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2011-11-17 15:17:04 +00:00
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#define SIRFUART_DATA_BIT_LEN_MASK 0x3
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#define SIRFUART_DATA_BIT_LEN_5 BIT(0)
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#define SIRFUART_DATA_BIT_LEN_6 1
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#define SIRFUART_DATA_BIT_LEN_7 2
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#define SIRFUART_DATA_BIT_LEN_8 3
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#define SIRFUART_STOP_BIT_LEN_1 0
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#define SIRFUART_STOP_BIT_LEN_2 BIT(2)
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#define SIRFUART_PARITY_EN BIT(3)
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#define SIRFUART_EVEN_BIT BIT(4)
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#define SIRFUART_STICK_BIT_MASK (7 << 3)
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#define SIRFUART_STICK_BIT_NONE (0 << 3)
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#define SIRFUART_STICK_BIT_EVEN BIT(3)
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#define SIRFUART_STICK_BIT_ODD (3 << 3)
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#define SIRFUART_STICK_BIT_MARK (5 << 3)
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#define SIRFUART_STICK_BIT_SPACE (7 << 3)
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#define SIRFUART_SET_BREAK BIT(6)
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#define SIRFUART_LOOP_BACK BIT(7)
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#define SIRFUART_PARITY_MASK (7 << 3)
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#define SIRFUART_DUMMY_READ BIT(16)
|
2013-08-12 10:15:35 +00:00
|
|
|
#define SIRFUART_AFC_CTRL_RX_THD 0x70
|
2011-11-17 15:17:04 +00:00
|
|
|
#define SIRFUART_AFC_RX_EN BIT(8)
|
|
|
|
#define SIRFUART_AFC_TX_EN BIT(9)
|
2013-08-12 10:15:35 +00:00
|
|
|
#define SIRFUART_AFC_CTS_CTRL BIT(10)
|
|
|
|
#define SIRFUART_AFC_RTS_CTRL BIT(11)
|
|
|
|
#define SIRFUART_AFC_CTS_STATUS BIT(12)
|
|
|
|
#define SIRFUART_AFC_RTS_STATUS BIT(13)
|
2011-11-17 15:17:04 +00:00
|
|
|
/* UART FIFO Register */
|
2013-08-12 10:15:35 +00:00
|
|
|
#define SIRFUART_FIFO_STOP 0x0
|
|
|
|
#define SIRFUART_FIFO_RESET BIT(0)
|
|
|
|
#define SIRFUART_FIFO_START BIT(1)
|
|
|
|
|
|
|
|
#define SIRFUART_RX_EN BIT(0)
|
|
|
|
#define SIRFUART_TX_EN BIT(1)
|
|
|
|
|
|
|
|
#define SIRFUART_IO_MODE BIT(0)
|
|
|
|
#define SIRFUART_DMA_MODE 0x0
|
serial: sirf: use hrtimer for data rx
when the serial works as a bluetooth sink, due to audio realtime
requirement, the driver should have something similar with ALSA:
1. one big DMA buffer to easy the schedule jitter
2. split this big DMA buffer to multiple small periods, for each
period, we get a DMA interrupt, then push the data to userspace.
the small periods will easy the audio latency.
so ALSA generally uses a cyclic chained DMA.
but for sirfsoc, the dma hardware has the limitation: we have
only two loops in the cyclic mode, so we can only support two
small periods to switch. if we make the DMA buffer too big, we
get long latency, if we make the DMA buffer too little, we get
miss in scheduling for audio realtime.
so this patch moves to use a hrtimer to simulate the cyclic
DMA, then we can have a big buffer, and also have a timely
data push to users as the hrtimer can generate in small period
then actual HW interrupts.
with this patch, we also delete a lot of complex codes to handle
loop buffers, and RX timeout interrupt since the RX work can be
completely handled from hrtimer interrupt.
tests show using this way will make our bad audio streaming be-
come smooth.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-26 09:36:00 +00:00
|
|
|
#define SIRFUART_RX_DMA_FLUSH 0x4
|
2013-08-12 10:15:35 +00:00
|
|
|
|
serial: sirf: workaround rx process to avoid possible data loss
when UART works in DMA mode and left bytes in rx fifo less than
a dma transfer unit, DMA engine can't transfer the bytes out
to rx DMA buffer. so it need a way to fetch them out and
flush them into tty buffer in time.
in the above case, we want UART switch from DMA mode to PIO mode and
fetch && flush bytes into tty layer buffer until rxfifo become empty,
after that done let UART switch from PIO mode back to DMA mode.
(record as method1)
method1 result in the next receive result wrong. for example in PIO part
of method1, we fetched && pushed X1...X3 bytes, when UART rxfifo newly
received Y1...Y4 bytes, UART trigger a DMA unit transfer, the DMA unit's
content is X1...X3Y1 and rxfifo fifo status is empty, so X1X2X3 pushed
twice by PIO way and DMA way also the bytes Y2Y3Y4 missed. add rxfifo
reset operation before UART switch back to DMA mode would resolve the
issue. ([method1 + do fifo reset] record as method2)
before the commit, UART driver use method2. but methd2 have a risk of
data loss, as if UART's shift register receive a complete byte and
transfer it into rxfifo before rxfifo reset operation the byte will
loss.
UART and USP have the similar bits CLEAR_RX_ADDR_EN(uart)/FRADDR_CLR_EN(usp),
When found UART controller changing I/O to DMA mode, UART controller
clears the two low bits of read point (rx_fifo_addr[1:0]).
when enable the bit + method1(record as method3), in above example
the DMA unit's content is X1...X3Y1 and there are Y2Y3Y4 in rxfifo by
experiment, we just push bytes in rx DMA buffer.
BTW, the workaround works only for UART receive DMA channel use SINGLE
DMA mode.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-14 00:52:22 +00:00
|
|
|
#define SIRFUART_CLEAR_RX_ADDR_EN 0x2
|
2013-08-12 10:15:35 +00:00
|
|
|
/* Baud Rate Calculation */
|
2015-04-29 06:45:09 +00:00
|
|
|
#define SIRF_USP_MIN_SAMPLE_DIV 0x1
|
2013-08-12 10:15:35 +00:00
|
|
|
#define SIRF_MIN_SAMPLE_DIV 0xf
|
|
|
|
#define SIRF_MAX_SAMPLE_DIV 0x3f
|
|
|
|
#define SIRF_IOCLK_DIV_MAX 0xffff
|
|
|
|
#define SIRF_SAMPLE_DIV_SHIFT 16
|
|
|
|
#define SIRF_IOCLK_DIV_MASK 0xffff
|
|
|
|
#define SIRF_SAMPLE_DIV_MASK 0x3f0000
|
|
|
|
#define SIRF_BAUD_RATE_SUPPORT_NR 18
|
|
|
|
|
|
|
|
/* USP SPEC */
|
|
|
|
#define SIRFSOC_USP_ENDIAN_CTRL_LSBF BIT(4)
|
|
|
|
#define SIRFSOC_USP_EN BIT(5)
|
2013-08-25 12:18:40 +00:00
|
|
|
#define SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET 0
|
|
|
|
#define SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET 8
|
|
|
|
#define SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK 0x3ff
|
|
|
|
#define SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET 21
|
|
|
|
#define SIRFSOC_USP_TX_DATA_LEN_OFFSET 0
|
|
|
|
#define SIRFSOC_USP_TX_SYNC_LEN_OFFSET 8
|
|
|
|
#define SIRFSOC_USP_TX_FRAME_LEN_OFFSET 16
|
|
|
|
#define SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET 24
|
|
|
|
#define SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET 30
|
|
|
|
#define SIRFSOC_USP_RX_DATA_LEN_OFFSET 0
|
|
|
|
#define SIRFSOC_USP_RX_FRAME_LEN_OFFSET 8
|
|
|
|
#define SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET 16
|
|
|
|
#define SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET 24
|
|
|
|
#define SIRFSOC_USP_ASYNC_DIV2_MASK 0x3f
|
|
|
|
#define SIRFSOC_USP_ASYNC_DIV2_OFFSET 16
|
2015-05-14 06:45:25 +00:00
|
|
|
#define SIRFSOC_USP_LOOP_BACK_CTRL BIT(2)
|
serial: sirf: workaround rx process to avoid possible data loss
when UART works in DMA mode and left bytes in rx fifo less than
a dma transfer unit, DMA engine can't transfer the bytes out
to rx DMA buffer. so it need a way to fetch them out and
flush them into tty buffer in time.
in the above case, we want UART switch from DMA mode to PIO mode and
fetch && flush bytes into tty layer buffer until rxfifo become empty,
after that done let UART switch from PIO mode back to DMA mode.
(record as method1)
method1 result in the next receive result wrong. for example in PIO part
of method1, we fetched && pushed X1...X3 bytes, when UART rxfifo newly
received Y1...Y4 bytes, UART trigger a DMA unit transfer, the DMA unit's
content is X1...X3Y1 and rxfifo fifo status is empty, so X1X2X3 pushed
twice by PIO way and DMA way also the bytes Y2Y3Y4 missed. add rxfifo
reset operation before UART switch back to DMA mode would resolve the
issue. ([method1 + do fifo reset] record as method2)
before the commit, UART driver use method2. but methd2 have a risk of
data loss, as if UART's shift register receive a complete byte and
transfer it into rxfifo before rxfifo reset operation the byte will
loss.
UART and USP have the similar bits CLEAR_RX_ADDR_EN(uart)/FRADDR_CLR_EN(usp),
When found UART controller changing I/O to DMA mode, UART controller
clears the two low bits of read point (rx_fifo_addr[1:0]).
when enable the bit + method1(record as method3), in above example
the DMA unit's content is X1...X3Y1 and there are Y2Y3Y4 in rxfifo by
experiment, we just push bytes in rx DMA buffer.
BTW, the workaround works only for UART receive DMA channel use SINGLE
DMA mode.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-14 00:52:22 +00:00
|
|
|
#define SIRFSOC_USP_FRADDR_CLR_EN BIT(1)
|
2013-08-12 10:15:35 +00:00
|
|
|
/* USP-UART Common */
|
|
|
|
#define SIRFSOC_UART_RX_TIMEOUT(br, to) (((br) * (((to) + 999) / 1000)) / 1000)
|
|
|
|
#define SIRFUART_RECV_TIMEOUT_VALUE(x) \
|
|
|
|
(((x) > 0xFFFF) ? 0xFFFF : ((x) & 0xFFFF))
|
2015-05-14 06:45:21 +00:00
|
|
|
#define SIRFUART_USP_RECV_TIMEOUT(x) (x & 0xFFFF)
|
|
|
|
#define SIRFUART_UART_RECV_TIMEOUT(x) ((x & 0xFFFF) << 16)
|
2011-11-17 15:17:04 +00:00
|
|
|
|
2015-04-29 06:45:09 +00:00
|
|
|
#define SIRFUART_FIFO_THD(port) (port->fifosize >> 1)
|
2015-05-14 06:45:21 +00:00
|
|
|
#define SIRFUART_ERR_INT_STAT(unit_st, uart_type) \
|
2013-08-12 10:15:35 +00:00
|
|
|
(uint_st->sirfsoc_rx_oflow | \
|
|
|
|
uint_st->sirfsoc_frm_err | \
|
|
|
|
uint_st->sirfsoc_rxd_brk | \
|
2015-05-14 06:45:21 +00:00
|
|
|
((uart_type != SIRF_REAL_UART) ? \
|
|
|
|
0 : uint_st->sirfsoc_parity_err))
|
|
|
|
#define SIRFUART_RX_IO_INT_EN(uint_en, uart_type) \
|
|
|
|
(uint_en->sirfsoc_rx_done_en |\
|
2013-08-12 10:15:35 +00:00
|
|
|
uint_en->sirfsoc_rxfifo_thd_en |\
|
|
|
|
uint_en->sirfsoc_rxfifo_full_en |\
|
|
|
|
uint_en->sirfsoc_frm_err_en |\
|
|
|
|
uint_en->sirfsoc_rx_oflow_en |\
|
|
|
|
uint_en->sirfsoc_rxd_brk_en |\
|
2015-05-14 06:45:21 +00:00
|
|
|
((uart_type != SIRF_REAL_UART) ? \
|
|
|
|
0 : uint_en->sirfsoc_parity_err_en))
|
2013-08-12 10:15:35 +00:00
|
|
|
#define SIRFUART_RX_IO_INT_ST(uint_st) \
|
2015-05-14 06:45:21 +00:00
|
|
|
(uint_st->sirfsoc_rxfifo_thd |\
|
|
|
|
uint_st->sirfsoc_rxfifo_full|\
|
|
|
|
uint_st->sirfsoc_rx_done |\
|
|
|
|
uint_st->sirfsoc_rx_timeout)
|
2013-08-12 10:15:35 +00:00
|
|
|
#define SIRFUART_CTS_INT_ST(uint_st) (uint_st->sirfsoc_cts)
|
2015-05-14 06:45:21 +00:00
|
|
|
#define SIRFUART_RX_DMA_INT_EN(uint_en, uart_type) \
|
serial: sirf: use hrtimer for data rx
when the serial works as a bluetooth sink, due to audio realtime
requirement, the driver should have something similar with ALSA:
1. one big DMA buffer to easy the schedule jitter
2. split this big DMA buffer to multiple small periods, for each
period, we get a DMA interrupt, then push the data to userspace.
the small periods will easy the audio latency.
so ALSA generally uses a cyclic chained DMA.
but for sirfsoc, the dma hardware has the limitation: we have
only two loops in the cyclic mode, so we can only support two
small periods to switch. if we make the DMA buffer too big, we
get long latency, if we make the DMA buffer too little, we get
miss in scheduling for audio realtime.
so this patch moves to use a hrtimer to simulate the cyclic
DMA, then we can have a big buffer, and also have a timely
data push to users as the hrtimer can generate in small period
then actual HW interrupts.
with this patch, we also delete a lot of complex codes to handle
loop buffers, and RX timeout interrupt since the RX work can be
completely handled from hrtimer interrupt.
tests show using this way will make our bad audio streaming be-
come smooth.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-26 09:36:00 +00:00
|
|
|
(uint_en->sirfsoc_frm_err_en |\
|
serial: sirf: add DMA support using dmaengine APIs
if we get the valid dma channels from dts, move to use dmaengine to do
rx/tx. because the dma hardware requires dma address and length to be
4bytes aligned, in this driver, we will still use PIO for non-aligned
bytes, and use dma for aligned bytes.
for rx, to keep the dmaengine always active, we use double-buffer, so
we issue two dma_desc at first, and maintain the status of both
1. dma transfer done: update in rx dma finish callback
2. dma buffer is inserted into tty: update in rx dma finish tasklet and
rx timeout tasklet
so we re-issue the dma_desc only if both 1&2 are finished.
for tx, as we know the actual length for every transfer, we don't need
the above double buffering.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-19 03:47:53 +00:00
|
|
|
uint_en->sirfsoc_rx_oflow_en |\
|
|
|
|
uint_en->sirfsoc_rxd_brk_en |\
|
2015-05-14 06:45:21 +00:00
|
|
|
((uart_type != SIRF_REAL_UART) ? \
|
|
|
|
0 : uint_en->sirfsoc_parity_err_en))
|
2011-11-17 15:17:04 +00:00
|
|
|
/* Generic Definitions */
|
|
|
|
#define SIRFSOC_UART_NAME "ttySiRF"
|
|
|
|
#define SIRFSOC_UART_MAJOR 0
|
|
|
|
#define SIRFSOC_UART_MINOR 0
|
|
|
|
#define SIRFUART_PORT_NAME "sirfsoc-uart"
|
|
|
|
#define SIRFUART_MAP_SIZE 0x200
|
2015-04-29 06:45:08 +00:00
|
|
|
#define SIRFSOC_UART_NR 11
|
2011-11-17 15:17:04 +00:00
|
|
|
#define SIRFSOC_PORT_TYPE 0xa5
|
|
|
|
|
serial: sirf: add DMA support using dmaengine APIs
if we get the valid dma channels from dts, move to use dmaengine to do
rx/tx. because the dma hardware requires dma address and length to be
4bytes aligned, in this driver, we will still use PIO for non-aligned
bytes, and use dma for aligned bytes.
for rx, to keep the dmaengine always active, we use double-buffer, so
we issue two dma_desc at first, and maintain the status of both
1. dma transfer done: update in rx dma finish callback
2. dma buffer is inserted into tty: update in rx dma finish tasklet and
rx timeout tasklet
so we re-issue the dma_desc only if both 1&2 are finished.
for tx, as we know the actual length for every transfer, we don't need
the above double buffering.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-19 03:47:53 +00:00
|
|
|
/* Uart Common Use Macro*/
|
serial: sirf: use hrtimer for data rx
when the serial works as a bluetooth sink, due to audio realtime
requirement, the driver should have something similar with ALSA:
1. one big DMA buffer to easy the schedule jitter
2. split this big DMA buffer to multiple small periods, for each
period, we get a DMA interrupt, then push the data to userspace.
the small periods will easy the audio latency.
so ALSA generally uses a cyclic chained DMA.
but for sirfsoc, the dma hardware has the limitation: we have
only two loops in the cyclic mode, so we can only support two
small periods to switch. if we make the DMA buffer too big, we
get long latency, if we make the DMA buffer too little, we get
miss in scheduling for audio realtime.
so this patch moves to use a hrtimer to simulate the cyclic
DMA, then we can have a big buffer, and also have a timely
data push to users as the hrtimer can generate in small period
then actual HW interrupts.
with this patch, we also delete a lot of complex codes to handle
loop buffers, and RX timeout interrupt since the RX work can be
completely handled from hrtimer interrupt.
tests show using this way will make our bad audio streaming be-
come smooth.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-26 09:36:00 +00:00
|
|
|
#define SIRFSOC_RX_DMA_BUF_SIZE (1024 * 32)
|
serial: sirf: add DMA support using dmaengine APIs
if we get the valid dma channels from dts, move to use dmaengine to do
rx/tx. because the dma hardware requires dma address and length to be
4bytes aligned, in this driver, we will still use PIO for non-aligned
bytes, and use dma for aligned bytes.
for rx, to keep the dmaengine always active, we use double-buffer, so
we issue two dma_desc at first, and maintain the status of both
1. dma transfer done: update in rx dma finish callback
2. dma buffer is inserted into tty: update in rx dma finish tasklet and
rx timeout tasklet
so we re-issue the dma_desc only if both 1&2 are finished.
for tx, as we know the actual length for every transfer, we don't need
the above double buffering.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-19 03:47:53 +00:00
|
|
|
#define BYTES_TO_ALIGN(dma_addr) ((unsigned long)(dma_addr) & 0x3)
|
|
|
|
/* Uart Fifo Level Chk */
|
|
|
|
#define SIRFUART_TX_FIFO_SC_OFFSET 0
|
|
|
|
#define SIRFUART_TX_FIFO_LC_OFFSET 10
|
|
|
|
#define SIRFUART_TX_FIFO_HC_OFFSET 20
|
|
|
|
#define SIRFUART_TX_FIFO_CHK_SC(line, value) ((((line) == 1) ? (value & 0x3) :\
|
|
|
|
(value & 0x1f)) << SIRFUART_TX_FIFO_SC_OFFSET)
|
|
|
|
#define SIRFUART_TX_FIFO_CHK_LC(line, value) ((((line) == 1) ? (value & 0x3) :\
|
|
|
|
(value & 0x1f)) << SIRFUART_TX_FIFO_LC_OFFSET)
|
|
|
|
#define SIRFUART_TX_FIFO_CHK_HC(line, value) ((((line) == 1) ? (value & 0x3) :\
|
|
|
|
(value & 0x1f)) << SIRFUART_TX_FIFO_HC_OFFSET)
|
|
|
|
|
|
|
|
#define SIRFUART_RX_FIFO_CHK_SC SIRFUART_TX_FIFO_CHK_SC
|
|
|
|
#define SIRFUART_RX_FIFO_CHK_LC SIRFUART_TX_FIFO_CHK_LC
|
|
|
|
#define SIRFUART_RX_FIFO_CHK_HC SIRFUART_TX_FIFO_CHK_HC
|
serial: sirf: use hrtimer for data rx
when the serial works as a bluetooth sink, due to audio realtime
requirement, the driver should have something similar with ALSA:
1. one big DMA buffer to easy the schedule jitter
2. split this big DMA buffer to multiple small periods, for each
period, we get a DMA interrupt, then push the data to userspace.
the small periods will easy the audio latency.
so ALSA generally uses a cyclic chained DMA.
but for sirfsoc, the dma hardware has the limitation: we have
only two loops in the cyclic mode, so we can only support two
small periods to switch. if we make the DMA buffer too big, we
get long latency, if we make the DMA buffer too little, we get
miss in scheduling for audio realtime.
so this patch moves to use a hrtimer to simulate the cyclic
DMA, then we can have a big buffer, and also have a timely
data push to users as the hrtimer can generate in small period
then actual HW interrupts.
with this patch, we also delete a lot of complex codes to handle
loop buffers, and RX timeout interrupt since the RX work can be
completely handled from hrtimer interrupt.
tests show using this way will make our bad audio streaming be-
come smooth.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-26 09:36:00 +00:00
|
|
|
#define SIRFUART_RX_FIFO_MASK 0x7f
|
serial: sirf: add DMA support using dmaengine APIs
if we get the valid dma channels from dts, move to use dmaengine to do
rx/tx. because the dma hardware requires dma address and length to be
4bytes aligned, in this driver, we will still use PIO for non-aligned
bytes, and use dma for aligned bytes.
for rx, to keep the dmaengine always active, we use double-buffer, so
we issue two dma_desc at first, and maintain the status of both
1. dma transfer done: update in rx dma finish callback
2. dma buffer is inserted into tty: update in rx dma finish tasklet and
rx timeout tasklet
so we re-issue the dma_desc only if both 1&2 are finished.
for tx, as we know the actual length for every transfer, we don't need
the above double buffering.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-19 03:47:53 +00:00
|
|
|
/* Indicate how many buffers used */
|
|
|
|
|
2011-11-17 15:17:04 +00:00
|
|
|
/* For Fast Baud Rate Calculation */
|
|
|
|
struct sirfsoc_baudrate_to_regv {
|
|
|
|
unsigned int baud_rate;
|
|
|
|
unsigned int reg_val;
|
|
|
|
};
|
|
|
|
|
serial: sirf: add DMA support using dmaengine APIs
if we get the valid dma channels from dts, move to use dmaengine to do
rx/tx. because the dma hardware requires dma address and length to be
4bytes aligned, in this driver, we will still use PIO for non-aligned
bytes, and use dma for aligned bytes.
for rx, to keep the dmaengine always active, we use double-buffer, so
we issue two dma_desc at first, and maintain the status of both
1. dma transfer done: update in rx dma finish callback
2. dma buffer is inserted into tty: update in rx dma finish tasklet and
rx timeout tasklet
so we re-issue the dma_desc only if both 1&2 are finished.
for tx, as we know the actual length for every transfer, we don't need
the above double buffering.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-19 03:47:53 +00:00
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enum sirfsoc_tx_state {
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TX_DMA_IDLE,
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TX_DMA_RUNNING,
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TX_DMA_PAUSE,
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};
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serial: sirf: use hrtimer for data rx
when the serial works as a bluetooth sink, due to audio realtime
requirement, the driver should have something similar with ALSA:
1. one big DMA buffer to easy the schedule jitter
2. split this big DMA buffer to multiple small periods, for each
period, we get a DMA interrupt, then push the data to userspace.
the small periods will easy the audio latency.
so ALSA generally uses a cyclic chained DMA.
but for sirfsoc, the dma hardware has the limitation: we have
only two loops in the cyclic mode, so we can only support two
small periods to switch. if we make the DMA buffer too big, we
get long latency, if we make the DMA buffer too little, we get
miss in scheduling for audio realtime.
so this patch moves to use a hrtimer to simulate the cyclic
DMA, then we can have a big buffer, and also have a timely
data push to users as the hrtimer can generate in small period
then actual HW interrupts.
with this patch, we also delete a lot of complex codes to handle
loop buffers, and RX timeout interrupt since the RX work can be
completely handled from hrtimer interrupt.
tests show using this way will make our bad audio streaming be-
come smooth.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-26 09:36:00 +00:00
|
|
|
struct sirfsoc_rx_buffer {
|
serial: sirf: add DMA support using dmaengine APIs
if we get the valid dma channels from dts, move to use dmaengine to do
rx/tx. because the dma hardware requires dma address and length to be
4bytes aligned, in this driver, we will still use PIO for non-aligned
bytes, and use dma for aligned bytes.
for rx, to keep the dmaengine always active, we use double-buffer, so
we issue two dma_desc at first, and maintain the status of both
1. dma transfer done: update in rx dma finish callback
2. dma buffer is inserted into tty: update in rx dma finish tasklet and
rx timeout tasklet
so we re-issue the dma_desc only if both 1&2 are finished.
for tx, as we know the actual length for every transfer, we don't need
the above double buffering.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-19 03:47:53 +00:00
|
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|
struct circ_buf xmit;
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dma_cookie_t cookie;
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struct dma_async_tx_descriptor *desc;
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dma_addr_t dma_addr;
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};
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2011-11-17 15:17:04 +00:00
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struct sirfsoc_uart_port {
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2013-08-14 22:52:15 +00:00
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bool hw_flow_ctrl;
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bool ms_enabled;
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2011-11-17 15:17:04 +00:00
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struct uart_port port;
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2013-01-16 06:49:27 +00:00
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struct clk *clk;
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2015-01-03 09:02:57 +00:00
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/* for SiRFatlas7, there are SET/CLR for UART_INT_EN */
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bool is_atlas7;
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2013-08-12 10:15:35 +00:00
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struct sirfsoc_uart_register *uart_reg;
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serial: sirf: add DMA support using dmaengine APIs
if we get the valid dma channels from dts, move to use dmaengine to do
rx/tx. because the dma hardware requires dma address and length to be
4bytes aligned, in this driver, we will still use PIO for non-aligned
bytes, and use dma for aligned bytes.
for rx, to keep the dmaengine always active, we use double-buffer, so
we issue two dma_desc at first, and maintain the status of both
1. dma transfer done: update in rx dma finish callback
2. dma buffer is inserted into tty: update in rx dma finish tasklet and
rx timeout tasklet
so we re-issue the dma_desc only if both 1&2 are finished.
for tx, as we know the actual length for every transfer, we don't need
the above double buffering.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-19 03:47:53 +00:00
|
|
|
struct dma_chan *rx_dma_chan;
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struct dma_chan *tx_dma_chan;
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dma_addr_t tx_dma_addr;
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struct dma_async_tx_descriptor *tx_dma_desc;
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unsigned long transfer_size;
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enum sirfsoc_tx_state tx_dma_state;
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2013-08-14 22:52:15 +00:00
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unsigned int cts_gpio;
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unsigned int rts_gpio;
|
serial: sirf: add DMA support using dmaengine APIs
if we get the valid dma channels from dts, move to use dmaengine to do
rx/tx. because the dma hardware requires dma address and length to be
4bytes aligned, in this driver, we will still use PIO for non-aligned
bytes, and use dma for aligned bytes.
for rx, to keep the dmaengine always active, we use double-buffer, so
we issue two dma_desc at first, and maintain the status of both
1. dma transfer done: update in rx dma finish callback
2. dma buffer is inserted into tty: update in rx dma finish tasklet and
rx timeout tasklet
so we re-issue the dma_desc only if both 1&2 are finished.
for tx, as we know the actual length for every transfer, we don't need
the above double buffering.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-08-19 03:47:53 +00:00
|
|
|
|
serial: sirf: use hrtimer for data rx
when the serial works as a bluetooth sink, due to audio realtime
requirement, the driver should have something similar with ALSA:
1. one big DMA buffer to easy the schedule jitter
2. split this big DMA buffer to multiple small periods, for each
period, we get a DMA interrupt, then push the data to userspace.
the small periods will easy the audio latency.
so ALSA generally uses a cyclic chained DMA.
but for sirfsoc, the dma hardware has the limitation: we have
only two loops in the cyclic mode, so we can only support two
small periods to switch. if we make the DMA buffer too big, we
get long latency, if we make the DMA buffer too little, we get
miss in scheduling for audio realtime.
so this patch moves to use a hrtimer to simulate the cyclic
DMA, then we can have a big buffer, and also have a timely
data push to users as the hrtimer can generate in small period
then actual HW interrupts.
with this patch, we also delete a lot of complex codes to handle
loop buffers, and RX timeout interrupt since the RX work can be
completely handled from hrtimer interrupt.
tests show using this way will make our bad audio streaming be-
come smooth.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-05-26 09:36:00 +00:00
|
|
|
struct sirfsoc_rx_buffer rx_dma_items;
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struct hrtimer hrt;
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bool is_hrt_enabled;
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unsigned long rx_period_time;
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serial: sirf: workaround rx process to avoid possible data loss
when UART works in DMA mode and left bytes in rx fifo less than
a dma transfer unit, DMA engine can't transfer the bytes out
to rx DMA buffer. so it need a way to fetch them out and
flush them into tty buffer in time.
in the above case, we want UART switch from DMA mode to PIO mode and
fetch && flush bytes into tty layer buffer until rxfifo become empty,
after that done let UART switch from PIO mode back to DMA mode.
(record as method1)
method1 result in the next receive result wrong. for example in PIO part
of method1, we fetched && pushed X1...X3 bytes, when UART rxfifo newly
received Y1...Y4 bytes, UART trigger a DMA unit transfer, the DMA unit's
content is X1...X3Y1 and rxfifo fifo status is empty, so X1X2X3 pushed
twice by PIO way and DMA way also the bytes Y2Y3Y4 missed. add rxfifo
reset operation before UART switch back to DMA mode would resolve the
issue. ([method1 + do fifo reset] record as method2)
before the commit, UART driver use method2. but methd2 have a risk of
data loss, as if UART's shift register receive a complete byte and
transfer it into rxfifo before rxfifo reset operation the byte will
loss.
UART and USP have the similar bits CLEAR_RX_ADDR_EN(uart)/FRADDR_CLR_EN(usp),
When found UART controller changing I/O to DMA mode, UART controller
clears the two low bits of read point (rx_fifo_addr[1:0]).
when enable the bit + method1(record as method3), in above example
the DMA unit's content is X1...X3Y1 and there are Y2Y3Y4 in rxfifo by
experiment, we just push bytes in rx DMA buffer.
BTW, the workaround works only for UART receive DMA channel use SINGLE
DMA mode.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-14 00:52:22 +00:00
|
|
|
unsigned long rx_last_pos;
|
|
|
|
unsigned long pio_fetch_cnt;
|
2011-11-17 15:17:04 +00:00
|
|
|
};
|
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|
/* Register Access Control */
|
|
|
|
#define portaddr(port, reg) ((port)->membase + (reg))
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#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
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#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
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/* UART Port Mask */
|
2015-04-29 06:45:09 +00:00
|
|
|
#define SIRFUART_FIFOLEVEL_MASK(port) ((port->fifosize - 1) & 0xFFF)
|
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#define SIRFUART_FIFOFULL_MASK(port) (port->fifosize & 0xFFF)
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#define SIRFUART_FIFOEMPTY_MASK(port) ((port->fifosize & 0xFFF) << 1)
|