2005-10-10 12:36:14 +00:00
|
|
|
/*
|
|
|
|
|
* PowerPC version
|
|
|
|
|
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
|
|
|
|
|
* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
|
|
|
|
|
* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
|
|
|
|
|
* Adapted for Power Macintosh by Paul Mackerras.
|
|
|
|
|
* Low-level exception handlers and MMU support
|
|
|
|
|
* rewritten by Paul Mackerras.
|
|
|
|
|
* Copyright (C) 1996 Paul Mackerras.
|
|
|
|
|
* MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
|
|
|
|
|
*
|
|
|
|
|
* This file contains the system call entry code, context switch
|
|
|
|
|
* code, and exception/interrupt return code for PowerPC.
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
|
* modify it under the terms of the GNU General Public License
|
|
|
|
|
* as published by the Free Software Foundation; either version
|
|
|
|
|
* 2 of the License, or (at your option) any later version.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include <linux/errno.h>
|
|
|
|
|
#include <asm/unistd.h>
|
|
|
|
|
#include <asm/processor.h>
|
|
|
|
|
#include <asm/page.h>
|
|
|
|
|
#include <asm/mmu.h>
|
|
|
|
|
#include <asm/thread_info.h>
|
|
|
|
|
#include <asm/ppc_asm.h>
|
|
|
|
|
#include <asm/asm-offsets.h>
|
|
|
|
|
#include <asm/cputable.h>
|
2006-09-25 08:19:00 +00:00
|
|
|
#include <asm/firmware.h>
|
2007-01-01 18:45:34 +00:00
|
|
|
#include <asm/bug.h>
|
2008-04-17 04:34:59 +00:00
|
|
|
#include <asm/ptrace.h>
|
2008-04-17 04:35:01 +00:00
|
|
|
#include <asm/irqflags.h>
|
2008-06-21 18:17:27 +00:00
|
|
|
#include <asm/ftrace.h>
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
#include <asm/hw_irq.h>
|
2013-05-13 16:16:43 +00:00
|
|
|
#include <asm/context_tracking.h>
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* System calls.
|
|
|
|
|
*/
|
|
|
|
|
.section ".toc","aw"
|
2014-02-04 05:05:53 +00:00
|
|
|
SYS_CALL_TABLE:
|
|
|
|
|
.tc sys_call_table[TC],sys_call_table
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
/* This value is used to mark exception frames on the stack. */
|
|
|
|
|
exception_marker:
|
2008-04-17 04:34:59 +00:00
|
|
|
.tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
.section ".text"
|
|
|
|
|
.align 7
|
|
|
|
|
|
|
|
|
|
.globl system_call_common
|
|
|
|
|
system_call_common:
|
|
|
|
|
andi. r10,r12,MSR_PR
|
|
|
|
|
mr r10,r1
|
|
|
|
|
addi r1,r1,-INT_FRAME_SIZE
|
|
|
|
|
beq- 1f
|
|
|
|
|
ld r1,PACAKSAVE(r13)
|
|
|
|
|
1: std r10,0(r1)
|
|
|
|
|
std r11,_NIP(r1)
|
|
|
|
|
std r12,_MSR(r1)
|
|
|
|
|
std r0,GPR0(r1)
|
|
|
|
|
std r10,GPR1(r1)
|
2012-12-06 21:46:37 +00:00
|
|
|
beq 2f /* if from kernel mode */
|
powerpc: Implement accurate task and CPU time accounting
This implements accurate task and cpu time accounting for 64-bit
powerpc kernels. Instead of accounting a whole jiffy of time to a
task on a timer interrupt because that task happened to be running at
the time, we now account time in units of timebase ticks according to
the actual time spent by the task in user mode and kernel mode. We
also count the time spent processing hardware and software interrupts
accurately. This is conditional on CONFIG_VIRT_CPU_ACCOUNTING. If
that is not set, we do tick-based approximate accounting as before.
To get this accurate information, we read either the PURR (processor
utilization of resources register) on POWER5 machines, or the timebase
on other machines on
* each entry to the kernel from usermode
* each exit to usermode
* transitions between process context, hard irq context and soft irq
context in kernel mode
* context switches.
On POWER5 systems with shared-processor logical partitioning we also
read both the PURR and the timebase at each timer interrupt and
context switch in order to determine how much time has been taken by
the hypervisor to run other partitions ("steal" time). Unfortunately,
since we need values of the PURR on both threads at the same time to
accurately calculate the steal time, and since we can only calculate
steal time on a per-core basis, the apportioning of the steal time
between idle time (time which we ceded to the hypervisor in the idle
loop) and actual stolen time is somewhat approximate at the moment.
This is all based quite heavily on what s390 does, and it uses the
generic interfaces that were added by the s390 developers,
i.e. account_system_time(), account_user_time(), etc.
This patch doesn't add any new interfaces between the kernel and
userspace, and doesn't change the units in which time is reported to
userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
times(), etc. Internally the various task and cpu times are stored in
timebase units, but they are converted to USER_HZ units (1/100th of a
second) when reported to userspace. Some precision is therefore lost
but there should not be any accumulating error, since the internal
accumulation is at full precision.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-23 23:06:59 +00:00
|
|
|
ACCOUNT_CPU_USER_ENTRY(r10, r11)
|
2012-12-06 21:46:37 +00:00
|
|
|
2: std r2,GPR2(r1)
|
2005-10-10 12:36:14 +00:00
|
|
|
std r3,GPR3(r1)
|
2012-04-05 03:44:48 +00:00
|
|
|
mfcr r2
|
2005-10-10 12:36:14 +00:00
|
|
|
std r4,GPR4(r1)
|
|
|
|
|
std r5,GPR5(r1)
|
|
|
|
|
std r6,GPR6(r1)
|
|
|
|
|
std r7,GPR7(r1)
|
|
|
|
|
std r8,GPR8(r1)
|
|
|
|
|
li r11,0
|
|
|
|
|
std r11,GPR9(r1)
|
|
|
|
|
std r11,GPR10(r1)
|
|
|
|
|
std r11,GPR11(r1)
|
|
|
|
|
std r11,GPR12(r1)
|
2012-04-04 18:24:29 +00:00
|
|
|
std r11,_XER(r1)
|
2012-04-04 18:26:39 +00:00
|
|
|
std r11,_CTR(r1)
|
2005-10-10 12:36:14 +00:00
|
|
|
std r9,GPR13(r1)
|
|
|
|
|
mflr r10
|
2012-04-05 03:44:48 +00:00
|
|
|
/*
|
|
|
|
|
* This clears CR0.SO (bit 28), which is the error indication on
|
|
|
|
|
* return from this system call.
|
|
|
|
|
*/
|
|
|
|
|
rldimi r2,r11,28,(63-28)
|
2005-10-10 12:36:14 +00:00
|
|
|
li r11,0xc01
|
|
|
|
|
std r10,_LINK(r1)
|
|
|
|
|
std r11,_TRAP(r1)
|
|
|
|
|
std r3,ORIG_GPR3(r1)
|
2012-04-05 03:44:48 +00:00
|
|
|
std r2,_CCR(r1)
|
2005-10-10 12:36:14 +00:00
|
|
|
ld r2,PACATOC(r13)
|
|
|
|
|
addi r9,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
ld r11,exception_marker@toc(r2)
|
|
|
|
|
std r11,-16(r9) /* "regshere" marker */
|
2012-07-25 05:56:04 +00:00
|
|
|
#if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
|
powerpc: Account time using timebase rather than PURR
Currently, when CONFIG_VIRT_CPU_ACCOUNTING is enabled, we use the
PURR register for measuring the user and system time used by
processes, as well as other related times such as hardirq and
softirq times. This turns out to be quite confusing for users
because it means that a program will often be measured as taking
less time when run on a multi-threaded processor (SMT2 or SMT4 mode)
than it does when run on a single-threaded processor (ST mode), even
though the program takes longer to finish. The discrepancy is
accounted for as stolen time, which is also confusing, particularly
when there are no other partitions running.
This changes the accounting to use the timebase instead, meaning that
the reported user and system times are the actual number of real-time
seconds that the program was executing on the processor thread,
regardless of which SMT mode the processor is in. Thus a program will
generally show greater user and system times when run on a
multi-threaded processor than on a single-threaded processor.
On pSeries systems on POWER5 or later processors, we measure the
stolen time (time when this partition wasn't running) using the
hypervisor dispatch trace log. We check for new entries in the
log on every entry from user mode and on every transition from
kernel process context to soft or hard IRQ context (i.e. when
account_system_vtime() gets called). So that we can correctly
distinguish time stolen from user time and time stolen from system
time, without having to check the log on every exit to user mode,
we store separate timestamps for exit to user mode and entry from
user mode.
On systems that have a SPURR (POWER6 and POWER7), we read the SPURR
in account_system_vtime() (as before), and then apportion the SPURR
ticks since the last time we read it between scaled user time and
scaled system time according to the relative proportions of user
time and system time over the same interval. This avoids having to
read the SPURR on every kernel entry and exit. On systems that have
PURR but not SPURR (i.e., POWER5), we do the same using the PURR
rather than the SPURR.
This disables the DTL user interface in /sys/debug/kernel/powerpc/dtl
for now since it conflicts with the use of the dispatch trace log
by the time accounting code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-26 19:56:43 +00:00
|
|
|
BEGIN_FW_FTR_SECTION
|
|
|
|
|
beq 33f
|
|
|
|
|
/* if from user, see if there are any DTL entries to process */
|
|
|
|
|
ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
|
|
|
|
|
ld r11,PACA_DTL_RIDX(r13) /* get log read index */
|
2013-08-06 16:01:46 +00:00
|
|
|
addi r10,r10,LPPACA_DTLIDX
|
|
|
|
|
LDX_BE r10,0,r10 /* get log write index */
|
powerpc: Account time using timebase rather than PURR
Currently, when CONFIG_VIRT_CPU_ACCOUNTING is enabled, we use the
PURR register for measuring the user and system time used by
processes, as well as other related times such as hardirq and
softirq times. This turns out to be quite confusing for users
because it means that a program will often be measured as taking
less time when run on a multi-threaded processor (SMT2 or SMT4 mode)
than it does when run on a single-threaded processor (ST mode), even
though the program takes longer to finish. The discrepancy is
accounted for as stolen time, which is also confusing, particularly
when there are no other partitions running.
This changes the accounting to use the timebase instead, meaning that
the reported user and system times are the actual number of real-time
seconds that the program was executing on the processor thread,
regardless of which SMT mode the processor is in. Thus a program will
generally show greater user and system times when run on a
multi-threaded processor than on a single-threaded processor.
On pSeries systems on POWER5 or later processors, we measure the
stolen time (time when this partition wasn't running) using the
hypervisor dispatch trace log. We check for new entries in the
log on every entry from user mode and on every transition from
kernel process context to soft or hard IRQ context (i.e. when
account_system_vtime() gets called). So that we can correctly
distinguish time stolen from user time and time stolen from system
time, without having to check the log on every exit to user mode,
we store separate timestamps for exit to user mode and entry from
user mode.
On systems that have a SPURR (POWER6 and POWER7), we read the SPURR
in account_system_vtime() (as before), and then apportion the SPURR
ticks since the last time we read it between scaled user time and
scaled system time according to the relative proportions of user
time and system time over the same interval. This avoids having to
read the SPURR on every kernel entry and exit. On systems that have
PURR but not SPURR (i.e., POWER5), we do the same using the PURR
rather than the SPURR.
This disables the DTL user interface in /sys/debug/kernel/powerpc/dtl
for now since it conflicts with the use of the dispatch trace log
by the time accounting code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-26 19:56:43 +00:00
|
|
|
cmpd cr1,r11,r10
|
|
|
|
|
beq+ cr1,33f
|
2014-02-04 05:04:35 +00:00
|
|
|
bl accumulate_stolen_time
|
powerpc: Account time using timebase rather than PURR
Currently, when CONFIG_VIRT_CPU_ACCOUNTING is enabled, we use the
PURR register for measuring the user and system time used by
processes, as well as other related times such as hardirq and
softirq times. This turns out to be quite confusing for users
because it means that a program will often be measured as taking
less time when run on a multi-threaded processor (SMT2 or SMT4 mode)
than it does when run on a single-threaded processor (ST mode), even
though the program takes longer to finish. The discrepancy is
accounted for as stolen time, which is also confusing, particularly
when there are no other partitions running.
This changes the accounting to use the timebase instead, meaning that
the reported user and system times are the actual number of real-time
seconds that the program was executing on the processor thread,
regardless of which SMT mode the processor is in. Thus a program will
generally show greater user and system times when run on a
multi-threaded processor than on a single-threaded processor.
On pSeries systems on POWER5 or later processors, we measure the
stolen time (time when this partition wasn't running) using the
hypervisor dispatch trace log. We check for new entries in the
log on every entry from user mode and on every transition from
kernel process context to soft or hard IRQ context (i.e. when
account_system_vtime() gets called). So that we can correctly
distinguish time stolen from user time and time stolen from system
time, without having to check the log on every exit to user mode,
we store separate timestamps for exit to user mode and entry from
user mode.
On systems that have a SPURR (POWER6 and POWER7), we read the SPURR
in account_system_vtime() (as before), and then apportion the SPURR
ticks since the last time we read it between scaled user time and
scaled system time according to the relative proportions of user
time and system time over the same interval. This avoids having to
read the SPURR on every kernel entry and exit. On systems that have
PURR but not SPURR (i.e., POWER5), we do the same using the PURR
rather than the SPURR.
This disables the DTL user interface in /sys/debug/kernel/powerpc/dtl
for now since it conflicts with the use of the dispatch trace log
by the time accounting code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-26 19:56:43 +00:00
|
|
|
REST_GPR(0,r1)
|
|
|
|
|
REST_4GPRS(3,r1)
|
|
|
|
|
REST_2GPRS(7,r1)
|
|
|
|
|
addi r9,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
33:
|
|
|
|
|
END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
|
2012-07-25 05:56:04 +00:00
|
|
|
#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
|
powerpc: Account time using timebase rather than PURR
Currently, when CONFIG_VIRT_CPU_ACCOUNTING is enabled, we use the
PURR register for measuring the user and system time used by
processes, as well as other related times such as hardirq and
softirq times. This turns out to be quite confusing for users
because it means that a program will often be measured as taking
less time when run on a multi-threaded processor (SMT2 or SMT4 mode)
than it does when run on a single-threaded processor (ST mode), even
though the program takes longer to finish. The discrepancy is
accounted for as stolen time, which is also confusing, particularly
when there are no other partitions running.
This changes the accounting to use the timebase instead, meaning that
the reported user and system times are the actual number of real-time
seconds that the program was executing on the processor thread,
regardless of which SMT mode the processor is in. Thus a program will
generally show greater user and system times when run on a
multi-threaded processor than on a single-threaded processor.
On pSeries systems on POWER5 or later processors, we measure the
stolen time (time when this partition wasn't running) using the
hypervisor dispatch trace log. We check for new entries in the
log on every entry from user mode and on every transition from
kernel process context to soft or hard IRQ context (i.e. when
account_system_vtime() gets called). So that we can correctly
distinguish time stolen from user time and time stolen from system
time, without having to check the log on every exit to user mode,
we store separate timestamps for exit to user mode and entry from
user mode.
On systems that have a SPURR (POWER6 and POWER7), we read the SPURR
in account_system_vtime() (as before), and then apportion the SPURR
ticks since the last time we read it between scaled user time and
scaled system time according to the relative proportions of user
time and system time over the same interval. This avoids having to
read the SPURR on every kernel entry and exit. On systems that have
PURR but not SPURR (i.e., POWER5), we do the same using the PURR
rather than the SPURR.
This disables the DTL user interface in /sys/debug/kernel/powerpc/dtl
for now since it conflicts with the use of the dispatch trace log
by the time accounting code.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2010-08-26 19:56:43 +00:00
|
|
|
|
2012-03-01 04:40:23 +00:00
|
|
|
/*
|
|
|
|
|
* A syscall should always be called with interrupts enabled
|
|
|
|
|
* so we just unconditionally hard-enable here. When some kind
|
|
|
|
|
* of irq tracing is used, we additionally check that condition
|
|
|
|
|
* is correct
|
|
|
|
|
*/
|
|
|
|
|
#if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
|
|
|
|
|
lbz r10,PACASOFTIRQEN(r13)
|
|
|
|
|
xori r10,r10,1
|
|
|
|
|
1: tdnei r10,0
|
|
|
|
|
EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
|
|
|
|
|
#endif
|
2009-07-23 23:15:59 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
wrteei 1
|
|
|
|
|
#else
|
2012-03-01 04:40:23 +00:00
|
|
|
ld r11,PACAKMSR(r13)
|
2005-10-10 12:36:14 +00:00
|
|
|
ori r11,r11,MSR_EE
|
|
|
|
|
mtmsrd r11,1
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
2005-10-10 12:36:14 +00:00
|
|
|
|
2012-03-01 04:40:23 +00:00
|
|
|
/* We do need to set SOFTE in the stack frame or the return
|
|
|
|
|
* from interrupt will be painful
|
|
|
|
|
*/
|
|
|
|
|
li r10,1
|
|
|
|
|
std r10,SOFTE(r1)
|
|
|
|
|
|
2012-07-05 04:41:35 +00:00
|
|
|
CURRENT_THREAD_INFO(r11, r1)
|
2005-10-10 12:36:14 +00:00
|
|
|
ld r10,TI_FLAGS(r11)
|
2015-01-15 01:01:42 +00:00
|
|
|
andi. r11,r10,_TIF_SYSCALL_DOTRACE
|
2013-01-08 23:47:36 +00:00
|
|
|
bne syscall_dotrace
|
2012-04-04 18:23:27 +00:00
|
|
|
.Lsyscall_dotrace_cont:
|
2005-10-10 12:36:14 +00:00
|
|
|
cmpldi 0,r0,NR_syscalls
|
|
|
|
|
bge- syscall_enosys
|
|
|
|
|
|
|
|
|
|
system_call: /* label this so stack traces look sane */
|
|
|
|
|
/*
|
|
|
|
|
* Need to vector to 32 Bit or default sys_call_table here,
|
|
|
|
|
* based on caller's run-mode / personality.
|
|
|
|
|
*/
|
2014-02-04 05:05:53 +00:00
|
|
|
ld r11,SYS_CALL_TABLE@toc(2)
|
2005-10-10 12:36:14 +00:00
|
|
|
andi. r10,r10,_TIF_32BIT
|
|
|
|
|
beq 15f
|
|
|
|
|
addi r11,r11,8 /* use 32-bit syscall entries */
|
|
|
|
|
clrldi r3,r3,32
|
|
|
|
|
clrldi r4,r4,32
|
|
|
|
|
clrldi r5,r5,32
|
|
|
|
|
clrldi r6,r6,32
|
|
|
|
|
clrldi r7,r7,32
|
|
|
|
|
clrldi r8,r8,32
|
|
|
|
|
15:
|
|
|
|
|
slwi r0,r0,4
|
2014-02-04 05:07:47 +00:00
|
|
|
ldx r12,r11,r0 /* Fetch system call handler [ptr] */
|
|
|
|
|
mtctr r12
|
2005-10-10 12:36:14 +00:00
|
|
|
bctrl /* Call handler */
|
|
|
|
|
|
2014-12-05 10:16:59 +00:00
|
|
|
.Lsyscall_exit:
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
std r3,RESULT(r1)
|
2012-07-05 04:41:35 +00:00
|
|
|
CURRENT_THREAD_INFO(r12, r1)
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
ld r8,_MSR(r1)
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
|
|
|
/* No MSR:RI on BookE */
|
2005-10-10 12:36:14 +00:00
|
|
|
andi. r10,r8,MSR_RI
|
|
|
|
|
beq- unrecov_restore
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif
|
2012-03-01 04:40:23 +00:00
|
|
|
/*
|
|
|
|
|
* Disable interrupts so current_thread_info()->flags can't change,
|
2009-07-23 23:15:59 +00:00
|
|
|
* and so that we don't get interrupted after loading SRR0/1.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
wrteei 0
|
|
|
|
|
#else
|
2012-03-01 04:40:23 +00:00
|
|
|
ld r10,PACAKMSR(r13)
|
2012-05-29 12:22:00 +00:00
|
|
|
/*
|
|
|
|
|
* For performance reasons we clear RI the same time that we
|
|
|
|
|
* clear EE. We only need to clear RI just before we restore r13
|
|
|
|
|
* below, but batching it with EE saves us one expensive mtmsrd call.
|
|
|
|
|
* We have to be careful to restore RI if we branch anywhere from
|
|
|
|
|
* here (eg syscall_exit_work).
|
|
|
|
|
*/
|
|
|
|
|
li r9,MSR_RI
|
|
|
|
|
andc r11,r10,r9
|
|
|
|
|
mtmsrd r11,1
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
|
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
ld r9,TI_FLAGS(r12)
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
li r11,-_LAST_ERRNO
|
2015-01-15 01:01:42 +00:00
|
|
|
andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
|
2005-10-10 12:36:14 +00:00
|
|
|
bne- syscall_exit_work
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
cmpld r3,r11
|
|
|
|
|
ld r5,_CCR(r1)
|
|
|
|
|
bge- syscall_error
|
2012-04-04 18:23:27 +00:00
|
|
|
.Lsyscall_error_cont:
|
2005-10-10 12:36:14 +00:00
|
|
|
ld r7,_NIP(r1)
|
2010-08-11 01:40:27 +00:00
|
|
|
BEGIN_FTR_SECTION
|
2005-10-10 12:36:14 +00:00
|
|
|
stdcx. r0,0,r1 /* to clear the reservation */
|
2010-08-11 01:40:27 +00:00
|
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
|
2005-10-10 12:36:14 +00:00
|
|
|
andi. r6,r8,MSR_PR
|
|
|
|
|
ld r4,_LINK(r1)
|
2009-07-23 23:15:59 +00:00
|
|
|
|
powerpc: Implement accurate task and CPU time accounting
This implements accurate task and cpu time accounting for 64-bit
powerpc kernels. Instead of accounting a whole jiffy of time to a
task on a timer interrupt because that task happened to be running at
the time, we now account time in units of timebase ticks according to
the actual time spent by the task in user mode and kernel mode. We
also count the time spent processing hardware and software interrupts
accurately. This is conditional on CONFIG_VIRT_CPU_ACCOUNTING. If
that is not set, we do tick-based approximate accounting as before.
To get this accurate information, we read either the PURR (processor
utilization of resources register) on POWER5 machines, or the timebase
on other machines on
* each entry to the kernel from usermode
* each exit to usermode
* transitions between process context, hard irq context and soft irq
context in kernel mode
* context switches.
On POWER5 systems with shared-processor logical partitioning we also
read both the PURR and the timebase at each timer interrupt and
context switch in order to determine how much time has been taken by
the hypervisor to run other partitions ("steal" time). Unfortunately,
since we need values of the PURR on both threads at the same time to
accurately calculate the steal time, and since we can only calculate
steal time on a per-core basis, the apportioning of the steal time
between idle time (time which we ceded to the hypervisor in the idle
loop) and actual stolen time is somewhat approximate at the moment.
This is all based quite heavily on what s390 does, and it uses the
generic interfaces that were added by the s390 developers,
i.e. account_system_time(), account_user_time(), etc.
This patch doesn't add any new interfaces between the kernel and
userspace, and doesn't change the units in which time is reported to
userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
times(), etc. Internally the various task and cpu times are stored in
timebase units, but they are converted to USER_HZ units (1/100th of a
second) when reported to userspace. Some precision is therefore lost
but there should not be any accumulating error, since the internal
accumulation is at full precision.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-23 23:06:59 +00:00
|
|
|
beq- 1f
|
|
|
|
|
ACCOUNT_CPU_USER_EXIT(r11, r12)
|
2012-12-06 21:51:04 +00:00
|
|
|
HMT_MEDIUM_LOW_HAS_PPR
|
powerpc: Implement accurate task and CPU time accounting
This implements accurate task and cpu time accounting for 64-bit
powerpc kernels. Instead of accounting a whole jiffy of time to a
task on a timer interrupt because that task happened to be running at
the time, we now account time in units of timebase ticks according to
the actual time spent by the task in user mode and kernel mode. We
also count the time spent processing hardware and software interrupts
accurately. This is conditional on CONFIG_VIRT_CPU_ACCOUNTING. If
that is not set, we do tick-based approximate accounting as before.
To get this accurate information, we read either the PURR (processor
utilization of resources register) on POWER5 machines, or the timebase
on other machines on
* each entry to the kernel from usermode
* each exit to usermode
* transitions between process context, hard irq context and soft irq
context in kernel mode
* context switches.
On POWER5 systems with shared-processor logical partitioning we also
read both the PURR and the timebase at each timer interrupt and
context switch in order to determine how much time has been taken by
the hypervisor to run other partitions ("steal" time). Unfortunately,
since we need values of the PURR on both threads at the same time to
accurately calculate the steal time, and since we can only calculate
steal time on a per-core basis, the apportioning of the steal time
between idle time (time which we ceded to the hypervisor in the idle
loop) and actual stolen time is somewhat approximate at the moment.
This is all based quite heavily on what s390 does, and it uses the
generic interfaces that were added by the s390 developers,
i.e. account_system_time(), account_user_time(), etc.
This patch doesn't add any new interfaces between the kernel and
userspace, and doesn't change the units in which time is reported to
userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
times(), etc. Internally the various task and cpu times are stored in
timebase units, but they are converted to USER_HZ units (1/100th of a
second) when reported to userspace. Some precision is therefore lost
but there should not be any accumulating error, since the internal
accumulation is at full precision.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-02-23 23:06:59 +00:00
|
|
|
ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
|
2005-10-10 12:36:14 +00:00
|
|
|
1: ld r2,GPR2(r1)
|
|
|
|
|
ld r1,GPR1(r1)
|
|
|
|
|
mtlr r4
|
|
|
|
|
mtcr r5
|
|
|
|
|
mtspr SPRN_SRR0,r7
|
|
|
|
|
mtspr SPRN_SRR1,r8
|
2009-07-23 23:15:59 +00:00
|
|
|
RFI
|
2005-10-10 12:36:14 +00:00
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
syscall_error:
|
2005-10-10 12:36:14 +00:00
|
|
|
oris r5,r5,0x1000 /* Set SO bit in CR */
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
neg r3,r3
|
2005-10-10 12:36:14 +00:00
|
|
|
std r5,_CCR(r1)
|
2012-04-04 18:23:27 +00:00
|
|
|
b .Lsyscall_error_cont
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
/* Traced system call support */
|
|
|
|
|
syscall_dotrace:
|
2014-02-04 05:04:35 +00:00
|
|
|
bl save_nvgprs
|
2005-10-10 12:36:14 +00:00
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
2014-02-04 05:04:35 +00:00
|
|
|
bl do_syscall_trace_enter
|
2008-07-27 06:51:03 +00:00
|
|
|
/*
|
|
|
|
|
* Restore argument registers possibly just changed.
|
|
|
|
|
* We use the return value of do_syscall_trace_enter
|
|
|
|
|
* for the call number to look up in the table (r0).
|
|
|
|
|
*/
|
|
|
|
|
mr r0,r3
|
2005-10-10 12:36:14 +00:00
|
|
|
ld r3,GPR3(r1)
|
|
|
|
|
ld r4,GPR4(r1)
|
|
|
|
|
ld r5,GPR5(r1)
|
|
|
|
|
ld r6,GPR6(r1)
|
|
|
|
|
ld r7,GPR7(r1)
|
|
|
|
|
ld r8,GPR8(r1)
|
|
|
|
|
addi r9,r1,STACK_FRAME_OVERHEAD
|
2012-07-05 04:41:35 +00:00
|
|
|
CURRENT_THREAD_INFO(r10, r1)
|
2005-10-10 12:36:14 +00:00
|
|
|
ld r10,TI_FLAGS(r10)
|
2012-04-04 18:23:27 +00:00
|
|
|
b .Lsyscall_dotrace_cont
|
2005-10-10 12:36:14 +00:00
|
|
|
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
syscall_enosys:
|
|
|
|
|
li r3,-ENOSYS
|
2014-12-05 10:16:59 +00:00
|
|
|
b .Lsyscall_exit
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
|
|
|
|
|
syscall_exit_work:
|
2012-05-29 12:22:00 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
|
|
|
mtmsrd r10,1 /* Restore RI */
|
|
|
|
|
#endif
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
/* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
|
|
|
|
|
If TIF_NOERROR is set, just save r3 as it is. */
|
|
|
|
|
|
|
|
|
|
andi. r0,r9,_TIF_RESTOREALL
|
2006-03-08 02:24:22 +00:00
|
|
|
beq+ 0f
|
|
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
b 2f
|
|
|
|
|
0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
blt+ 1f
|
|
|
|
|
andi. r0,r9,_TIF_NOERROR
|
|
|
|
|
bne- 1f
|
|
|
|
|
ld r5,_CCR(r1)
|
|
|
|
|
neg r3,r3
|
|
|
|
|
oris r5,r5,0x1000 /* Set SO bit in CR */
|
|
|
|
|
std r5,_CCR(r1)
|
|
|
|
|
1: std r3,GPR3(r1)
|
|
|
|
|
2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
|
|
|
|
|
beq 4f
|
|
|
|
|
|
2006-03-08 02:24:22 +00:00
|
|
|
/* Clear per-syscall TIF flags if any are set. */
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
|
|
|
|
|
li r11,_TIF_PERSYSCALL_MASK
|
|
|
|
|
addi r12,r12,TI_FLAGS
|
|
|
|
|
3: ldarx r10,0,r12
|
|
|
|
|
andc r10,r10,r11
|
|
|
|
|
stdcx. r10,0,r12
|
|
|
|
|
bne- 3b
|
|
|
|
|
subi r12,r12,TI_FLAGS
|
2006-03-08 02:24:22 +00:00
|
|
|
|
|
|
|
|
4: /* Anything else left to do? */
|
2013-04-15 01:44:14 +00:00
|
|
|
SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */
|
2015-01-15 01:01:42 +00:00
|
|
|
andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
|
2014-02-04 05:04:35 +00:00
|
|
|
beq ret_from_except_lite
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
|
|
|
|
|
/* Re-enable interrupts */
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
wrteei 1
|
|
|
|
|
#else
|
2012-03-01 04:40:23 +00:00
|
|
|
ld r10,PACAKMSR(r13)
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
ori r10,r10,MSR_EE
|
|
|
|
|
mtmsrd r10,1
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
|
2014-02-04 05:04:35 +00:00
|
|
|
bl save_nvgprs
|
2005-10-10 12:36:14 +00:00
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
2014-02-04 05:04:35 +00:00
|
|
|
bl do_syscall_trace_leave
|
|
|
|
|
b ret_from_except
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
/* Save non-volatile GPRs, if not already saved. */
|
|
|
|
|
_GLOBAL(save_nvgprs)
|
|
|
|
|
ld r11,_TRAP(r1)
|
|
|
|
|
andi. r0,r11,1
|
|
|
|
|
beqlr-
|
|
|
|
|
SAVE_NVGPRS(r1)
|
|
|
|
|
clrrdi r0,r11,1
|
|
|
|
|
std r0,_TRAP(r1)
|
|
|
|
|
blr
|
|
|
|
|
|
[PATCH] syscall entry/exit revamp
This cleanup patch speeds up the null syscall path on ppc64 by about 3%,
and brings the ppc32 and ppc64 code slightly closer together.
The ppc64 code was checking current_thread_info()->flags twice in the
syscall exit path; once for TIF_SYSCALL_T_OR_A before disabling
interrupts, and then again for TIF_SIGPENDING|TIF_NEED_RESCHED etc after
disabling interrupts. Now we do the same as ppc32 -- check the flags
only once in the fast path, and re-enable interrupts if necessary in the
ptrace case.
The patch abolishes the 'syscall_noerror' member of struct thread_info
and replaces it with a TIF_NOERROR bit in the flags, which is handled in
the slow path. This shortens the syscall entry code, which no longer
needs to clear syscall_noerror.
The patch adds a TIF_SAVE_NVGPRS flag which causes the syscall exit slow
path to save the non-volatile GPRs into a signal frame. This removes the
need for the assembly wrappers around sys_sigsuspend(),
sys_rt_sigsuspend(), et al which existed solely to save those registers
in advance. It also means I don't have to add new wrappers for ppoll()
and pselect(), which is what I was supposed to be doing when I got
distracted into this...
Finally, it unifies the ppc64 and ppc32 methods of handling syscall exit
directly into a signal handler (as required by sigsuspend et al) by
introducing a TIF_RESTOREALL flag which causes _all_ the registers to be
reloaded from the pt_regs by taking the ret_from_exception path, instead
of the normal syscall exit path which stomps on the callee-saved GPRs.
It appears to pass an LTP test run on ppc64, and passes basic testing on
ppc32 too. Brief tests of ptrace functionality with strace and gdb also
appear OK. I wouldn't send it to Linus for 2.6.15 just yet though :)
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-15 18:52:18 +00:00
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
/*
|
|
|
|
|
* The sigsuspend and rt_sigsuspend system calls can call do_signal
|
|
|
|
|
* and thus put the process into the stopped state where we might
|
|
|
|
|
* want to examine its user state with ptrace. Therefore we need
|
|
|
|
|
* to save all the nonvolatile registers (r14 - r31) before calling
|
|
|
|
|
* the C code. Similarly, fork, vfork and clone need the full
|
|
|
|
|
* register state on the stack so that it can be copied to the child.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
_GLOBAL(ppc_fork)
|
2014-02-04 05:04:35 +00:00
|
|
|
bl save_nvgprs
|
|
|
|
|
bl sys_fork
|
2014-12-05 10:16:59 +00:00
|
|
|
b .Lsyscall_exit
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
_GLOBAL(ppc_vfork)
|
2014-02-04 05:04:35 +00:00
|
|
|
bl save_nvgprs
|
|
|
|
|
bl sys_vfork
|
2014-12-05 10:16:59 +00:00
|
|
|
b .Lsyscall_exit
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
_GLOBAL(ppc_clone)
|
2014-02-04 05:04:35 +00:00
|
|
|
bl save_nvgprs
|
|
|
|
|
bl sys_clone
|
2014-12-05 10:16:59 +00:00
|
|
|
b .Lsyscall_exit
|
2005-10-10 12:36:14 +00:00
|
|
|
|
2006-03-08 02:24:22 +00:00
|
|
|
_GLOBAL(ppc32_swapcontext)
|
2014-02-04 05:04:35 +00:00
|
|
|
bl save_nvgprs
|
|
|
|
|
bl compat_sys_swapcontext
|
2014-12-05 10:16:59 +00:00
|
|
|
b .Lsyscall_exit
|
2006-03-08 02:24:22 +00:00
|
|
|
|
|
|
|
|
_GLOBAL(ppc64_swapcontext)
|
2014-02-04 05:04:35 +00:00
|
|
|
bl save_nvgprs
|
|
|
|
|
bl sys_swapcontext
|
2014-12-05 10:16:59 +00:00
|
|
|
b .Lsyscall_exit
|
2006-03-08 02:24:22 +00:00
|
|
|
|
powerpc: Add a proper syscall for switching endianness
We currently have a "special" syscall for switching endianness. This is
syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall
exception entry.
That has a few problems, firstly the syscall number is outside of the
usual range, which confuses various tools. For example strace doesn't
recognise the syscall at all.
Secondly it's handled explicitly as a special case in the syscall
exception entry, which is complicated enough without it.
As a first step toward removing the special syscall, we need to add a
regular syscall that implements the same functionality.
The logic is simple, it simply toggles the MSR_LE bit in the userspace
MSR. This is the same as the special syscall, with the caveat that the
special syscall clobbers fewer registers.
This version clobbers r9-r12, XER, CTR, and CR0-1,5-7.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-03-28 10:35:16 +00:00
|
|
|
_GLOBAL(ppc_switch_endian)
|
|
|
|
|
bl save_nvgprs
|
|
|
|
|
bl sys_switch_endian
|
|
|
|
|
b .Lsyscall_exit
|
|
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
_GLOBAL(ret_from_fork)
|
2014-02-04 05:04:35 +00:00
|
|
|
bl schedule_tail
|
2005-10-10 12:36:14 +00:00
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
li r3,0
|
2014-12-05 10:16:59 +00:00
|
|
|
b .Lsyscall_exit
|
2005-10-10 12:36:14 +00:00
|
|
|
|
2012-09-12 22:32:42 +00:00
|
|
|
_GLOBAL(ret_from_kernel_thread)
|
2014-02-04 05:04:35 +00:00
|
|
|
bl schedule_tail
|
2012-09-12 22:32:42 +00:00
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
mtlr r14
|
|
|
|
|
mr r3,r15
|
2014-02-04 05:08:51 +00:00
|
|
|
#if defined(_CALL_ELF) && _CALL_ELF == 2
|
|
|
|
|
mr r12,r14
|
|
|
|
|
#endif
|
2012-09-12 22:32:42 +00:00
|
|
|
blrl
|
|
|
|
|
li r3,0
|
2014-12-05 10:16:59 +00:00
|
|
|
b .Lsyscall_exit
|
2012-08-31 19:48:05 +00:00
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
/*
|
|
|
|
|
* This routine switches between two different tasks. The process
|
|
|
|
|
* state of one is saved on its kernel stack. Then the state
|
|
|
|
|
* of the other is restored from its kernel stack. The memory
|
|
|
|
|
* management hardware is updated to the second process's state.
|
|
|
|
|
* Finally, we can return to the second process, via ret_from_except.
|
|
|
|
|
* On entry, r3 points to the THREAD for the current task, r4
|
|
|
|
|
* points to the THREAD for the new task.
|
|
|
|
|
*
|
|
|
|
|
* Note: there are two ways to get to the "going out" portion
|
|
|
|
|
* of this code; either by coming in via the entry (_switch)
|
|
|
|
|
* or via "fork" which must set up an environment equivalent
|
|
|
|
|
* to the "_switch" path. If you change this you'll have to change
|
|
|
|
|
* the fork code also.
|
|
|
|
|
*
|
|
|
|
|
* The code which creates the new task context is in 'copy_thread'
|
2006-01-23 16:58:20 +00:00
|
|
|
* in arch/powerpc/kernel/process.c
|
2005-10-10 12:36:14 +00:00
|
|
|
*/
|
|
|
|
|
.align 7
|
|
|
|
|
_GLOBAL(_switch)
|
|
|
|
|
mflr r0
|
|
|
|
|
std r0,16(r1)
|
|
|
|
|
stdu r1,-SWITCH_FRAME_SIZE(r1)
|
|
|
|
|
/* r3-r13 are caller saved -- Cort */
|
|
|
|
|
SAVE_8GPRS(14, r1)
|
|
|
|
|
SAVE_10GPRS(22, r1)
|
|
|
|
|
mflr r20 /* Return to switch caller */
|
|
|
|
|
mfmsr r22
|
|
|
|
|
li r0, MSR_FP
|
2008-06-25 04:07:18 +00:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
oris r0,r0,MSR_VSX@h /* Disable VSX */
|
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_VSX)
|
|
|
|
|
#endif /* CONFIG_VSX */
|
2005-10-10 12:36:14 +00:00
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
oris r0,r0,MSR_VEC@h /* Disable altivec */
|
|
|
|
|
mfspr r24,SPRN_VRSAVE /* save vrsave register value */
|
|
|
|
|
std r24,THREAD_VRSAVE(r3)
|
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
|
|
|
|
and. r0,r0,r22
|
|
|
|
|
beq+ 1f
|
|
|
|
|
andc r22,r22,r0
|
2009-07-23 23:15:59 +00:00
|
|
|
MTMSRD(r22)
|
2005-10-10 12:36:14 +00:00
|
|
|
isync
|
|
|
|
|
1: std r20,_NIP(r1)
|
|
|
|
|
mfcr r23
|
|
|
|
|
std r23,_CCR(r1)
|
|
|
|
|
std r1,KSP(r3) /* Set old stack pointer */
|
|
|
|
|
|
2013-02-07 15:46:58 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
BEGIN_FTR_SECTION
|
2013-04-30 20:17:04 +00:00
|
|
|
/* Event based branch registers */
|
|
|
|
|
mfspr r0, SPRN_BESCR
|
|
|
|
|
std r0, THREAD_BESCR(r3)
|
|
|
|
|
mfspr r0, SPRN_EBBHR
|
|
|
|
|
std r0, THREAD_EBBHR(r3)
|
|
|
|
|
mfspr r0, SPRN_EBBRR
|
|
|
|
|
std r0, THREAD_EBBRR(r3)
|
2013-04-30 20:17:02 +00:00
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
|
2013-02-07 15:46:58 +00:00
|
|
|
#endif
|
|
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
/* We need a sync somewhere here to make sure that if the
|
|
|
|
|
* previous task gets rescheduled on another CPU, it sees all
|
|
|
|
|
* stores it has performed on this one.
|
|
|
|
|
*/
|
|
|
|
|
sync
|
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
2010-08-11 01:40:27 +00:00
|
|
|
/*
|
|
|
|
|
* If we optimise away the clear of the reservation in system
|
|
|
|
|
* calls because we know the CPU tracks the address of the
|
|
|
|
|
* reservation, then we need to clear it here to cover the
|
|
|
|
|
* case that the kernel context switch path has no larx
|
|
|
|
|
* instructions.
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
ldarx r6,0,r1
|
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
|
|
|
|
|
|
2013-05-29 19:34:27 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
|
|
|
/* Cancel all explict user streams as they will have no use after context
|
|
|
|
|
* switch and will stop the HW from creating streams itself
|
|
|
|
|
*/
|
|
|
|
|
DCBT_STOP_ALL_STREAM_IDS(r6)
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
addi r6,r4,-THREAD /* Convert THREAD to 'current' */
|
|
|
|
|
std r6,PACACURRENT(r13) /* Set new 'current' */
|
|
|
|
|
|
|
|
|
|
ld r8,KSP(r4) /* new stack pointer */
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S
|
2007-10-11 10:37:10 +00:00
|
|
|
BEGIN_FTR_SECTION
|
2005-10-10 12:36:14 +00:00
|
|
|
clrrdi r6,r8,28 /* get its ESID */
|
|
|
|
|
clrrdi r9,r1,28 /* get current sp ESID */
|
2014-07-10 02:29:20 +00:00
|
|
|
FTR_SECTION_ELSE
|
2007-10-11 10:37:10 +00:00
|
|
|
clrrdi r6,r8,40 /* get its 1T ESID */
|
|
|
|
|
clrrdi r9,r1,40 /* get current sp 1T ESID */
|
2014-07-10 02:29:20 +00:00
|
|
|
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
|
2005-10-10 12:36:14 +00:00
|
|
|
clrldi. r0,r6,2 /* is new ESID c00000000? */
|
|
|
|
|
cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
|
|
|
|
|
cror eq,4*cr1+eq,eq
|
|
|
|
|
beq 2f /* if yes, don't slbie it */
|
|
|
|
|
|
|
|
|
|
/* Bolt in the new stack SLB entry */
|
|
|
|
|
ld r7,KSP_VSID(r4) /* Get new stack's VSID */
|
|
|
|
|
oris r0,r6,(SLB_ESID_V)@h
|
|
|
|
|
ori r0,r0,(SLB_NUM_BOLTED-1)@l
|
2007-10-11 10:37:10 +00:00
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
li r9,MMU_SEGSIZE_1T /* insert B field */
|
|
|
|
|
oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
|
|
|
|
|
rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
|
2011-04-06 19:48:50 +00:00
|
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
|
2006-08-07 06:19:19 +00:00
|
|
|
|
2007-08-24 06:58:37 +00:00
|
|
|
/* Update the last bolted SLB. No write barriers are needed
|
|
|
|
|
* here, provided we only update the current CPU's SLB shadow
|
|
|
|
|
* buffer.
|
|
|
|
|
*/
|
2006-08-07 06:19:19 +00:00
|
|
|
ld r9,PACA_SLBSHADOWPTR(r13)
|
2006-08-09 07:00:30 +00:00
|
|
|
li r12,0
|
2013-08-06 16:01:46 +00:00
|
|
|
std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
|
|
|
|
|
li r12,SLBSHADOW_STACKVSID
|
|
|
|
|
STDX_BE r7,r12,r9 /* Save VSID */
|
|
|
|
|
li r12,SLBSHADOW_STACKESID
|
|
|
|
|
STDX_BE r0,r12,r9 /* Save ESID */
|
2006-08-07 06:19:19 +00:00
|
|
|
|
2011-04-06 19:48:50 +00:00
|
|
|
/* No need to check for MMU_FTR_NO_SLBIE_B here, since when
|
2007-10-15 14:58:59 +00:00
|
|
|
* we have 1TB segments, the only CPUs known to have the errata
|
|
|
|
|
* only support less than 1TB of system memory and we'll never
|
|
|
|
|
* actually hit this code path.
|
|
|
|
|
*/
|
|
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
slbie r6
|
|
|
|
|
slbie r6 /* Workaround POWER5 < DD2.1 issue */
|
|
|
|
|
slbmte r7,r0
|
|
|
|
|
isync
|
|
|
|
|
2:
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif /* !CONFIG_PPC_BOOK3S */
|
|
|
|
|
|
2012-07-05 04:41:35 +00:00
|
|
|
CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
|
2005-10-10 12:36:14 +00:00
|
|
|
/* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
|
|
|
|
|
because we don't need to leave the 288-byte ABI gap at the
|
|
|
|
|
top of the kernel stack. */
|
|
|
|
|
addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
|
|
|
|
|
|
|
|
|
|
mr r1,r8 /* start using new stack pointer */
|
|
|
|
|
std r7,PACAKSAVE(r13)
|
|
|
|
|
|
2013-02-07 15:46:58 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
BEGIN_FTR_SECTION
|
2013-04-30 20:17:04 +00:00
|
|
|
/* Event based branch registers */
|
|
|
|
|
ld r0, THREAD_BESCR(r4)
|
|
|
|
|
mtspr SPRN_BESCR, r0
|
|
|
|
|
ld r0, THREAD_EBBHR(r4)
|
|
|
|
|
mtspr SPRN_EBBHR, r0
|
|
|
|
|
ld r0, THREAD_EBBRR(r4)
|
|
|
|
|
mtspr SPRN_EBBRR, r0
|
|
|
|
|
|
2013-02-07 15:46:58 +00:00
|
|
|
ld r0,THREAD_TAR(r4)
|
|
|
|
|
mtspr SPRN_TAR,r0
|
2013-04-30 20:17:02 +00:00
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
|
2013-02-07 15:46:58 +00:00
|
|
|
#endif
|
|
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
ld r0,THREAD_VRSAVE(r4)
|
|
|
|
|
mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
|
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
2011-03-02 15:18:48 +00:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
BEGIN_FTR_SECTION
|
2012-09-03 16:51:10 +00:00
|
|
|
lwz r6,THREAD_DSCR_INHERIT(r4)
|
2011-03-02 15:18:48 +00:00
|
|
|
ld r0,THREAD_DSCR(r4)
|
2012-09-03 16:51:10 +00:00
|
|
|
cmpwi r6,0
|
|
|
|
|
bne 1f
|
2014-05-21 06:32:38 +00:00
|
|
|
ld r0,PACA_DSCR(r13)
|
2013-08-09 07:29:29 +00:00
|
|
|
1:
|
2013-08-26 03:55:57 +00:00
|
|
|
BEGIN_FTR_SECTION_NESTED(70)
|
|
|
|
|
mfspr r8, SPRN_FSCR
|
|
|
|
|
rldimi r8, r6, FSCR_DSCR_LG, (63 - FSCR_DSCR_LG)
|
|
|
|
|
mtspr SPRN_FSCR, r8
|
|
|
|
|
END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
|
|
|
|
|
cmpd r0,r25
|
2012-09-03 16:51:10 +00:00
|
|
|
beq 2f
|
2011-03-02 15:18:48 +00:00
|
|
|
mtspr SPRN_DSCR,r0
|
2012-09-03 16:51:10 +00:00
|
|
|
2:
|
2011-03-02 15:18:48 +00:00
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
|
|
|
|
|
#endif
|
2005-10-10 12:36:14 +00:00
|
|
|
|
2012-09-03 16:51:10 +00:00
|
|
|
ld r6,_CCR(r1)
|
|
|
|
|
mtcrf 0xFF,r6
|
|
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
/* r3-r13 are destroyed -- Cort */
|
|
|
|
|
REST_8GPRS(14, r1)
|
|
|
|
|
REST_10GPRS(22, r1)
|
|
|
|
|
|
|
|
|
|
/* convert old thread to its task_struct for return value */
|
|
|
|
|
addi r3,r3,-THREAD
|
|
|
|
|
ld r7,_NIP(r1) /* Return to _switch caller in new task */
|
|
|
|
|
mtlr r7
|
|
|
|
|
addi r1,r1,SWITCH_FRAME_SIZE
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.align 7
|
|
|
|
|
_GLOBAL(ret_from_except)
|
|
|
|
|
ld r11,_TRAP(r1)
|
|
|
|
|
andi. r0,r11,1
|
2014-02-04 05:04:35 +00:00
|
|
|
bne ret_from_except_lite
|
2005-10-10 12:36:14 +00:00
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
|
|
|
|
|
_GLOBAL(ret_from_except_lite)
|
|
|
|
|
/*
|
|
|
|
|
* Disable interrupts so that current_thread_info()->flags
|
|
|
|
|
* can't change between when we test it and when we return
|
|
|
|
|
* from the interrupt.
|
|
|
|
|
*/
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
wrteei 0
|
|
|
|
|
#else
|
2012-03-02 00:33:52 +00:00
|
|
|
ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
|
|
|
|
|
mtmsrd r10,1 /* Update machine state */
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
2005-10-10 12:36:14 +00:00
|
|
|
|
2012-07-05 04:41:35 +00:00
|
|
|
CURRENT_THREAD_INFO(r9, r1)
|
2005-10-10 12:36:14 +00:00
|
|
|
ld r3,_MSR(r1)
|
2013-05-22 04:20:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
ld r10,PACACURRENT(r13)
|
|
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
2005-10-10 12:36:14 +00:00
|
|
|
ld r4,TI_FLAGS(r9)
|
|
|
|
|
andi. r3,r3,MSR_PR
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
|
|
|
beq resume_kernel
|
2013-05-22 04:20:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
lwz r3,(THREAD+THREAD_DBCR0)(r10)
|
|
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
/* Check current_thread_info()->flags */
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
|
|
|
andi. r0,r4,_TIF_USER_WORK_MASK
|
2013-05-22 04:20:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
bne 1f
|
|
|
|
|
/*
|
|
|
|
|
* Check to see if the dbcr0 register is set up to debug.
|
|
|
|
|
* Use the internal debug mode bit to do this.
|
|
|
|
|
*/
|
|
|
|
|
andis. r0,r3,DBCR0_IDM@h
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
|
|
|
beq restore
|
2013-05-22 04:20:59 +00:00
|
|
|
mfmsr r0
|
|
|
|
|
rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
|
|
|
|
|
mtmsr r0
|
|
|
|
|
mtspr SPRN_DBCR0,r3
|
|
|
|
|
li r10, -1
|
|
|
|
|
mtspr SPRN_DBSR,r10
|
|
|
|
|
b restore
|
|
|
|
|
#else
|
|
|
|
|
beq restore
|
|
|
|
|
#endif
|
|
|
|
|
1: andi. r0,r4,_TIF_NEED_RESCHED
|
|
|
|
|
beq 2f
|
2014-02-04 05:04:35 +00:00
|
|
|
bl restore_interrupts
|
2013-05-13 16:16:43 +00:00
|
|
|
SCHEDULE_USER
|
2014-02-04 05:04:35 +00:00
|
|
|
b ret_from_except_lite
|
powerpc: Don't corrupt transactional state when using FP/VMX in kernel
Currently, when we have a process using the transactional memory
facilities on POWER8 (that is, the processor is in transactional
or suspended state), and the process enters the kernel and the
kernel then uses the floating-point or vector (VMX/Altivec) facility,
we end up corrupting the user-visible FP/VMX/VSX state. This
happens, for example, if a page fault causes a copy-on-write
operation, because the copy_page function will use VMX to do the
copy on POWER8. The test program below demonstrates the bug.
The bug happens because when FP/VMX state for a transactional process
is stored in the thread_struct, we store the checkpointed state in
.fp_state/.vr_state and the transactional (current) state in
.transact_fp/.transact_vr. However, when the kernel wants to use
FP/VMX, it calls enable_kernel_fp() or enable_kernel_altivec(),
which saves the current state in .fp_state/.vr_state. Furthermore,
when we return to the user process we return with FP/VMX/VSX
disabled. The next time the process uses FP/VMX/VSX, we don't know
which set of state (the current register values, .fp_state/.vr_state,
or .transact_fp/.transact_vr) we should be using, since we have no
way to tell if we are still in the same transaction, and if not,
whether the previous transaction succeeded or failed.
Thus it is necessary to strictly adhere to the rule that if FP has
been enabled at any point in a transaction, we must keep FP enabled
for the user process with the current transactional state in the
FP registers, until we detect that it is no longer in a transaction.
Similarly for VMX; once enabled it must stay enabled until the
process is no longer transactional.
In order to keep this rule, we add a new thread_info flag which we
test when returning from the kernel to userspace, called TIF_RESTORE_TM.
This flag indicates that there is FP/VMX/VSX state to be restored
before entering userspace, and when it is set the .tm_orig_msr field
in the thread_struct indicates what state needs to be restored.
The restoration is done by restore_tm_state(). The TIF_RESTORE_TM
bit is set by new giveup_fpu/altivec_maybe_transactional helpers,
which are called from enable_kernel_fp/altivec, giveup_vsx, and
flush_fp/altivec_to_thread instead of giveup_fpu/altivec.
The other thing to be done is to get the transactional FP/VMX/VSX
state from .fp_state/.vr_state when doing reclaim, if that state
has been saved there by giveup_fpu/altivec_maybe_transactional.
Having done this, we set the FP/VMX bit in the thread's MSR after
reclaim to indicate that that part of the state is now valid
(having been reclaimed from the processor's checkpointed state).
Finally, in the signal handling code, we move the clearing of the
transactional state bits in the thread's MSR a bit earlier, before
calling flush_fp_to_thread(), so that we don't unnecessarily set
the TIF_RESTORE_TM bit.
This is the test program:
/* Michael Neuling 4/12/2013
*
* See if the altivec state is leaked out of an aborted transaction due to
* kernel vmx copy loops.
*
* gcc -m64 htm_vmxcopy.c -o htm_vmxcopy
*
*/
/* We don't use all of these, but for reference: */
int main(int argc, char *argv[])
{
long double vecin = 1.3;
long double vecout;
unsigned long pgsize = getpagesize();
int i;
int fd;
int size = pgsize*16;
char tmpfile[] = "/tmp/page_faultXXXXXX";
char buf[pgsize];
char *a;
uint64_t aborted = 0;
fd = mkstemp(tmpfile);
assert(fd >= 0);
memset(buf, 0, pgsize);
for (i = 0; i < size; i += pgsize)
assert(write(fd, buf, pgsize) == pgsize);
unlink(tmpfile);
a = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
assert(a != MAP_FAILED);
asm __volatile__(
"lxvd2x 40,0,%[vecinptr] ; " // set 40 to initial value
TBEGIN
"beq 3f ;"
TSUSPEND
"xxlxor 40,40,40 ; " // set 40 to 0
"std 5, 0(%[map]) ;" // cause kernel vmx copy page
TABORT
TRESUME
TEND
"li %[res], 0 ;"
"b 5f ;"
"3: ;" // Abort handler
"li %[res], 1 ;"
"5: ;"
"stxvd2x 40,0,%[vecoutptr] ; "
: [res]"=r"(aborted)
: [vecinptr]"r"(&vecin),
[vecoutptr]"r"(&vecout),
[map]"r"(a)
: "memory", "r0", "r3", "r4", "r5", "r6", "r7");
if (aborted && (vecin != vecout)){
printf("FAILED: vector state leaked on abort %f != %f\n",
(double)vecin, (double)vecout);
exit(1);
}
munmap(a, size);
close(fd);
printf("PASSED!\n");
return 0;
}
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-01-13 04:56:29 +00:00
|
|
|
2:
|
|
|
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
|
|
|
|
andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
|
|
|
|
|
bne 3f /* only restore TM if nothing else to do */
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
2014-02-04 05:04:35 +00:00
|
|
|
bl restore_tm_state
|
powerpc: Don't corrupt transactional state when using FP/VMX in kernel
Currently, when we have a process using the transactional memory
facilities on POWER8 (that is, the processor is in transactional
or suspended state), and the process enters the kernel and the
kernel then uses the floating-point or vector (VMX/Altivec) facility,
we end up corrupting the user-visible FP/VMX/VSX state. This
happens, for example, if a page fault causes a copy-on-write
operation, because the copy_page function will use VMX to do the
copy on POWER8. The test program below demonstrates the bug.
The bug happens because when FP/VMX state for a transactional process
is stored in the thread_struct, we store the checkpointed state in
.fp_state/.vr_state and the transactional (current) state in
.transact_fp/.transact_vr. However, when the kernel wants to use
FP/VMX, it calls enable_kernel_fp() or enable_kernel_altivec(),
which saves the current state in .fp_state/.vr_state. Furthermore,
when we return to the user process we return with FP/VMX/VSX
disabled. The next time the process uses FP/VMX/VSX, we don't know
which set of state (the current register values, .fp_state/.vr_state,
or .transact_fp/.transact_vr) we should be using, since we have no
way to tell if we are still in the same transaction, and if not,
whether the previous transaction succeeded or failed.
Thus it is necessary to strictly adhere to the rule that if FP has
been enabled at any point in a transaction, we must keep FP enabled
for the user process with the current transactional state in the
FP registers, until we detect that it is no longer in a transaction.
Similarly for VMX; once enabled it must stay enabled until the
process is no longer transactional.
In order to keep this rule, we add a new thread_info flag which we
test when returning from the kernel to userspace, called TIF_RESTORE_TM.
This flag indicates that there is FP/VMX/VSX state to be restored
before entering userspace, and when it is set the .tm_orig_msr field
in the thread_struct indicates what state needs to be restored.
The restoration is done by restore_tm_state(). The TIF_RESTORE_TM
bit is set by new giveup_fpu/altivec_maybe_transactional helpers,
which are called from enable_kernel_fp/altivec, giveup_vsx, and
flush_fp/altivec_to_thread instead of giveup_fpu/altivec.
The other thing to be done is to get the transactional FP/VMX/VSX
state from .fp_state/.vr_state when doing reclaim, if that state
has been saved there by giveup_fpu/altivec_maybe_transactional.
Having done this, we set the FP/VMX bit in the thread's MSR after
reclaim to indicate that that part of the state is now valid
(having been reclaimed from the processor's checkpointed state).
Finally, in the signal handling code, we move the clearing of the
transactional state bits in the thread's MSR a bit earlier, before
calling flush_fp_to_thread(), so that we don't unnecessarily set
the TIF_RESTORE_TM bit.
This is the test program:
/* Michael Neuling 4/12/2013
*
* See if the altivec state is leaked out of an aborted transaction due to
* kernel vmx copy loops.
*
* gcc -m64 htm_vmxcopy.c -o htm_vmxcopy
*
*/
/* We don't use all of these, but for reference: */
int main(int argc, char *argv[])
{
long double vecin = 1.3;
long double vecout;
unsigned long pgsize = getpagesize();
int i;
int fd;
int size = pgsize*16;
char tmpfile[] = "/tmp/page_faultXXXXXX";
char buf[pgsize];
char *a;
uint64_t aborted = 0;
fd = mkstemp(tmpfile);
assert(fd >= 0);
memset(buf, 0, pgsize);
for (i = 0; i < size; i += pgsize)
assert(write(fd, buf, pgsize) == pgsize);
unlink(tmpfile);
a = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
assert(a != MAP_FAILED);
asm __volatile__(
"lxvd2x 40,0,%[vecinptr] ; " // set 40 to initial value
TBEGIN
"beq 3f ;"
TSUSPEND
"xxlxor 40,40,40 ; " // set 40 to 0
"std 5, 0(%[map]) ;" // cause kernel vmx copy page
TABORT
TRESUME
TEND
"li %[res], 0 ;"
"b 5f ;"
"3: ;" // Abort handler
"li %[res], 1 ;"
"5: ;"
"stxvd2x 40,0,%[vecoutptr] ; "
: [res]"=r"(aborted)
: [vecinptr]"r"(&vecin),
[vecoutptr]"r"(&vecout),
[map]"r"(a)
: "memory", "r0", "r3", "r4", "r5", "r6", "r7");
if (aborted && (vecin != vecout)){
printf("FAILED: vector state leaked on abort %f != %f\n",
(double)vecin, (double)vecout);
exit(1);
}
munmap(a, size);
close(fd);
printf("PASSED!\n");
return 0;
}
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-01-13 04:56:29 +00:00
|
|
|
b restore
|
|
|
|
|
3:
|
|
|
|
|
#endif
|
2014-02-04 05:04:35 +00:00
|
|
|
bl save_nvgprs
|
2014-10-31 05:50:57 +00:00
|
|
|
/*
|
|
|
|
|
* Use a non volatile GPR to save and restore our thread_info flags
|
|
|
|
|
* across the call to restore_interrupts.
|
|
|
|
|
*/
|
|
|
|
|
mr r30,r4
|
2014-02-04 05:04:35 +00:00
|
|
|
bl restore_interrupts
|
2014-10-31 05:50:57 +00:00
|
|
|
mr r4,r30
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
2014-02-04 05:04:35 +00:00
|
|
|
bl do_notify_resume
|
|
|
|
|
b ret_from_except
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
|
|
|
|
|
|
|
|
resume_kernel:
|
2012-09-16 23:54:30 +00:00
|
|
|
/* check current_thread_info, _TIF_EMULATE_STACK_STORE */
|
2013-09-26 08:41:34 +00:00
|
|
|
andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
|
2012-09-16 23:54:30 +00:00
|
|
|
beq+ 1f
|
|
|
|
|
|
|
|
|
|
addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
|
|
|
|
|
|
|
|
|
|
lwz r3,GPR1(r1)
|
|
|
|
|
subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
|
|
|
|
|
mr r4,r1 /* src: current exception frame */
|
|
|
|
|
mr r1,r3 /* Reroute the trampoline frame to r1 */
|
|
|
|
|
|
|
|
|
|
/* Copy from the original to the trampoline. */
|
|
|
|
|
li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
|
|
|
|
|
li r6,0 /* start offset: 0 */
|
|
|
|
|
mtctr r5
|
|
|
|
|
2: ldx r0,r6,r4
|
|
|
|
|
stdx r0,r6,r3
|
|
|
|
|
addi r6,r6,8
|
|
|
|
|
bdnz 2b
|
|
|
|
|
|
|
|
|
|
/* Do real store operation to complete stwu */
|
|
|
|
|
lwz r5,GPR1(r1)
|
|
|
|
|
std r8,0(r5)
|
|
|
|
|
|
|
|
|
|
/* Clear _TIF_EMULATE_STACK_STORE flag */
|
|
|
|
|
lis r11,_TIF_EMULATE_STACK_STORE@h
|
|
|
|
|
addi r5,r9,TI_FLAGS
|
2013-04-09 22:31:24 +00:00
|
|
|
0: ldarx r4,0,r5
|
2012-09-16 23:54:30 +00:00
|
|
|
andc r4,r4,r11
|
|
|
|
|
stdcx. r4,0,r5
|
|
|
|
|
bne- 0b
|
|
|
|
|
1:
|
|
|
|
|
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
|
|
|
#ifdef CONFIG_PREEMPT
|
|
|
|
|
/* Check if we need to preempt */
|
|
|
|
|
andi. r0,r4,_TIF_NEED_RESCHED
|
|
|
|
|
beq+ restore
|
|
|
|
|
/* Check that preempt_count() == 0 and interrupts are enabled */
|
|
|
|
|
lwz r8,TI_PREEMPT(r9)
|
|
|
|
|
cmpwi cr1,r8,0
|
|
|
|
|
ld r0,SOFTE(r1)
|
|
|
|
|
cmpdi r0,0
|
|
|
|
|
crandc eq,cr1*4+eq,eq
|
|
|
|
|
bne restore
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Here we are preempting the current task. We want to make
|
2013-07-16 03:09:30 +00:00
|
|
|
* sure we are soft-disabled first and reconcile irq state.
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
|
|
|
*/
|
2013-07-16 03:09:30 +00:00
|
|
|
RECONCILE_IRQ_STATE(r3,r4)
|
2014-02-04 05:04:35 +00:00
|
|
|
1: bl preempt_schedule_irq
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
|
|
|
|
|
|
|
|
/* Re-test flags and eventually loop */
|
2012-07-05 04:41:35 +00:00
|
|
|
CURRENT_THREAD_INFO(r9, r1)
|
2005-10-10 12:36:14 +00:00
|
|
|
ld r4,TI_FLAGS(r9)
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
|
|
|
andi. r0,r4,_TIF_NEED_RESCHED
|
|
|
|
|
bne 1b
|
2013-01-06 00:49:34 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* arch_local_irq_restore() from preempt_schedule_irq above may
|
|
|
|
|
* enable hard interrupt but we really should disable interrupts
|
|
|
|
|
* when we return from the interrupt, and so that we don't get
|
|
|
|
|
* interrupted after loading SRR0/1.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
wrteei 0
|
|
|
|
|
#else
|
|
|
|
|
ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
|
|
|
|
|
mtmsrd r10,1 /* Update machine state */
|
|
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-06 20:56:43 +00:00
|
|
|
#endif /* CONFIG_PREEMPT */
|
2005-10-10 12:36:14 +00:00
|
|
|
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
.globl fast_exc_return_irq
|
|
|
|
|
fast_exc_return_irq:
|
2005-10-10 12:36:14 +00:00
|
|
|
restore:
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
/*
|
2012-05-10 16:12:38 +00:00
|
|
|
* This is the main kernel exit path. First we check if we
|
|
|
|
|
* are about to re-enable interrupts
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
*/
|
2008-07-16 04:21:34 +00:00
|
|
|
ld r5,SOFTE(r1)
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
lbz r6,PACASOFTIRQEN(r13)
|
2012-05-10 16:12:38 +00:00
|
|
|
cmpwi cr0,r5,0
|
|
|
|
|
beq restore_irq_off
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
|
2012-05-10 16:12:38 +00:00
|
|
|
/* We are enabling, were we already enabled ? Yes, just return */
|
|
|
|
|
cmpwi cr0,r6,1
|
|
|
|
|
beq cr0,do_restore
|
2005-10-10 12:36:14 +00:00
|
|
|
|
2012-05-10 16:12:38 +00:00
|
|
|
/*
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
* We are about to soft-enable interrupts (we are hard disabled
|
|
|
|
|
* at this point). We check if there's anything that needs to
|
|
|
|
|
* be replayed first.
|
|
|
|
|
*/
|
|
|
|
|
lbz r0,PACAIRQHAPPENED(r13)
|
|
|
|
|
cmpwi cr0,r0,0
|
|
|
|
|
bne- restore_check_irq_replay
|
2007-02-07 02:13:26 +00:00
|
|
|
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
/*
|
|
|
|
|
* Get here when nothing happened while soft-disabled, just
|
|
|
|
|
* soft-enable and move-on. We will hard-enable as a side
|
|
|
|
|
* effect of rfi
|
|
|
|
|
*/
|
|
|
|
|
restore_no_replay:
|
|
|
|
|
TRACE_ENABLE_INTS
|
|
|
|
|
li r0,1
|
|
|
|
|
stb r0,PACASOFTIRQEN(r13);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Final return path. BookE is handled in a different file
|
|
|
|
|
*/
|
2012-05-10 16:12:38 +00:00
|
|
|
do_restore:
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
2014-02-04 05:04:35 +00:00
|
|
|
b exception_return_book3e
|
2009-07-23 23:15:59 +00:00
|
|
|
#else
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
/*
|
|
|
|
|
* Clear the reservation. If we know the CPU tracks the address of
|
|
|
|
|
* the reservation then we can potentially save some cycles and use
|
|
|
|
|
* a larx. On POWER6 and POWER7 this is significantly faster.
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
stdcx. r0,0,r1 /* to clear the reservation */
|
|
|
|
|
FTR_SECTION_ELSE
|
|
|
|
|
ldarx r4,0,r1
|
|
|
|
|
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Some code path such as load_up_fpu or altivec return directly
|
|
|
|
|
* here. They run entirely hard disabled and do not alter the
|
|
|
|
|
* interrupt state. They also don't use lwarx/stwcx. and thus
|
|
|
|
|
* are known not to leave dangling reservations.
|
|
|
|
|
*/
|
|
|
|
|
.globl fast_exception_return
|
|
|
|
|
fast_exception_return:
|
|
|
|
|
ld r3,_MSR(r1)
|
2007-02-07 02:13:26 +00:00
|
|
|
ld r4,_CTR(r1)
|
|
|
|
|
ld r0,_LINK(r1)
|
|
|
|
|
mtctr r4
|
|
|
|
|
mtlr r0
|
|
|
|
|
ld r4,_XER(r1)
|
|
|
|
|
mtspr SPRN_XER,r4
|
|
|
|
|
|
|
|
|
|
REST_8GPRS(5, r1)
|
|
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
andi. r0,r3,MSR_RI
|
|
|
|
|
beq- unrecov_restore
|
|
|
|
|
|
2013-11-05 05:33:22 +00:00
|
|
|
/* Load PPR from thread struct before we clear MSR:RI */
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
ld r2,PACACURRENT(r13)
|
|
|
|
|
ld r2,TASKTHREADPPR(r2)
|
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
|
|
|
|
|
|
2007-02-07 02:13:26 +00:00
|
|
|
/*
|
|
|
|
|
* Clear RI before restoring r13. If we are returning to
|
|
|
|
|
* userspace and we take an exception after restoring r13,
|
|
|
|
|
* we end up corrupting the userspace r13 value.
|
|
|
|
|
*/
|
2012-03-02 00:33:52 +00:00
|
|
|
ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
|
|
|
|
|
andc r4,r4,r0 /* r0 contains MSR_RI here */
|
2007-02-07 02:13:26 +00:00
|
|
|
mtmsrd r4,1
|
2005-10-10 12:36:14 +00:00
|
|
|
|
2013-02-13 16:21:34 +00:00
|
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
|
|
|
|
/* TM debug */
|
|
|
|
|
std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
|
|
|
|
|
#endif
|
2005-10-10 12:36:14 +00:00
|
|
|
/*
|
|
|
|
|
* r13 is our per cpu area, only restore it if we are returning to
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
* userspace the value stored in the stack frame may belong to
|
|
|
|
|
* another CPU.
|
2005-10-10 12:36:14 +00:00
|
|
|
*/
|
2007-02-07 02:13:26 +00:00
|
|
|
andi. r0,r3,MSR_PR
|
2005-10-10 12:36:14 +00:00
|
|
|
beq 1f
|
2013-11-05 05:33:22 +00:00
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
mtspr SPRN_PPR,r2 /* Restore PPR */
|
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
|
2007-02-07 02:13:26 +00:00
|
|
|
ACCOUNT_CPU_USER_EXIT(r2, r4)
|
2005-10-10 12:36:14 +00:00
|
|
|
REST_GPR(13, r1)
|
|
|
|
|
1:
|
2007-02-07 02:13:26 +00:00
|
|
|
mtspr SPRN_SRR1,r3
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
ld r2,_CCR(r1)
|
|
|
|
|
mtcrf 0xFF,r2
|
|
|
|
|
ld r2,_NIP(r1)
|
|
|
|
|
mtspr SPRN_SRR0,r2
|
|
|
|
|
|
|
|
|
|
ld r0,GPR0(r1)
|
|
|
|
|
ld r2,GPR2(r1)
|
|
|
|
|
ld r3,GPR3(r1)
|
|
|
|
|
ld r4,GPR4(r1)
|
|
|
|
|
ld r1,GPR1(r1)
|
|
|
|
|
|
|
|
|
|
rfid
|
|
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
|
|
|
|
|
2012-05-10 16:12:38 +00:00
|
|
|
/*
|
|
|
|
|
* We are returning to a context with interrupts soft disabled.
|
|
|
|
|
*
|
|
|
|
|
* However, we may also about to hard enable, so we need to
|
|
|
|
|
* make sure that in this case, we also clear PACA_IRQ_HARD_DIS
|
|
|
|
|
* or that bit can get out of sync and bad things will happen
|
|
|
|
|
*/
|
|
|
|
|
restore_irq_off:
|
|
|
|
|
ld r3,_MSR(r1)
|
|
|
|
|
lbz r7,PACAIRQHAPPENED(r13)
|
|
|
|
|
andi. r0,r3,MSR_EE
|
|
|
|
|
beq 1f
|
|
|
|
|
rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
|
|
|
|
|
stb r7,PACAIRQHAPPENED(r13)
|
|
|
|
|
1: li r0,0
|
|
|
|
|
stb r0,PACASOFTIRQEN(r13);
|
|
|
|
|
TRACE_DISABLE_INTS
|
|
|
|
|
b do_restore
|
|
|
|
|
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
/*
|
|
|
|
|
* Something did happen, check if a re-emit is needed
|
|
|
|
|
* (this also clears paca->irq_happened)
|
|
|
|
|
*/
|
|
|
|
|
restore_check_irq_replay:
|
|
|
|
|
/* XXX: We could implement a fast path here where we check
|
|
|
|
|
* for irq_happened being just 0x01, in which case we can
|
|
|
|
|
* clear it and return. That means that we would potentially
|
|
|
|
|
* miss a decrementer having wrapped all the way around.
|
|
|
|
|
*
|
|
|
|
|
* Still, this might be useful for things like hash_page
|
|
|
|
|
*/
|
2014-02-04 05:04:35 +00:00
|
|
|
bl __check_irq_replay
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
cmpwi cr0,r3,0
|
|
|
|
|
beq restore_no_replay
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We need to re-emit an interrupt. We do so by re-using our
|
|
|
|
|
* existing exception frame. We first change the trap value,
|
|
|
|
|
* but we need to ensure we preserve the low nibble of it
|
|
|
|
|
*/
|
|
|
|
|
ld r4,_TRAP(r1)
|
|
|
|
|
clrldi r4,r4,60
|
|
|
|
|
or r4,r4,r3
|
|
|
|
|
std r4,_TRAP(r1)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Then find the right handler and call it. Interrupts are
|
|
|
|
|
* still soft-disabled and we keep them that way.
|
|
|
|
|
*/
|
|
|
|
|
cmpwi cr0,r3,0x500
|
|
|
|
|
bne 1f
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD;
|
2014-02-04 05:04:35 +00:00
|
|
|
bl do_IRQ
|
|
|
|
|
b ret_from_except
|
2014-07-29 13:10:01 +00:00
|
|
|
1: cmpwi cr0,r3,0xe60
|
|
|
|
|
bne 1f
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD;
|
|
|
|
|
bl handle_hmi_exception
|
|
|
|
|
b ret_from_except
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
1: cmpwi cr0,r3,0x900
|
|
|
|
|
bne 1f
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD;
|
2014-02-04 05:04:35 +00:00
|
|
|
bl timer_interrupt
|
|
|
|
|
b ret_from_except
|
2012-11-14 18:49:48 +00:00
|
|
|
#ifdef CONFIG_PPC_DOORBELL
|
|
|
|
|
1:
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
2012-11-14 18:49:48 +00:00
|
|
|
cmpwi cr0,r3,0x280
|
|
|
|
|
#else
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
cmpwi cr0,r3,0xe80
|
|
|
|
|
FTR_SECTION_ELSE
|
|
|
|
|
cmpwi cr0,r3,0xa00
|
|
|
|
|
ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
|
|
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
bne 1f
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD;
|
2014-02-04 05:04:35 +00:00
|
|
|
bl doorbell_exception
|
|
|
|
|
b ret_from_except
|
2012-11-14 18:49:48 +00:00
|
|
|
#endif /* CONFIG_PPC_DOORBELL */
|
2014-02-04 05:04:35 +00:00
|
|
|
1: b ret_from_except /* What else to do here ? */
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
unrecov_restore:
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
2014-02-04 05:04:35 +00:00
|
|
|
bl unrecoverable_exception
|
2005-10-10 12:36:14 +00:00
|
|
|
b unrecov_restore
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_RTAS
|
|
|
|
|
/*
|
|
|
|
|
* On CHRP, the Run-Time Abstraction Services (RTAS) have to be
|
|
|
|
|
* called with the MMU off.
|
|
|
|
|
*
|
|
|
|
|
* In addition, we need to be in 32b mode, at least for now.
|
|
|
|
|
*
|
|
|
|
|
* Note: r3 is an input parameter to rtas, so don't trash it...
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(enter_rtas)
|
|
|
|
|
mflr r0
|
|
|
|
|
std r0,16(r1)
|
|
|
|
|
stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
|
|
|
|
|
|
|
|
|
|
/* Because RTAS is running in 32b mode, it clobbers the high order half
|
|
|
|
|
* of all registers that it saves. We therefore save those registers
|
|
|
|
|
* RTAS might touch to the stack. (r0, r3-r13 are caller saved)
|
|
|
|
|
*/
|
|
|
|
|
SAVE_GPR(2, r1) /* Save the TOC */
|
|
|
|
|
SAVE_GPR(13, r1) /* Save paca */
|
|
|
|
|
SAVE_8GPRS(14, r1) /* Save the non-volatiles */
|
|
|
|
|
SAVE_10GPRS(22, r1) /* ditto */
|
|
|
|
|
|
|
|
|
|
mfcr r4
|
|
|
|
|
std r4,_CCR(r1)
|
|
|
|
|
mfctr r5
|
|
|
|
|
std r5,_CTR(r1)
|
|
|
|
|
mfspr r6,SPRN_XER
|
|
|
|
|
std r6,_XER(r1)
|
|
|
|
|
mfdar r7
|
|
|
|
|
std r7,_DAR(r1)
|
|
|
|
|
mfdsisr r8
|
|
|
|
|
std r8,_DSISR(r1)
|
|
|
|
|
|
2006-03-27 23:20:00 +00:00
|
|
|
/* Temporary workaround to clear CR until RTAS can be modified to
|
|
|
|
|
* ignore all bits.
|
|
|
|
|
*/
|
|
|
|
|
li r0,0
|
|
|
|
|
mtcr r0
|
|
|
|
|
|
2007-01-01 18:45:34 +00:00
|
|
|
#ifdef CONFIG_BUG
|
2005-10-10 12:36:14 +00:00
|
|
|
/* There is no way it is acceptable to get here with interrupts enabled,
|
|
|
|
|
* check it with the asm equivalent of WARN_ON
|
|
|
|
|
*/
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 06:47:49 +00:00
|
|
|
lbz r0,PACASOFTIRQEN(r13)
|
2005-10-10 12:36:14 +00:00
|
|
|
1: tdnei r0,0
|
2007-01-01 18:45:34 +00:00
|
|
|
EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
|
|
|
|
|
#endif
|
|
|
|
|
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 06:47:49 +00:00
|
|
|
/* Hard-disable interrupts */
|
|
|
|
|
mfmsr r6
|
|
|
|
|
rldicl r7,r6,48,1
|
|
|
|
|
rotldi r7,r7,16
|
|
|
|
|
mtmsrd r7,1
|
|
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
/* Unfortunately, the stack pointer and the MSR are also clobbered,
|
|
|
|
|
* so they are saved in the PACA which allows us to restore
|
|
|
|
|
* our original state after RTAS returns.
|
|
|
|
|
*/
|
|
|
|
|
std r1,PACAR1(r13)
|
|
|
|
|
std r6,PACASAVEDMSR(r13)
|
|
|
|
|
|
|
|
|
|
/* Setup our real return addr */
|
2014-02-04 05:04:52 +00:00
|
|
|
LOAD_REG_ADDR(r4,rtas_return_loc)
|
2006-01-13 03:56:25 +00:00
|
|
|
clrldi r4,r4,2 /* convert to realmode address */
|
2005-10-10 12:36:14 +00:00
|
|
|
mtlr r4
|
|
|
|
|
|
|
|
|
|
li r0,0
|
|
|
|
|
ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
|
|
|
|
|
andc r0,r6,r0
|
|
|
|
|
|
|
|
|
|
li r9,1
|
|
|
|
|
rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
|
2013-09-23 02:04:45 +00:00
|
|
|
ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
|
2005-10-10 12:36:14 +00:00
|
|
|
andc r6,r0,r9
|
|
|
|
|
sync /* disable interrupts so SRR0/1 */
|
|
|
|
|
mtmsrd r0 /* don't get trashed */
|
|
|
|
|
|
2006-01-13 03:56:25 +00:00
|
|
|
LOAD_REG_ADDR(r4, rtas)
|
2005-10-10 12:36:14 +00:00
|
|
|
ld r5,RTASENTRY(r4) /* get the rtas->entry value */
|
|
|
|
|
ld r4,RTASBASE(r4) /* get the rtas->base value */
|
|
|
|
|
|
|
|
|
|
mtspr SPRN_SRR0,r5
|
|
|
|
|
mtspr SPRN_SRR1,r6
|
|
|
|
|
rfid
|
|
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
2014-02-04 05:04:52 +00:00
|
|
|
rtas_return_loc:
|
2013-09-23 02:04:45 +00:00
|
|
|
FIXUP_ENDIAN
|
|
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
/* relocation is off at this point */
|
2011-01-20 06:50:21 +00:00
|
|
|
GET_PACA(r4)
|
2006-01-13 03:56:25 +00:00
|
|
|
clrldi r4,r4,2 /* convert to realmode address */
|
2005-10-10 12:36:14 +00:00
|
|
|
|
2008-08-30 01:41:12 +00:00
|
|
|
bcl 20,31,$+4
|
|
|
|
|
0: mflr r3
|
2014-02-04 05:04:52 +00:00
|
|
|
ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
|
2008-08-30 01:41:12 +00:00
|
|
|
|
2005-10-10 12:36:14 +00:00
|
|
|
mfmsr r6
|
|
|
|
|
li r0,MSR_RI
|
|
|
|
|
andc r6,r6,r0
|
|
|
|
|
sync
|
|
|
|
|
mtmsrd r6
|
|
|
|
|
|
|
|
|
|
ld r1,PACAR1(r4) /* Restore our SP */
|
|
|
|
|
ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
|
|
|
|
|
|
|
|
|
|
mtspr SPRN_SRR0,r3
|
|
|
|
|
mtspr SPRN_SRR1,r4
|
|
|
|
|
rfid
|
|
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
2008-08-30 01:41:12 +00:00
|
|
|
.align 3
|
2014-02-04 05:04:52 +00:00
|
|
|
1: .llong rtas_restore_regs
|
2008-08-30 01:41:12 +00:00
|
|
|
|
2014-02-04 05:04:52 +00:00
|
|
|
rtas_restore_regs:
|
2005-10-10 12:36:14 +00:00
|
|
|
/* relocation is on at this point */
|
|
|
|
|
REST_GPR(2, r1) /* Restore the TOC */
|
|
|
|
|
REST_GPR(13, r1) /* Restore paca */
|
|
|
|
|
REST_8GPRS(14, r1) /* Restore the non-volatiles */
|
|
|
|
|
REST_10GPRS(22, r1) /* ditto */
|
|
|
|
|
|
2011-01-20 06:50:21 +00:00
|
|
|
GET_PACA(r13)
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
ld r4,_CCR(r1)
|
|
|
|
|
mtcr r4
|
|
|
|
|
ld r5,_CTR(r1)
|
|
|
|
|
mtctr r5
|
|
|
|
|
ld r6,_XER(r1)
|
|
|
|
|
mtspr SPRN_XER,r6
|
|
|
|
|
ld r7,_DAR(r1)
|
|
|
|
|
mtdar r7
|
|
|
|
|
ld r8,_DSISR(r1)
|
|
|
|
|
mtdsisr r8
|
|
|
|
|
|
|
|
|
|
addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
|
|
|
|
|
ld r0,16(r1) /* get return address */
|
|
|
|
|
|
|
|
|
|
mtlr r0
|
|
|
|
|
blr /* return to caller */
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_PPC_RTAS */
|
|
|
|
|
|
|
|
|
|
_GLOBAL(enter_prom)
|
|
|
|
|
mflr r0
|
|
|
|
|
std r0,16(r1)
|
|
|
|
|
stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
|
|
|
|
|
|
|
|
|
|
/* Because PROM is running in 32b mode, it clobbers the high order half
|
|
|
|
|
* of all registers that it saves. We therefore save those registers
|
|
|
|
|
* PROM might touch to the stack. (r0, r3-r13 are caller saved)
|
|
|
|
|
*/
|
2009-07-23 23:15:07 +00:00
|
|
|
SAVE_GPR(2, r1)
|
2005-10-10 12:36:14 +00:00
|
|
|
SAVE_GPR(13, r1)
|
|
|
|
|
SAVE_8GPRS(14, r1)
|
|
|
|
|
SAVE_10GPRS(22, r1)
|
2009-07-23 23:15:07 +00:00
|
|
|
mfcr r10
|
2005-10-10 12:36:14 +00:00
|
|
|
mfmsr r11
|
2009-07-23 23:15:07 +00:00
|
|
|
std r10,_CCR(r1)
|
2005-10-10 12:36:14 +00:00
|
|
|
std r11,_MSR(r1)
|
|
|
|
|
|
2013-09-23 02:04:45 +00:00
|
|
|
/* Put PROM address in SRR0 */
|
|
|
|
|
mtsrr0 r4
|
|
|
|
|
|
|
|
|
|
/* Setup our trampoline return addr in LR */
|
|
|
|
|
bcl 20,31,$+4
|
|
|
|
|
0: mflr r4
|
|
|
|
|
addi r4,r4,(1f - 0b)
|
|
|
|
|
mtlr r4
|
2005-10-10 12:36:14 +00:00
|
|
|
|
2013-09-23 02:04:45 +00:00
|
|
|
/* Prepare a 32-bit mode big endian MSR
|
2005-10-10 12:36:14 +00:00
|
|
|
*/
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
rlwinm r11,r11,0,1,31
|
2013-09-23 02:04:45 +00:00
|
|
|
mtsrr1 r11
|
|
|
|
|
rfi
|
2009-07-23 23:15:59 +00:00
|
|
|
#else /* CONFIG_PPC_BOOK3E */
|
2013-09-23 02:04:45 +00:00
|
|
|
LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
|
|
|
|
|
andc r11,r11,r12
|
|
|
|
|
mtsrr1 r11
|
|
|
|
|
rfid
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
2005-10-10 12:36:14 +00:00
|
|
|
|
2013-09-23 02:04:45 +00:00
|
|
|
1: /* Return from OF */
|
|
|
|
|
FIXUP_ENDIAN
|
2005-10-10 12:36:14 +00:00
|
|
|
|
|
|
|
|
/* Just make sure that r1 top 32 bits didn't get
|
|
|
|
|
* corrupt by OF
|
|
|
|
|
*/
|
|
|
|
|
rldicl r1,r1,0,32
|
|
|
|
|
|
|
|
|
|
/* Restore the MSR (back to 64 bits) */
|
|
|
|
|
ld r0,_MSR(r1)
|
2009-07-23 23:15:07 +00:00
|
|
|
MTMSRD(r0)
|
2005-10-10 12:36:14 +00:00
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
/* Restore other registers */
|
|
|
|
|
REST_GPR(2, r1)
|
|
|
|
|
REST_GPR(13, r1)
|
|
|
|
|
REST_8GPRS(14, r1)
|
|
|
|
|
REST_10GPRS(22, r1)
|
|
|
|
|
ld r4,_CCR(r1)
|
|
|
|
|
mtcr r4
|
|
|
|
|
|
|
|
|
|
addi r1,r1,PROM_FRAME_SIZE
|
|
|
|
|
ld r0,16(r1)
|
|
|
|
|
mtlr r0
|
|
|
|
|
blr
|
2008-05-15 03:49:44 +00:00
|
|
|
|
2008-10-06 23:06:12 +00:00
|
|
|
#ifdef CONFIG_FUNCTION_TRACER
|
2008-05-15 03:49:44 +00:00
|
|
|
#ifdef CONFIG_DYNAMIC_FTRACE
|
|
|
|
|
_GLOBAL(mcount)
|
|
|
|
|
_GLOBAL(_mcount)
|
|
|
|
|
blr
|
|
|
|
|
|
2014-04-03 22:06:33 +00:00
|
|
|
_GLOBAL_TOC(ftrace_caller)
|
2008-05-15 03:49:44 +00:00
|
|
|
/* Taken from output of objdump from lib64/glibc */
|
|
|
|
|
mflr r3
|
|
|
|
|
ld r11, 0(r1)
|
|
|
|
|
stdu r1, -112(r1)
|
|
|
|
|
std r3, 128(r1)
|
|
|
|
|
ld r4, 16(r11)
|
2008-06-21 18:17:27 +00:00
|
|
|
subi r3, r3, MCOUNT_INSN_SIZE
|
2008-05-15 03:49:44 +00:00
|
|
|
.globl ftrace_call
|
|
|
|
|
ftrace_call:
|
|
|
|
|
bl ftrace_stub
|
|
|
|
|
nop
|
2009-02-11 06:19:54 +00:00
|
|
|
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
|
|
|
|
.globl ftrace_graph_call
|
|
|
|
|
ftrace_graph_call:
|
|
|
|
|
b ftrace_graph_stub
|
|
|
|
|
_GLOBAL(ftrace_graph_stub)
|
|
|
|
|
#endif
|
2008-05-15 03:49:44 +00:00
|
|
|
ld r0, 128(r1)
|
|
|
|
|
mtlr r0
|
|
|
|
|
addi r1, r1, 112
|
|
|
|
|
_GLOBAL(ftrace_stub)
|
|
|
|
|
blr
|
|
|
|
|
#else
|
2014-04-03 22:06:33 +00:00
|
|
|
_GLOBAL_TOC(_mcount)
|
2008-05-15 03:49:44 +00:00
|
|
|
/* Taken from output of objdump from lib64/glibc */
|
|
|
|
|
mflr r3
|
|
|
|
|
ld r11, 0(r1)
|
|
|
|
|
stdu r1, -112(r1)
|
|
|
|
|
std r3, 128(r1)
|
|
|
|
|
ld r4, 16(r11)
|
|
|
|
|
|
2008-06-21 18:17:27 +00:00
|
|
|
subi r3, r3, MCOUNT_INSN_SIZE
|
2008-05-15 03:49:44 +00:00
|
|
|
LOAD_REG_ADDR(r5,ftrace_trace_function)
|
|
|
|
|
ld r5,0(r5)
|
|
|
|
|
ld r5,0(r5)
|
|
|
|
|
mtctr r5
|
|
|
|
|
bctrl
|
|
|
|
|
nop
|
2009-02-10 05:10:27 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
|
|
|
|
b ftrace_graph_caller
|
|
|
|
|
#endif
|
2008-05-15 03:49:44 +00:00
|
|
|
ld r0, 128(r1)
|
|
|
|
|
mtlr r0
|
|
|
|
|
addi r1, r1, 112
|
|
|
|
|
_GLOBAL(ftrace_stub)
|
|
|
|
|
blr
|
|
|
|
|
|
2009-02-10 05:10:27 +00:00
|
|
|
#endif /* CONFIG_DYNAMIC_FTRACE */
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
2009-02-11 06:19:54 +00:00
|
|
|
_GLOBAL(ftrace_graph_caller)
|
2009-02-10 05:10:27 +00:00
|
|
|
/* load r4 with local address */
|
|
|
|
|
ld r4, 128(r1)
|
|
|
|
|
subi r4, r4, MCOUNT_INSN_SIZE
|
|
|
|
|
|
2014-09-17 07:07:04 +00:00
|
|
|
/* Grab the LR out of the caller stack frame */
|
2009-02-10 05:10:27 +00:00
|
|
|
ld r11, 112(r1)
|
2014-09-17 07:07:04 +00:00
|
|
|
ld r3, 16(r11)
|
2009-02-10 05:10:27 +00:00
|
|
|
|
2014-02-04 05:04:35 +00:00
|
|
|
bl prepare_ftrace_return
|
2009-02-10 05:10:27 +00:00
|
|
|
nop
|
|
|
|
|
|
2014-09-17 07:07:04 +00:00
|
|
|
/*
|
|
|
|
|
* prepare_ftrace_return gives us the address we divert to.
|
|
|
|
|
* Change the LR in the callers stack frame to this.
|
|
|
|
|
*/
|
|
|
|
|
ld r11, 112(r1)
|
|
|
|
|
std r3, 16(r11)
|
|
|
|
|
|
2009-02-10 05:10:27 +00:00
|
|
|
ld r0, 128(r1)
|
|
|
|
|
mtlr r0
|
|
|
|
|
addi r1, r1, 112
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
_GLOBAL(return_to_handler)
|
|
|
|
|
/* need to save return values */
|
|
|
|
|
std r4, -32(r1)
|
|
|
|
|
std r3, -24(r1)
|
|
|
|
|
/* save TOC */
|
|
|
|
|
std r2, -16(r1)
|
|
|
|
|
std r31, -8(r1)
|
|
|
|
|
mr r31, r1
|
|
|
|
|
stdu r1, -112(r1)
|
|
|
|
|
|
2009-02-11 20:45:49 +00:00
|
|
|
/*
|
2014-09-17 07:07:03 +00:00
|
|
|
* We might be called from a module.
|
2009-02-11 20:45:49 +00:00
|
|
|
* Switch to our TOC to run inside the core kernel.
|
|
|
|
|
*/
|
2009-09-15 15:30:14 +00:00
|
|
|
ld r2, PACATOC(r13)
|
2009-02-10 05:10:27 +00:00
|
|
|
|
2014-02-04 05:04:35 +00:00
|
|
|
bl ftrace_return_to_handler
|
2009-02-10 05:10:27 +00:00
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
/* return value has real return address */
|
|
|
|
|
mtlr r3
|
|
|
|
|
|
|
|
|
|
ld r1, 0(r1)
|
|
|
|
|
ld r4, -32(r1)
|
|
|
|
|
ld r3, -24(r1)
|
|
|
|
|
ld r2, -16(r1)
|
|
|
|
|
ld r31, -8(r1)
|
|
|
|
|
|
|
|
|
|
/* Jump back to real return address */
|
|
|
|
|
blr
|
|
|
|
|
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
|
|
|
|
|
#endif /* CONFIG_FUNCTION_TRACER */
|
