linux/Documentation/devicetree/bindings/clock/altr_socfpga.txt

Device Tree Clock bindings for Altera's SoCFPGA platform

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be one of the following:
	"altr,socfpga-pll-clock" - for a PLL clock
	"altr,socfpga-perip-clock" - The peripheral clock divided from the
		PLL clock.
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
- clocks : shall be the input parent clock phandle for the clock. This is
	either an oscillator or a pll output.
- #clock-cells : from common clock binding, shall be set to 0.

Optional properties:
- fixed-divider : If clocks have a fixed divider value, use this property.
ARM: socfpga: Add clock entries into device tree Adds the main PLL clock groups for SOCFPGA into device tree file so that the clock framework to query the clock and clock rates appropriately. $cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc1 2 2 25000000 sdram_pll 0 0 400000000 s2f_usr2_clk 0 0 66666666 ddr_dq_clk 0 0 200000000 ddr_2x_dqs_clk 0 0 400000000 ddr_dqs_clk 0 0 200000000 periph_pll 2 2 500000000 s2f_usr1_clk 0 0 50000000 per_base_clk 4 4 100000000 per_nand_mmc_clk 0 0 25000000 per_qsi_clk 0 0 250000000 emac1_clk 1 1 125000000 emac0_clk 0 0 125000000 main_pll 1 1 1600000000 cfg_s2f_usr0_clk 0 0 100000000 main_nand_sdmmc_clk 0 0 100000000 main_qspi_clk 0 0 400000000 dbg_base_clk 0 0 400000000 mainclk 0 0 400000000 mpuclk 1 1 800000000 smp_twd 1 1 200000000 Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Signed-off-by: Olof Johansson <olof@lixom.net> 2013-04-11 15:55:25 +00:00			`Device Tree Clock bindings for Altera's SoCFPGA platform`

			`This binding uses the common clock binding[1].`

			`[1] Documentation/devicetree/bindings/clock/clock-bindings.txt`

			`Required properties:`
			`- compatible : shall be one of the following:`
			`"altr,socfpga-pll-clock" - for a PLL clock`
			`"altr,socfpga-perip-clock" - The peripheral clock divided from the`
			`PLL clock.`
			`- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.`
			`- clocks : shall be the input parent clock phandle for the clock. This is`
			`either an oscillator or a pll output.`
			`- #clock-cells : from common clock binding, shall be set to 0.`

			`Optional properties:`
			`- fixed-divider : If clocks have a fixed divider value, use this property.`