2014-03-17 00:02:46 +00:00
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* Renesas VMSA-Compatible IOMMU
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The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
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It provides address translation for bus masters outside of the CPU, each
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connected to the IPMMU through a port called micro-TLB.
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Required Properties:
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2016-02-29 14:33:09 +00:00
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- compatible: Must contain SoC-specific and generic entry below in case
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the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
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2015-11-17 03:53:20 +00:00
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- "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
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2018-01-24 15:42:00 +00:00
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- "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
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2018-10-04 16:25:47 +00:00
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- "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU.
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2018-01-24 15:42:00 +00:00
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- "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
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2018-08-17 14:31:05 +00:00
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- "renesas,ipmmu-r8a774a1" for the R8A774A1 (RZ/G2M) IPMMU.
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2018-12-13 20:19:28 +00:00
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- "renesas,ipmmu-r8a774c0" for the R8A774C0 (RZ/G2E) IPMMU.
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2015-11-17 03:53:20 +00:00
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- "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
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- "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
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- "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
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- "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
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2016-02-29 14:33:09 +00:00
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- "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.
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2017-12-20 16:48:00 +00:00
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- "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
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2018-06-14 10:48:24 +00:00
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- "renesas,ipmmu-r8a77965" for the R8A77965 (R-Car M3-N) IPMMU.
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2017-12-20 16:48:01 +00:00
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- "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
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2018-06-14 10:48:26 +00:00
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- "renesas,ipmmu-r8a77980" for the R8A77980 (R-Car V3H) IPMMU.
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- "renesas,ipmmu-r8a77990" for the R8A77990 (R-Car E3) IPMMU.
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2017-12-20 16:48:01 +00:00
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- "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
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2018-01-24 15:42:00 +00:00
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- "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
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IPMMU.
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2015-11-17 03:53:20 +00:00
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2014-03-17 00:02:46 +00:00
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- reg: Base address and size of the IPMMU registers.
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- interrupts: Specifiers for the MMU fault interrupts. For instances that
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support secure mode two interrupts must be specified, for non-secure and
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secure mode, in that order. For instances that don't support secure mode a
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2016-02-29 14:33:09 +00:00
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single interrupt must be specified. Not required for cache IPMMUs.
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2014-03-17 00:02:46 +00:00
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- #iommu-cells: Must be 1.
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2016-02-29 14:33:09 +00:00
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Optional properties:
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- renesas,ipmmu-main: reference to the main IPMMU instance in two cells.
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The first cell is a phandle to the main IPMMU and the second cell is
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the interrupt bit number associated with the particular cache IPMMU device.
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The interrupt bit number needs to match the main IPMMU IMSSTR register.
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Only used by cache IPMMU instances.
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2014-03-17 00:02:46 +00:00
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Each bus master connected to an IPMMU must reference the IPMMU in its device
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node with the following property:
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- iommus: A reference to the IPMMU in two cells. The first cell is a phandle
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to the IPMMU and the second cell the number of the micro-TLB that the
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device is connected to.
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Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
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ipmmu_mx: mmu@fe951000 {
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2015-11-17 03:53:20 +00:00
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compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
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2014-03-17 00:02:46 +00:00
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reg = <0 0xfe951000 0 0x1000>;
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interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
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<0 221 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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};
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2017-10-04 12:33:08 +00:00
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vsp@fe928000 {
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2014-03-17 00:02:46 +00:00
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...
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iommus = <&ipmmu_mx 13>;
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...
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};
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