2008-05-23 08:32:46 +00:00
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/*
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2011-01-17 20:25:28 +00:00
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* Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
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2008-05-23 08:32:46 +00:00
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*
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* Author: Tony Li <tony.li@freescale.com>
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* Jason Jin <Jason.jin@freescale.com>
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*
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* The hwirq alloc and free code reuse from sysdev/mpic_msi.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2 of the
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* License.
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*
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*/
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2008-05-23 08:32:46 +00:00
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#include <linux/of_platform.h>
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2014-08-19 11:25:03 +00:00
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#include <linux/interrupt.h>
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2014-08-19 11:25:05 +00:00
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#include <linux/seq_file.h>
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2008-05-23 08:32:46 +00:00
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#include <sysdev/fsl_soc.h>
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#include <asm/prom.h>
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#include <asm/hw_irq.h>
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#include <asm/ppc-pci.h>
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2010-04-22 08:31:35 +00:00
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#include <asm/mpic.h>
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2011-12-13 20:51:59 +00:00
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#include <asm/fsl_hcalls.h>
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2008-05-23 08:32:46 +00:00
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#include "fsl_msi.h"
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2010-08-05 07:45:08 +00:00
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#include "fsl_pci.h"
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2008-05-23 08:32:46 +00:00
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2013-06-21 10:59:14 +00:00
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#define MSIIR_OFFSET_MASK 0xfffff
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#define MSIIR_IBS_SHIFT 0
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#define MSIIR_SRS_SHIFT 5
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#define MSIIR1_IBS_SHIFT 4
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#define MSIIR1_SRS_SHIFT 0
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#define MSI_SRS_MASK 0xf
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#define MSI_IBS_MASK 0x1f
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#define msi_hwirq(msi, msir_index, intr_index) \
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((msir_index) << (msi)->srs_shift | \
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((intr_index) << (msi)->ibs_shift))
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2012-11-30 23:34:59 +00:00
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static LIST_HEAD(msi_head);
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2010-04-22 08:31:36 +00:00
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2008-05-23 08:32:46 +00:00
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struct fsl_msi_feature {
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u32 fsl_pic_ip;
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2011-09-23 17:41:35 +00:00
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u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
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2008-05-23 08:32:46 +00:00
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};
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2010-04-22 08:31:35 +00:00
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struct fsl_msi_cascade_data {
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struct fsl_msi *msi_data;
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int index;
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2014-08-19 11:25:01 +00:00
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int virq;
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2010-04-22 08:31:35 +00:00
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};
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2008-05-23 08:32:46 +00:00
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static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
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{
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return in_be32(base + (reg >> 2));
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}
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/*
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* We do not need this actually. The MSIR register has been read once
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* in the cascade interrupt. So, this MSI interrupt has been acked
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*/
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2011-03-07 13:59:54 +00:00
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static void fsl_msi_end_irq(struct irq_data *d)
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2008-05-23 08:32:46 +00:00
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{
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}
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2014-08-19 11:25:05 +00:00
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static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
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{
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struct fsl_msi *msi_data = irqd->domain->host_data;
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irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
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int cascade_virq, srs;
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srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
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cascade_virq = msi_data->cascade_array[srs]->virq;
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seq_printf(p, " fsl-msi-%d", cascade_virq);
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}
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2008-05-23 08:32:46 +00:00
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static struct irq_chip fsl_msi_chip = {
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2014-11-23 11:23:20 +00:00
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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2011-03-07 13:59:54 +00:00
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.irq_ack = fsl_msi_end_irq,
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2014-08-19 11:25:05 +00:00
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.irq_print_chip = fsl_msi_print_chip,
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2008-05-23 08:32:46 +00:00
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};
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2012-02-14 21:06:50 +00:00
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static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
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2008-05-23 08:32:46 +00:00
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irq_hw_number_t hw)
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{
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2010-03-15 06:38:33 +00:00
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struct fsl_msi *msi_data = h->host_data;
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2008-05-23 08:32:46 +00:00
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struct irq_chip *chip = &fsl_msi_chip;
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2011-03-25 14:43:57 +00:00
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irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
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2008-05-23 08:32:46 +00:00
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2011-03-25 15:45:20 +00:00
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irq_set_chip_data(virq, msi_data);
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irq_set_chip_and_handler(virq, chip, handle_edge_irq);
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2008-05-23 08:32:46 +00:00
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return 0;
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}
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2012-01-26 19:24:34 +00:00
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static const struct irq_domain_ops fsl_msi_host_ops = {
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2008-05-23 08:32:46 +00:00
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.map = fsl_msi_host_map,
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};
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static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
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{
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2013-06-21 10:59:14 +00:00
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int rc, hwirq;
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2008-05-23 08:32:46 +00:00
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2013-06-21 10:59:14 +00:00
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rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
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2015-10-13 11:51:29 +00:00
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irq_domain_get_of_node(msi_data->irqhost));
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2008-08-05 23:10:02 +00:00
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if (rc)
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return rc;
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2008-05-23 08:32:46 +00:00
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2013-06-21 10:59:14 +00:00
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/*
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* Reserve all the hwirqs
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* The available hwirqs will be released in fsl_msi_setup_hwirq()
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*/
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for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
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msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
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2008-05-23 08:32:46 +00:00
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return 0;
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}
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static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct msi_desc *entry;
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2010-03-15 06:38:33 +00:00
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struct fsl_msi *msi_data;
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powerpc/MSI: Fix race condition in tearing down MSI interrupts
This fixes a race which can result in the same virtual IRQ number
being assigned to two different MSI interrupts. The most visible
consequence of that is usually a warning and stack trace from the
sysfs code about an attempt to create a duplicate entry in sysfs.
The race happens when one CPU (say CPU 0) is disposing of an MSI
while another CPU (say CPU 1) is setting up an MSI. CPU 0 calls
(for example) pnv_teardown_msi_irqs(), which calls
msi_bitmap_free_hwirqs() to indicate that the MSI (i.e. its
hardware IRQ number) is no longer in use. Then, before CPU 0 gets
to calling irq_dispose_mapping() to free up the virtal IRQ number,
CPU 1 comes in and calls msi_bitmap_alloc_hwirqs() to allocate an
MSI, and gets the same hardware IRQ number that CPU 0 just freed.
CPU 1 then calls irq_create_mapping() to get a virtual IRQ number,
which sees that there is currently a mapping for that hardware IRQ
number and returns the corresponding virtual IRQ number (which is
the same virtual IRQ number that CPU 0 was using). CPU 0 then
calls irq_dispose_mapping() and frees that virtual IRQ number.
Now, if another CPU comes along and calls irq_create_mapping(), it
is likely to get the virtual IRQ number that was just freed,
resulting in the same virtual IRQ number apparently being used for
two different hardware interrupts.
To fix this race, we just move the call to msi_bitmap_free_hwirqs()
to after the call to irq_dispose_mapping(). Since virq_to_hw()
doesn't work for the virtual IRQ number after irq_dispose_mapping()
has been called, we need to call it before irq_dispose_mapping() and
remember the result for the msi_bitmap_free_hwirqs() call.
The pattern of calling msi_bitmap_free_hwirqs() before
irq_dispose_mapping() appears in 5 places under arch/powerpc, and
appears to have originated in commit 05af7bd2d75e ("[POWERPC] MPIC
U3/U4 MSI backend") from 2007.
Fixes: 05af7bd2d75e ("[POWERPC] MPIC U3/U4 MSI backend")
Cc: stable@vger.kernel.org # v2.6.22+
Reported-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-09-10 04:36:21 +00:00
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irq_hw_number_t hwirq;
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2008-05-23 08:32:46 +00:00
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2015-07-09 08:00:38 +00:00
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for_each_pci_msi_entry(entry, pdev) {
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2016-09-06 11:53:24 +00:00
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if (!entry->irq)
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2008-05-23 08:32:46 +00:00
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continue;
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powerpc/MSI: Fix race condition in tearing down MSI interrupts
This fixes a race which can result in the same virtual IRQ number
being assigned to two different MSI interrupts. The most visible
consequence of that is usually a warning and stack trace from the
sysfs code about an attempt to create a duplicate entry in sysfs.
The race happens when one CPU (say CPU 0) is disposing of an MSI
while another CPU (say CPU 1) is setting up an MSI. CPU 0 calls
(for example) pnv_teardown_msi_irqs(), which calls
msi_bitmap_free_hwirqs() to indicate that the MSI (i.e. its
hardware IRQ number) is no longer in use. Then, before CPU 0 gets
to calling irq_dispose_mapping() to free up the virtal IRQ number,
CPU 1 comes in and calls msi_bitmap_alloc_hwirqs() to allocate an
MSI, and gets the same hardware IRQ number that CPU 0 just freed.
CPU 1 then calls irq_create_mapping() to get a virtual IRQ number,
which sees that there is currently a mapping for that hardware IRQ
number and returns the corresponding virtual IRQ number (which is
the same virtual IRQ number that CPU 0 was using). CPU 0 then
calls irq_dispose_mapping() and frees that virtual IRQ number.
Now, if another CPU comes along and calls irq_create_mapping(), it
is likely to get the virtual IRQ number that was just freed,
resulting in the same virtual IRQ number apparently being used for
two different hardware interrupts.
To fix this race, we just move the call to msi_bitmap_free_hwirqs()
to after the call to irq_dispose_mapping(). Since virq_to_hw()
doesn't work for the virtual IRQ number after irq_dispose_mapping()
has been called, we need to call it before irq_dispose_mapping() and
remember the result for the msi_bitmap_free_hwirqs() call.
The pattern of calling msi_bitmap_free_hwirqs() before
irq_dispose_mapping() appears in 5 places under arch/powerpc, and
appears to have originated in commit 05af7bd2d75e ("[POWERPC] MPIC
U3/U4 MSI backend") from 2007.
Fixes: 05af7bd2d75e ("[POWERPC] MPIC U3/U4 MSI backend")
Cc: stable@vger.kernel.org # v2.6.22+
Reported-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-09-10 04:36:21 +00:00
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hwirq = virq_to_hw(entry->irq);
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2011-05-10 19:30:11 +00:00
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msi_data = irq_get_chip_data(entry->irq);
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2011-03-25 15:45:20 +00:00
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irq_set_msi_desc(entry->irq, NULL);
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2008-05-23 08:32:46 +00:00
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irq_dispose_mapping(entry->irq);
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powerpc/MSI: Fix race condition in tearing down MSI interrupts
This fixes a race which can result in the same virtual IRQ number
being assigned to two different MSI interrupts. The most visible
consequence of that is usually a warning and stack trace from the
sysfs code about an attempt to create a duplicate entry in sysfs.
The race happens when one CPU (say CPU 0) is disposing of an MSI
while another CPU (say CPU 1) is setting up an MSI. CPU 0 calls
(for example) pnv_teardown_msi_irqs(), which calls
msi_bitmap_free_hwirqs() to indicate that the MSI (i.e. its
hardware IRQ number) is no longer in use. Then, before CPU 0 gets
to calling irq_dispose_mapping() to free up the virtal IRQ number,
CPU 1 comes in and calls msi_bitmap_alloc_hwirqs() to allocate an
MSI, and gets the same hardware IRQ number that CPU 0 just freed.
CPU 1 then calls irq_create_mapping() to get a virtual IRQ number,
which sees that there is currently a mapping for that hardware IRQ
number and returns the corresponding virtual IRQ number (which is
the same virtual IRQ number that CPU 0 was using). CPU 0 then
calls irq_dispose_mapping() and frees that virtual IRQ number.
Now, if another CPU comes along and calls irq_create_mapping(), it
is likely to get the virtual IRQ number that was just freed,
resulting in the same virtual IRQ number apparently being used for
two different hardware interrupts.
To fix this race, we just move the call to msi_bitmap_free_hwirqs()
to after the call to irq_dispose_mapping(). Since virq_to_hw()
doesn't work for the virtual IRQ number after irq_dispose_mapping()
has been called, we need to call it before irq_dispose_mapping() and
remember the result for the msi_bitmap_free_hwirqs() call.
The pattern of calling msi_bitmap_free_hwirqs() before
irq_dispose_mapping() appears in 5 places under arch/powerpc, and
appears to have originated in commit 05af7bd2d75e ("[POWERPC] MPIC
U3/U4 MSI backend") from 2007.
Fixes: 05af7bd2d75e ("[POWERPC] MPIC U3/U4 MSI backend")
Cc: stable@vger.kernel.org # v2.6.22+
Reported-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-09-10 04:36:21 +00:00
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msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
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2008-05-23 08:32:46 +00:00
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}
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return;
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}
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static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
|
2010-03-15 06:38:33 +00:00
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struct msi_msg *msg,
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struct fsl_msi *fsl_msi_data)
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2008-05-23 08:32:46 +00:00
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{
|
2010-03-15 06:38:33 +00:00
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struct fsl_msi *msi_data = fsl_msi_data;
|
2009-05-12 20:51:56 +00:00
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
|
2011-09-23 17:41:35 +00:00
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u64 address; /* Physical address of the MSIIR */
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int len;
|
2012-11-30 23:34:59 +00:00
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const __be64 *reg;
|
2011-09-23 17:41:35 +00:00
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/* If the msi-address-64 property exists, then use it */
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reg = of_get_property(hose->dn, "msi-address-64", &len);
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if (reg && (len == sizeof(u64)))
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address = be64_to_cpup(reg);
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else
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address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
|
2008-05-23 08:32:46 +00:00
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|
2011-09-23 17:41:35 +00:00
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msg->address_lo = lower_32_bits(address);
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msg->address_hi = upper_32_bits(address);
|
2009-05-12 20:51:56 +00:00
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|
2015-02-26 07:23:08 +00:00
|
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/*
|
|
|
|
* MPIC version 2.0 has erratum PIC1. It causes
|
|
|
|
* that neither MSI nor MSI-X can work fine.
|
|
|
|
* This is a workaround to allow MSI-X to function
|
|
|
|
* properly. It only works for MSI-X, we prevent
|
|
|
|
* MSI on buggy chips in fsl_setup_msi_irqs().
|
|
|
|
*/
|
|
|
|
if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
|
|
|
|
msg->data = __swab32(hwirq);
|
|
|
|
else
|
|
|
|
msg->data = hwirq;
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2013-06-21 10:59:14 +00:00
|
|
|
pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
|
|
|
|
(hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
|
|
|
|
(hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
|
2008-05-23 08:32:46 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
|
|
|
|
{
|
powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 22:06:35 +00:00
|
|
|
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
|
|
|
|
struct device_node *np;
|
|
|
|
phandle phandle = 0;
|
2010-04-22 08:31:36 +00:00
|
|
|
int rc, hwirq = -ENOMEM;
|
2008-05-23 08:32:46 +00:00
|
|
|
unsigned int virq;
|
|
|
|
struct msi_desc *entry;
|
|
|
|
struct msi_msg msg;
|
2010-03-15 06:38:33 +00:00
|
|
|
struct fsl_msi *msi_data;
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2015-02-26 07:23:08 +00:00
|
|
|
if (type == PCI_CAP_ID_MSI) {
|
|
|
|
/*
|
|
|
|
* MPIC version 2.0 has erratum PIC1. For now MSI
|
|
|
|
* could not work. So check to prevent MSI from
|
|
|
|
* being used on the board with this erratum.
|
|
|
|
*/
|
|
|
|
list_for_each_entry(msi_data, &msi_head, list)
|
|
|
|
if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2014-09-07 18:57:53 +00:00
|
|
|
|
powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 22:06:35 +00:00
|
|
|
/*
|
|
|
|
* If the PCI node has an fsl,msi property, then we need to use it
|
|
|
|
* to find the specific MSI.
|
|
|
|
*/
|
|
|
|
np = of_parse_phandle(hose->dn, "fsl,msi", 0);
|
|
|
|
if (np) {
|
2011-12-13 20:51:59 +00:00
|
|
|
if (of_device_is_compatible(np, "fsl,mpic-msi") ||
|
2014-08-13 13:55:13 +00:00
|
|
|
of_device_is_compatible(np, "fsl,vmpic-msi") ||
|
|
|
|
of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
|
powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 22:06:35 +00:00
|
|
|
phandle = np->phandle;
|
|
|
|
else {
|
2011-12-13 20:51:59 +00:00
|
|
|
dev_err(&pdev->dev,
|
2017-08-21 15:16:47 +00:00
|
|
|
"node %pOF has an invalid fsl,msi phandle %u\n",
|
|
|
|
hose->dn, np->phandle);
|
powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 22:06:35 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-07-09 08:00:38 +00:00
|
|
|
for_each_pci_msi_entry(entry, pdev) {
|
powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 22:06:35 +00:00
|
|
|
/*
|
|
|
|
* Loop over all the MSI devices until we find one that has an
|
|
|
|
* available interrupt.
|
|
|
|
*/
|
2010-04-22 08:31:36 +00:00
|
|
|
list_for_each_entry(msi_data, &msi_head, list) {
|
powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 22:06:35 +00:00
|
|
|
/*
|
|
|
|
* If the PCI node has an fsl,msi property, then we
|
|
|
|
* restrict our search to the corresponding MSI node.
|
|
|
|
* The simplest way is to skip over MSI nodes with the
|
|
|
|
* wrong phandle. Under the Freescale hypervisor, this
|
|
|
|
* has the additional benefit of skipping over MSI
|
|
|
|
* nodes that are not mapped in the PAMU.
|
|
|
|
*/
|
|
|
|
if (phandle && (phandle != msi_data->phandle))
|
|
|
|
continue;
|
|
|
|
|
2010-04-22 08:31:36 +00:00
|
|
|
hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
|
|
|
|
if (hwirq >= 0)
|
|
|
|
break;
|
|
|
|
}
|
2010-03-15 06:38:33 +00:00
|
|
|
|
2008-05-23 08:32:46 +00:00
|
|
|
if (hwirq < 0) {
|
|
|
|
rc = hwirq;
|
2011-12-13 20:51:59 +00:00
|
|
|
dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
|
2008-05-23 08:32:46 +00:00
|
|
|
goto out_free;
|
|
|
|
}
|
|
|
|
|
|
|
|
virq = irq_create_mapping(msi_data->irqhost, hwirq);
|
|
|
|
|
2016-09-06 11:53:24 +00:00
|
|
|
if (!virq) {
|
2011-12-13 20:51:59 +00:00
|
|
|
dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
|
2008-08-05 23:10:02 +00:00
|
|
|
msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
|
2008-05-23 08:32:46 +00:00
|
|
|
rc = -ENOSPC;
|
|
|
|
goto out_free;
|
|
|
|
}
|
2011-05-10 19:30:11 +00:00
|
|
|
/* chip_data is msi_data via host->hostdata in host->map() */
|
2011-03-25 15:45:20 +00:00
|
|
|
irq_set_msi_desc(virq, entry);
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2010-03-15 06:38:33 +00:00
|
|
|
fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
|
2014-11-09 15:10:34 +00:00
|
|
|
pci_write_msi_msg(virq, &msg);
|
2008-05-23 08:32:46 +00:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_free:
|
2010-04-22 08:31:36 +00:00
|
|
|
/* free by the caller of this function */
|
2008-05-23 08:32:46 +00:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2014-08-19 11:25:03 +00:00
|
|
|
static irqreturn_t fsl_msi_cascade(int irq, void *data)
|
2008-05-23 08:32:46 +00:00
|
|
|
{
|
|
|
|
unsigned int cascade_irq;
|
2010-04-22 08:31:35 +00:00
|
|
|
struct fsl_msi *msi_data;
|
2008-05-23 08:32:46 +00:00
|
|
|
int msir_index = -1;
|
|
|
|
u32 msir_value = 0;
|
|
|
|
u32 intr_index;
|
|
|
|
u32 have_shift = 0;
|
2014-08-19 11:25:03 +00:00
|
|
|
struct fsl_msi_cascade_data *cascade_data = data;
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
2010-04-22 08:31:35 +00:00
|
|
|
|
|
|
|
msi_data = cascade_data->msi_data;
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2010-04-22 08:31:35 +00:00
|
|
|
msir_index = cascade_data->index;
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2013-06-21 10:59:14 +00:00
|
|
|
if (msir_index >= NR_MSI_REG_MAX)
|
2016-09-06 11:53:24 +00:00
|
|
|
cascade_irq = 0;
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2010-03-15 06:38:33 +00:00
|
|
|
switch (msi_data->feature & FSL_PIC_IP_MASK) {
|
2008-05-23 08:32:46 +00:00
|
|
|
case FSL_PIC_IP_MPIC:
|
|
|
|
msir_value = fsl_msi_read(msi_data->msi_regs,
|
|
|
|
msir_index * 0x10);
|
|
|
|
break;
|
|
|
|
case FSL_PIC_IP_IPIC:
|
|
|
|
msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
|
|
|
|
break;
|
2012-07-03 05:48:55 +00:00
|
|
|
#ifdef CONFIG_EPAPR_PARAVIRT
|
|
|
|
case FSL_PIC_IP_VMPIC: {
|
|
|
|
unsigned int ret;
|
2011-12-13 20:51:59 +00:00
|
|
|
ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
|
|
|
|
"irq %u (ret=%u)\n", irq, ret);
|
|
|
|
msir_value = 0;
|
|
|
|
}
|
|
|
|
break;
|
2008-05-23 08:32:46 +00:00
|
|
|
}
|
2012-07-03 05:48:55 +00:00
|
|
|
#endif
|
|
|
|
}
|
2008-05-23 08:32:46 +00:00
|
|
|
|
|
|
|
while (msir_value) {
|
|
|
|
intr_index = ffs(msir_value) - 1;
|
|
|
|
|
|
|
|
cascade_irq = irq_linear_revmap(msi_data->irqhost,
|
2013-06-21 10:59:14 +00:00
|
|
|
msi_hwirq(msi_data, msir_index,
|
|
|
|
intr_index + have_shift));
|
2016-09-06 11:53:24 +00:00
|
|
|
if (cascade_irq) {
|
2008-05-23 08:32:46 +00:00
|
|
|
generic_handle_irq(cascade_irq);
|
2014-08-19 11:25:03 +00:00
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
}
|
2008-05-23 13:41:02 +00:00
|
|
|
have_shift += intr_index + 1;
|
|
|
|
msir_value = msir_value >> (intr_index + 1);
|
2008-05-23 08:32:46 +00:00
|
|
|
}
|
|
|
|
|
2014-08-19 11:25:03 +00:00
|
|
|
return ret;
|
2008-05-23 08:32:46 +00:00
|
|
|
}
|
|
|
|
|
2010-07-22 21:52:34 +00:00
|
|
|
static int fsl_of_msi_remove(struct platform_device *ofdev)
|
2010-04-22 08:31:39 +00:00
|
|
|
{
|
2011-05-10 19:30:07 +00:00
|
|
|
struct fsl_msi *msi = platform_get_drvdata(ofdev);
|
2010-04-22 08:31:39 +00:00
|
|
|
int virq, i;
|
|
|
|
|
|
|
|
if (msi->list.prev != NULL)
|
|
|
|
list_del(&msi->list);
|
2013-06-21 10:59:14 +00:00
|
|
|
for (i = 0; i < NR_MSI_REG_MAX; i++) {
|
2014-08-19 11:25:01 +00:00
|
|
|
if (msi->cascade_array[i]) {
|
|
|
|
virq = msi->cascade_array[i]->virq;
|
|
|
|
|
2016-09-06 11:53:24 +00:00
|
|
|
BUG_ON(!virq);
|
2014-08-19 11:25:01 +00:00
|
|
|
|
2014-08-19 11:25:03 +00:00
|
|
|
free_irq(virq, msi->cascade_array[i]);
|
2014-08-19 11:25:01 +00:00
|
|
|
kfree(msi->cascade_array[i]);
|
2010-04-22 08:31:39 +00:00
|
|
|
irq_dispose_mapping(virq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (msi->bitmap.bitmap)
|
|
|
|
msi_bitmap_free(&msi->bitmap);
|
2011-12-13 20:51:59 +00:00
|
|
|
if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
|
|
|
|
iounmap(msi->msi_regs);
|
2010-04-22 08:31:39 +00:00
|
|
|
kfree(msi);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-04-02 13:33:36 +00:00
|
|
|
static struct lock_class_key fsl_msi_irq_class;
|
2017-12-02 17:11:04 +00:00
|
|
|
static struct lock_class_key fsl_msi_irq_request_class;
|
2013-04-02 13:33:36 +00:00
|
|
|
|
2012-12-21 22:04:10 +00:00
|
|
|
static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
|
|
|
|
int offset, int irq_index)
|
2011-01-17 20:25:28 +00:00
|
|
|
{
|
|
|
|
struct fsl_msi_cascade_data *cascade_data = NULL;
|
2014-08-19 11:25:03 +00:00
|
|
|
int virt_msir, i, ret;
|
2011-01-17 20:25:28 +00:00
|
|
|
|
|
|
|
virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
|
2016-09-06 11:53:24 +00:00
|
|
|
if (!virt_msir) {
|
2011-01-17 20:25:28 +00:00
|
|
|
dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
|
|
|
|
__func__, irq_index);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
|
|
|
|
if (!cascade_data) {
|
|
|
|
dev_err(&dev->dev, "No memory for MSI cascade data\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2017-12-02 17:11:04 +00:00
|
|
|
irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class,
|
|
|
|
&fsl_msi_irq_request_class);
|
2011-09-13 21:17:00 +00:00
|
|
|
cascade_data->index = offset;
|
2011-01-17 20:25:28 +00:00
|
|
|
cascade_data->msi_data = msi;
|
2014-08-19 11:25:01 +00:00
|
|
|
cascade_data->virq = virt_msir;
|
|
|
|
msi->cascade_array[irq_index] = cascade_data;
|
2014-08-19 11:25:03 +00:00
|
|
|
|
2014-11-14 05:51:22 +00:00
|
|
|
ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD,
|
2014-08-19 11:25:03 +00:00
|
|
|
"fsl-msi-cascade", cascade_data);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
|
|
|
|
virt_msir, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
2011-01-17 20:25:28 +00:00
|
|
|
|
2013-06-21 10:59:14 +00:00
|
|
|
/* Release the hwirqs corresponding to this MSI register */
|
|
|
|
for (i = 0; i < IRQS_PER_MSI_REG; i++)
|
|
|
|
msi_bitmap_free_hwirqs(&msi->bitmap,
|
|
|
|
msi_hwirq(msi, offset, i), 1);
|
|
|
|
|
2011-01-17 20:25:28 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-05-18 17:19:24 +00:00
|
|
|
static const struct of_device_id fsl_of_msi_ids[];
|
2012-12-21 22:04:10 +00:00
|
|
|
static int fsl_of_msi_probe(struct platform_device *dev)
|
2008-05-23 08:32:46 +00:00
|
|
|
{
|
2011-05-18 17:19:24 +00:00
|
|
|
const struct of_device_id *match;
|
2008-05-23 08:32:46 +00:00
|
|
|
struct fsl_msi *msi;
|
2013-06-21 10:59:14 +00:00
|
|
|
struct resource res, msiir;
|
2011-01-17 20:25:28 +00:00
|
|
|
int err, i, j, irq_index, count;
|
2008-05-23 08:32:46 +00:00
|
|
|
const u32 *p;
|
2012-05-21 19:57:39 +00:00
|
|
|
const struct fsl_msi_feature *features;
|
2010-04-22 08:31:37 +00:00
|
|
|
int len;
|
|
|
|
u32 offset;
|
2015-04-14 04:27:58 +00:00
|
|
|
struct pci_controller *phb;
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2011-05-18 17:19:24 +00:00
|
|
|
match = of_match_device(fsl_of_msi_ids, &dev->dev);
|
|
|
|
if (!match)
|
2011-02-23 02:59:54 +00:00
|
|
|
return -EINVAL;
|
2011-05-18 17:19:24 +00:00
|
|
|
features = match->data;
|
2011-02-23 02:59:54 +00:00
|
|
|
|
2008-05-23 08:32:46 +00:00
|
|
|
printk(KERN_DEBUG "Setting up Freescale MSI support\n");
|
|
|
|
|
|
|
|
msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
|
|
|
|
if (!msi) {
|
|
|
|
dev_err(&dev->dev, "No memory for MSI structure\n");
|
2010-04-22 08:31:39 +00:00
|
|
|
return -ENOMEM;
|
2008-05-23 08:32:46 +00:00
|
|
|
}
|
2011-05-10 19:30:07 +00:00
|
|
|
platform_set_drvdata(dev, msi);
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2012-02-14 21:06:54 +00:00
|
|
|
msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
|
2013-06-21 10:59:14 +00:00
|
|
|
NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
|
2008-05-23 08:32:46 +00:00
|
|
|
|
|
|
|
if (msi->irqhost == NULL) {
|
|
|
|
dev_err(&dev->dev, "No memory for MSI irqhost\n");
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto error_out;
|
|
|
|
}
|
|
|
|
|
2011-12-13 20:51:59 +00:00
|
|
|
/*
|
|
|
|
* Under the Freescale hypervisor, the msi nodes don't have a 'reg'
|
|
|
|
* property. Instead, we use hypercalls to access the MSI.
|
|
|
|
*/
|
|
|
|
if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
|
|
|
|
err = of_address_to_resource(dev->dev.of_node, 0, &res);
|
|
|
|
if (err) {
|
2017-08-21 15:16:47 +00:00
|
|
|
dev_err(&dev->dev, "invalid resource for node %pOF\n",
|
|
|
|
dev->dev.of_node);
|
2011-12-13 20:51:59 +00:00
|
|
|
goto error_out;
|
|
|
|
}
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2011-12-13 20:51:59 +00:00
|
|
|
msi->msi_regs = ioremap(res.start, resource_size(&res));
|
|
|
|
if (!msi->msi_regs) {
|
2012-03-08 22:47:37 +00:00
|
|
|
err = -ENOMEM;
|
2017-08-21 15:16:47 +00:00
|
|
|
dev_err(&dev->dev, "could not map node %pOF\n",
|
|
|
|
dev->dev.of_node);
|
2011-12-13 20:51:59 +00:00
|
|
|
goto error_out;
|
|
|
|
}
|
|
|
|
msi->msiir_offset =
|
|
|
|
features->msiir_offset + (res.start & 0xfffff);
|
2013-06-21 10:59:14 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* First read the MSIIR/MSIIR1 offset from dts
|
|
|
|
* On failure use the hardcode MSIIR offset
|
|
|
|
*/
|
|
|
|
if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
|
|
|
|
msi->msiir_offset = features->msiir_offset +
|
|
|
|
(res.start & MSIIR_OFFSET_MASK);
|
|
|
|
else
|
|
|
|
msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
|
2008-05-23 08:32:46 +00:00
|
|
|
}
|
|
|
|
|
2008-05-23 13:41:02 +00:00
|
|
|
msi->feature = features->fsl_pic_ip;
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2015-02-26 07:23:08 +00:00
|
|
|
/* For erratum PIC1 on MPIC version 2.0*/
|
|
|
|
if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC
|
|
|
|
&& (fsl_mpic_primary_get_version() == 0x0200))
|
|
|
|
msi->feature |= MSI_HW_ERRATA_ENDIAN;
|
|
|
|
|
powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 22:06:35 +00:00
|
|
|
/*
|
|
|
|
* Remember the phandle, so that we can match with any PCI nodes
|
|
|
|
* that have an "fsl,msi" property.
|
|
|
|
*/
|
|
|
|
msi->phandle = dev->dev.of_node->phandle;
|
|
|
|
|
2013-05-07 13:46:36 +00:00
|
|
|
err = fsl_msi_init_allocator(msi);
|
|
|
|
if (err) {
|
2008-05-23 08:32:46 +00:00
|
|
|
dev_err(&dev->dev, "Error allocating MSI bitmap\n");
|
|
|
|
goto error_out;
|
|
|
|
}
|
|
|
|
|
2011-01-17 20:25:28 +00:00
|
|
|
p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
|
|
|
|
|
2014-08-13 13:55:13 +00:00
|
|
|
if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
|
|
|
|
of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
|
2013-06-21 10:59:14 +00:00
|
|
|
msi->srs_shift = MSIIR1_SRS_SHIFT;
|
|
|
|
msi->ibs_shift = MSIIR1_IBS_SHIFT;
|
|
|
|
if (p)
|
|
|
|
dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
|
|
|
|
__func__);
|
|
|
|
|
|
|
|
for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
|
|
|
|
irq_index++) {
|
|
|
|
err = fsl_msi_setup_hwirq(msi, dev,
|
|
|
|
irq_index, irq_index);
|
|
|
|
if (err)
|
|
|
|
goto error_out;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
static const u32 all_avail[] =
|
|
|
|
{ 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
|
2011-01-17 20:25:28 +00:00
|
|
|
|
2013-06-21 10:59:14 +00:00
|
|
|
msi->srs_shift = MSIIR_SRS_SHIFT;
|
|
|
|
msi->ibs_shift = MSIIR_IBS_SHIFT;
|
|
|
|
|
|
|
|
if (p && len % (2 * sizeof(u32)) != 0) {
|
|
|
|
dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
|
|
|
|
__func__);
|
2011-01-17 20:25:28 +00:00
|
|
|
err = -EINVAL;
|
|
|
|
goto error_out;
|
|
|
|
}
|
|
|
|
|
2013-06-21 10:59:14 +00:00
|
|
|
if (!p) {
|
|
|
|
p = all_avail;
|
|
|
|
len = sizeof(all_avail);
|
|
|
|
}
|
2011-01-17 20:25:28 +00:00
|
|
|
|
2013-06-21 10:59:14 +00:00
|
|
|
for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
|
|
|
|
if (p[i * 2] % IRQS_PER_MSI_REG ||
|
|
|
|
p[i * 2 + 1] % IRQS_PER_MSI_REG) {
|
2017-08-21 15:16:47 +00:00
|
|
|
pr_warn("%s: %pOF: msi available range of %u at %u is not IRQ-aligned\n",
|
|
|
|
__func__, dev->dev.of_node,
|
2013-06-21 10:59:14 +00:00
|
|
|
p[i * 2 + 1], p[i * 2]);
|
|
|
|
err = -EINVAL;
|
2010-04-22 08:31:35 +00:00
|
|
|
goto error_out;
|
2013-06-21 10:59:14 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
offset = p[i * 2] / IRQS_PER_MSI_REG;
|
|
|
|
count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
|
|
|
|
|
|
|
|
for (j = 0; j < count; j++, irq_index++) {
|
|
|
|
err = fsl_msi_setup_hwirq(msi, dev, offset + j,
|
|
|
|
irq_index);
|
|
|
|
if (err)
|
|
|
|
goto error_out;
|
|
|
|
}
|
2008-05-23 08:32:46 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-04-22 08:31:36 +00:00
|
|
|
list_add_tail(&msi->list, &msi_head);
|
2008-05-23 08:32:46 +00:00
|
|
|
|
2015-04-14 04:27:58 +00:00
|
|
|
/*
|
|
|
|
* Apply the MSI ops to all the controllers.
|
|
|
|
* It doesn't hurt to reassign the same ops,
|
|
|
|
* but bail out if we find another MSI driver.
|
|
|
|
*/
|
|
|
|
list_for_each_entry(phb, &hose_list, list_node) {
|
|
|
|
if (!phb->controller_ops.setup_msi_irqs) {
|
|
|
|
phb->controller_ops.setup_msi_irqs = fsl_setup_msi_irqs;
|
|
|
|
phb->controller_ops.teardown_msi_irqs = fsl_teardown_msi_irqs;
|
|
|
|
} else if (phb->controller_ops.setup_msi_irqs != fsl_setup_msi_irqs) {
|
|
|
|
dev_err(&dev->dev, "Different MSI driver already installed!\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto error_out;
|
|
|
|
}
|
2010-03-15 06:38:33 +00:00
|
|
|
}
|
2008-05-23 08:32:46 +00:00
|
|
|
return 0;
|
|
|
|
error_out:
|
2010-04-22 08:31:39 +00:00
|
|
|
fsl_of_msi_remove(dev);
|
2008-05-23 08:32:46 +00:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct fsl_msi_feature mpic_msi_feature = {
|
|
|
|
.fsl_pic_ip = FSL_PIC_IP_MPIC,
|
|
|
|
.msiir_offset = 0x140,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct fsl_msi_feature ipic_msi_feature = {
|
|
|
|
.fsl_pic_ip = FSL_PIC_IP_IPIC,
|
|
|
|
.msiir_offset = 0x38,
|
|
|
|
};
|
|
|
|
|
2011-12-13 20:51:59 +00:00
|
|
|
static const struct fsl_msi_feature vmpic_msi_feature = {
|
|
|
|
.fsl_pic_ip = FSL_PIC_IP_VMPIC,
|
|
|
|
.msiir_offset = 0,
|
|
|
|
};
|
|
|
|
|
2008-05-23 08:32:46 +00:00
|
|
|
static const struct of_device_id fsl_of_msi_ids[] = {
|
|
|
|
{
|
|
|
|
.compatible = "fsl,mpic-msi",
|
2012-07-13 16:24:26 +00:00
|
|
|
.data = &mpic_msi_feature,
|
2008-05-23 08:32:46 +00:00
|
|
|
},
|
2013-06-21 10:59:14 +00:00
|
|
|
{
|
|
|
|
.compatible = "fsl,mpic-msi-v4.3",
|
|
|
|
.data = &mpic_msi_feature,
|
|
|
|
},
|
2008-05-23 08:32:46 +00:00
|
|
|
{
|
|
|
|
.compatible = "fsl,ipic-msi",
|
2012-07-13 16:24:26 +00:00
|
|
|
.data = &ipic_msi_feature,
|
2008-05-23 08:32:46 +00:00
|
|
|
},
|
2012-07-03 05:48:55 +00:00
|
|
|
#ifdef CONFIG_EPAPR_PARAVIRT
|
2011-12-13 20:51:59 +00:00
|
|
|
{
|
|
|
|
.compatible = "fsl,vmpic-msi",
|
2012-07-13 16:24:26 +00:00
|
|
|
.data = &vmpic_msi_feature,
|
2011-12-13 20:51:59 +00:00
|
|
|
},
|
2014-08-13 13:55:13 +00:00
|
|
|
{
|
|
|
|
.compatible = "fsl,vmpic-msi-v4.3",
|
|
|
|
.data = &vmpic_msi_feature,
|
|
|
|
},
|
2012-07-03 05:48:55 +00:00
|
|
|
#endif
|
2008-05-23 08:32:46 +00:00
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
2011-02-23 02:59:54 +00:00
|
|
|
static struct platform_driver fsl_of_msi_driver = {
|
2010-04-13 23:13:02 +00:00
|
|
|
.driver = {
|
|
|
|
.name = "fsl-msi",
|
|
|
|
.of_match_table = fsl_of_msi_ids,
|
|
|
|
},
|
2008-05-23 08:32:46 +00:00
|
|
|
.probe = fsl_of_msi_probe,
|
2010-04-22 08:31:39 +00:00
|
|
|
.remove = fsl_of_msi_remove,
|
2008-05-23 08:32:46 +00:00
|
|
|
};
|
|
|
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static __init int fsl_of_msi_init(void)
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{
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2011-02-23 02:59:54 +00:00
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return platform_driver_register(&fsl_of_msi_driver);
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2008-05-23 08:32:46 +00:00
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}
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subsys_initcall(fsl_of_msi_init);
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