2019-06-04 08:10:48 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2015-08-13 07:56:31 +00:00
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/*
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* IEEE754 floating point arithmetic
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* double precision: MADDF.f (Fused Multiply Add)
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* MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft])
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*
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* MIPS floating point support
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* Copyright (C) 2015 Imagination Technologies, Ltd.
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* Author: Markos Chandras <markos.chandras@imgtec.com>
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*/
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#include "ieee754dp.h"
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2016-04-21 13:04:50 +00:00
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2017-07-27 16:08:59 +00:00
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/* 128 bits shift right logical with rounding. */
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2017-11-02 11:14:02 +00:00
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static void srl128(u64 *hptr, u64 *lptr, int count)
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2017-07-27 16:08:59 +00:00
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{
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u64 low;
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if (count >= 128) {
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*lptr = *hptr != 0 || *lptr != 0;
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*hptr = 0;
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} else if (count >= 64) {
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if (count == 64) {
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*lptr = *hptr | (*lptr != 0);
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} else {
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low = *lptr;
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*lptr = *hptr >> (count - 64);
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*lptr |= (*hptr << (128 - count)) != 0 || low != 0;
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}
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*hptr = 0;
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} else {
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low = *lptr;
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*lptr = low >> count | *hptr << (64 - count);
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*lptr |= (low << (64 - count)) != 0;
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*hptr = *hptr >> count;
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}
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}
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2016-04-21 13:04:50 +00:00
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static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
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union ieee754dp y, enum maddf_flags flags)
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2015-08-13 07:56:31 +00:00
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{
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int re;
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int rs;
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2017-11-02 11:13:59 +00:00
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unsigned int lxm;
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unsigned int hxm;
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unsigned int lym;
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unsigned int hym;
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2015-08-13 07:56:31 +00:00
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u64 lrm;
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u64 hrm;
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2017-07-27 16:08:59 +00:00
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u64 lzm;
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u64 hzm;
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2015-08-13 07:56:31 +00:00
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u64 t;
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u64 at;
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int s;
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COMPXDP;
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COMPYDP;
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2016-04-21 13:04:51 +00:00
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COMPZDP;
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2015-08-13 07:56:31 +00:00
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EXPLODEXDP;
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EXPLODEYDP;
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2016-04-21 13:04:51 +00:00
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EXPLODEZDP;
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2015-08-13 07:56:31 +00:00
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FLUSHXDP;
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FLUSHYDP;
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2016-04-21 13:04:51 +00:00
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FLUSHZDP;
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2015-08-13 07:56:31 +00:00
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ieee754_clearcx();
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2020-01-13 10:16:11 +00:00
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rs = xs ^ ys;
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if (flags & MADDF_NEGATE_PRODUCT)
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rs ^= 1;
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if (flags & MADDF_NEGATE_ADDITION)
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zs ^= 1;
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MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix NaN propagation
Fix the cases of <MADDF|MSUBF>.<D|S> when any of three inputs is any
NaN. Correct behavior of <MADDF|MSUBF>.<D|S> fd, fs, ft is following:
- if any of inputs is sNaN, return a sNaN using following rules: if
only one input is sNaN, return that one; if more than one input is
sNaN, order of precedence for return value is fd, fs, ft
- if no input is sNaN, but at least one of inputs is qNaN, return a
qNaN using following rules: if only one input is qNaN, return that
one; if more than one input is qNaN, order of precedence for
return value is fd, fs, ft
The previous code contained correct handling of some above cases, but
not all. Also, such handling was scattered into various cases of
"switch (CLPAIR(xc, yc))" statement, and elsewhere. With this patch,
this logic is placed in one place, and "switch (CLPAIR(xc, yc))" is
significantly simplified.
A relevant example:
MADDF.S fd,fs,ft:
If fs contains qNaN1, ft contains qNaN2, and fd contains qNaN3, fd
is going to contain qNaN3 (without this patch, it used to contain
qNaN1).
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Bo Hu <bohu@google.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: Jin Qian <jinqian@google.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.7+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16886/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-27 16:08:54 +00:00
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/*
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* Handle the cases when at least one of x, y or z is a NaN.
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* Order of precedence is sNaN, qNaN and z, x, y.
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*/
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if (zc == IEEE754_CLASS_SNAN)
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2015-08-13 07:56:31 +00:00
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return ieee754dp_nanxcpt(z);
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MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix NaN propagation
Fix the cases of <MADDF|MSUBF>.<D|S> when any of three inputs is any
NaN. Correct behavior of <MADDF|MSUBF>.<D|S> fd, fs, ft is following:
- if any of inputs is sNaN, return a sNaN using following rules: if
only one input is sNaN, return that one; if more than one input is
sNaN, order of precedence for return value is fd, fs, ft
- if no input is sNaN, but at least one of inputs is qNaN, return a
qNaN using following rules: if only one input is qNaN, return that
one; if more than one input is qNaN, order of precedence for
return value is fd, fs, ft
The previous code contained correct handling of some above cases, but
not all. Also, such handling was scattered into various cases of
"switch (CLPAIR(xc, yc))" statement, and elsewhere. With this patch,
this logic is placed in one place, and "switch (CLPAIR(xc, yc))" is
significantly simplified.
A relevant example:
MADDF.S fd,fs,ft:
If fs contains qNaN1, ft contains qNaN2, and fd contains qNaN3, fd
is going to contain qNaN3 (without this patch, it used to contain
qNaN1).
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Bo Hu <bohu@google.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: Jin Qian <jinqian@google.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.7+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16886/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-27 16:08:54 +00:00
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if (xc == IEEE754_CLASS_SNAN)
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2015-08-13 07:56:31 +00:00
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return ieee754dp_nanxcpt(x);
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MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix NaN propagation
Fix the cases of <MADDF|MSUBF>.<D|S> when any of three inputs is any
NaN. Correct behavior of <MADDF|MSUBF>.<D|S> fd, fs, ft is following:
- if any of inputs is sNaN, return a sNaN using following rules: if
only one input is sNaN, return that one; if more than one input is
sNaN, order of precedence for return value is fd, fs, ft
- if no input is sNaN, but at least one of inputs is qNaN, return a
qNaN using following rules: if only one input is qNaN, return that
one; if more than one input is qNaN, order of precedence for
return value is fd, fs, ft
The previous code contained correct handling of some above cases, but
not all. Also, such handling was scattered into various cases of
"switch (CLPAIR(xc, yc))" statement, and elsewhere. With this patch,
this logic is placed in one place, and "switch (CLPAIR(xc, yc))" is
significantly simplified.
A relevant example:
MADDF.S fd,fs,ft:
If fs contains qNaN1, ft contains qNaN2, and fd contains qNaN3, fd
is going to contain qNaN3 (without this patch, it used to contain
qNaN1).
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Bo Hu <bohu@google.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: Jin Qian <jinqian@google.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.7+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16886/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-27 16:08:54 +00:00
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if (yc == IEEE754_CLASS_SNAN)
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return ieee754dp_nanxcpt(y);
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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if (xc == IEEE754_CLASS_QNAN)
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return x;
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if (yc == IEEE754_CLASS_QNAN)
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2015-08-13 07:56:31 +00:00
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return y;
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MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix NaN propagation
Fix the cases of <MADDF|MSUBF>.<D|S> when any of three inputs is any
NaN. Correct behavior of <MADDF|MSUBF>.<D|S> fd, fs, ft is following:
- if any of inputs is sNaN, return a sNaN using following rules: if
only one input is sNaN, return that one; if more than one input is
sNaN, order of precedence for return value is fd, fs, ft
- if no input is sNaN, but at least one of inputs is qNaN, return a
qNaN using following rules: if only one input is qNaN, return that
one; if more than one input is qNaN, order of precedence for
return value is fd, fs, ft
The previous code contained correct handling of some above cases, but
not all. Also, such handling was scattered into various cases of
"switch (CLPAIR(xc, yc))" statement, and elsewhere. With this patch,
this logic is placed in one place, and "switch (CLPAIR(xc, yc))" is
significantly simplified.
A relevant example:
MADDF.S fd,fs,ft:
If fs contains qNaN1, ft contains qNaN2, and fd contains qNaN3, fd
is going to contain qNaN3 (without this patch, it used to contain
qNaN1).
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Bo Hu <bohu@google.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: Jin Qian <jinqian@google.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.7+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16886/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-27 16:08:54 +00:00
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if (zc == IEEE754_CLASS_DNORM)
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DPDNORMZ;
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/* ZERO z cases are handled separately below */
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2015-08-13 07:56:31 +00:00
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MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix NaN propagation
Fix the cases of <MADDF|MSUBF>.<D|S> when any of three inputs is any
NaN. Correct behavior of <MADDF|MSUBF>.<D|S> fd, fs, ft is following:
- if any of inputs is sNaN, return a sNaN using following rules: if
only one input is sNaN, return that one; if more than one input is
sNaN, order of precedence for return value is fd, fs, ft
- if no input is sNaN, but at least one of inputs is qNaN, return a
qNaN using following rules: if only one input is qNaN, return that
one; if more than one input is qNaN, order of precedence for
return value is fd, fs, ft
The previous code contained correct handling of some above cases, but
not all. Also, such handling was scattered into various cases of
"switch (CLPAIR(xc, yc))" statement, and elsewhere. With this patch,
this logic is placed in one place, and "switch (CLPAIR(xc, yc))" is
significantly simplified.
A relevant example:
MADDF.S fd,fs,ft:
If fs contains qNaN1, ft contains qNaN2, and fd contains qNaN3, fd
is going to contain qNaN3 (without this patch, it used to contain
qNaN1).
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Bo Hu <bohu@google.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: Jin Qian <jinqian@google.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.7+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16886/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-27 16:08:54 +00:00
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switch (CLPAIR(xc, yc)) {
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2015-08-13 07:56:31 +00:00
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/*
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* Infinity handling
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*/
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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return ieee754dp_indef();
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
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2020-01-13 10:16:11 +00:00
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if ((zc == IEEE754_CLASS_INF) && (zs != rs)) {
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MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix some cases of infinite inputs
Fix the cases of <MADDF|MSUBF>.<D|S> when any of two multiplicands is
infinity. The correct behavior in such cases is affected by the nature
of third input. Cases of addition of infinities with opposite signs
and subtraction of infinities with same signs may arise and must be
handles separately. Also, the value od flags argument (that determines
whether the instruction is MADDF or MSUBF) affects the outcome.
Relevant examples:
MADDF.S fd,fs,ft:
If fs contains +inf, ft contains +inf, and fd contains -inf, fd is
going to contain indef (without this patch, it used to contain
-inf).
MSUBF.S fd,fs,ft:
If fs contains +inf, ft contains 1.0, and fd contains +0.0, fd is
going to contain -inf (without this patch, it used to contain +inf).
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: Bo Hu <bohu@google.com>
Cc: Jin Qian <jinqian@google.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.7+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16887/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-27 16:08:55 +00:00
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/*
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* Cases of addition of infinities with opposite signs
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* or subtraction of infinities with same signs.
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*/
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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return ieee754dp_indef();
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}
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/*
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* z is here either not an infinity, or an infinity having the
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2020-01-13 10:16:11 +00:00
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* same sign as product (x*y). The result must be an infinity,
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* and its sign is determined only by the sign of product (x*y).
|
MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix some cases of infinite inputs
Fix the cases of <MADDF|MSUBF>.<D|S> when any of two multiplicands is
infinity. The correct behavior in such cases is affected by the nature
of third input. Cases of addition of infinities with opposite signs
and subtraction of infinities with same signs may arise and must be
handles separately. Also, the value od flags argument (that determines
whether the instruction is MADDF or MSUBF) affects the outcome.
Relevant examples:
MADDF.S fd,fs,ft:
If fs contains +inf, ft contains +inf, and fd contains -inf, fd is
going to contain indef (without this patch, it used to contain
-inf).
MSUBF.S fd,fs,ft:
If fs contains +inf, ft contains 1.0, and fd contains +0.0, fd is
going to contain -inf (without this patch, it used to contain +inf).
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: Bo Hu <bohu@google.com>
Cc: Jin Qian <jinqian@google.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.7+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16887/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-27 16:08:55 +00:00
|
|
|
*/
|
2020-01-13 10:16:11 +00:00
|
|
|
return ieee754dp_inf(rs);
|
2015-08-13 07:56:31 +00:00
|
|
|
|
|
|
|
case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
|
|
|
|
case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
|
|
|
|
case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
|
|
|
|
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
|
|
|
|
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
|
|
|
|
if (zc == IEEE754_CLASS_INF)
|
|
|
|
return ieee754dp_inf(zs);
|
2017-07-27 16:08:56 +00:00
|
|
|
if (zc == IEEE754_CLASS_ZERO) {
|
|
|
|
/* Handle cases +0 + (-0) and similar ones. */
|
2020-01-13 10:16:11 +00:00
|
|
|
if (zs == rs)
|
2017-07-27 16:08:56 +00:00
|
|
|
/*
|
|
|
|
* Cases of addition of zeros of equal signs
|
|
|
|
* or subtraction of zeroes of opposite signs.
|
|
|
|
* The sign of the resulting zero is in any
|
|
|
|
* such case determined only by the sign of z.
|
|
|
|
*/
|
|
|
|
return z;
|
|
|
|
|
|
|
|
return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
|
|
|
|
}
|
|
|
|
/* x*y is here 0, and z is not 0, so just return z */
|
2015-08-13 07:56:31 +00:00
|
|
|
return z;
|
|
|
|
|
|
|
|
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
|
|
|
|
DPDNORMX;
|
2020-05-04 08:51:29 +00:00
|
|
|
fallthrough;
|
2015-08-13 07:56:31 +00:00
|
|
|
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
|
MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix NaN propagation
Fix the cases of <MADDF|MSUBF>.<D|S> when any of three inputs is any
NaN. Correct behavior of <MADDF|MSUBF>.<D|S> fd, fs, ft is following:
- if any of inputs is sNaN, return a sNaN using following rules: if
only one input is sNaN, return that one; if more than one input is
sNaN, order of precedence for return value is fd, fs, ft
- if no input is sNaN, but at least one of inputs is qNaN, return a
qNaN using following rules: if only one input is qNaN, return that
one; if more than one input is qNaN, order of precedence for
return value is fd, fs, ft
The previous code contained correct handling of some above cases, but
not all. Also, such handling was scattered into various cases of
"switch (CLPAIR(xc, yc))" statement, and elsewhere. With this patch,
this logic is placed in one place, and "switch (CLPAIR(xc, yc))" is
significantly simplified.
A relevant example:
MADDF.S fd,fs,ft:
If fs contains qNaN1, ft contains qNaN2, and fd contains qNaN3, fd
is going to contain qNaN3 (without this patch, it used to contain
qNaN1).
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Bo Hu <bohu@google.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: Jin Qian <jinqian@google.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.7+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16886/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-27 16:08:54 +00:00
|
|
|
if (zc == IEEE754_CLASS_INF)
|
2015-08-13 07:56:31 +00:00
|
|
|
return ieee754dp_inf(zs);
|
|
|
|
DPDNORMY;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
|
MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix NaN propagation
Fix the cases of <MADDF|MSUBF>.<D|S> when any of three inputs is any
NaN. Correct behavior of <MADDF|MSUBF>.<D|S> fd, fs, ft is following:
- if any of inputs is sNaN, return a sNaN using following rules: if
only one input is sNaN, return that one; if more than one input is
sNaN, order of precedence for return value is fd, fs, ft
- if no input is sNaN, but at least one of inputs is qNaN, return a
qNaN using following rules: if only one input is qNaN, return that
one; if more than one input is qNaN, order of precedence for
return value is fd, fs, ft
The previous code contained correct handling of some above cases, but
not all. Also, such handling was scattered into various cases of
"switch (CLPAIR(xc, yc))" statement, and elsewhere. With this patch,
this logic is placed in one place, and "switch (CLPAIR(xc, yc))" is
significantly simplified.
A relevant example:
MADDF.S fd,fs,ft:
If fs contains qNaN1, ft contains qNaN2, and fd contains qNaN3, fd
is going to contain qNaN3 (without this patch, it used to contain
qNaN1).
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Bo Hu <bohu@google.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: Jin Qian <jinqian@google.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.7+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16886/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-27 16:08:54 +00:00
|
|
|
if (zc == IEEE754_CLASS_INF)
|
2015-08-13 07:56:31 +00:00
|
|
|
return ieee754dp_inf(zs);
|
|
|
|
DPDNORMX;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
|
MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix NaN propagation
Fix the cases of <MADDF|MSUBF>.<D|S> when any of three inputs is any
NaN. Correct behavior of <MADDF|MSUBF>.<D|S> fd, fs, ft is following:
- if any of inputs is sNaN, return a sNaN using following rules: if
only one input is sNaN, return that one; if more than one input is
sNaN, order of precedence for return value is fd, fs, ft
- if no input is sNaN, but at least one of inputs is qNaN, return a
qNaN using following rules: if only one input is qNaN, return that
one; if more than one input is qNaN, order of precedence for
return value is fd, fs, ft
The previous code contained correct handling of some above cases, but
not all. Also, such handling was scattered into various cases of
"switch (CLPAIR(xc, yc))" statement, and elsewhere. With this patch,
this logic is placed in one place, and "switch (CLPAIR(xc, yc))" is
significantly simplified.
A relevant example:
MADDF.S fd,fs,ft:
If fs contains qNaN1, ft contains qNaN2, and fd contains qNaN3, fd
is going to contain qNaN3 (without this patch, it used to contain
qNaN1).
Fixes: e24c3bec3e8e ("MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instruction")
Fixes: 83d43305a1df ("MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction")
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Bo Hu <bohu@google.com>
Cc: Douglas Leung <douglas.leung@imgtec.com>
Cc: Jin Qian <jinqian@google.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>
Cc: Raghu Gandham <raghu.gandham@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.7+
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16886/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-07-27 16:08:54 +00:00
|
|
|
if (zc == IEEE754_CLASS_INF)
|
2015-08-13 07:56:31 +00:00
|
|
|
return ieee754dp_inf(zs);
|
MIPS: math-emu: Mark fall throughs in switch statements with a comment
Mark intentional fall throughs in switch statements with a consistent
comment.
In most of the cases, a new comment line containing text "fall through"
is inserted. In some of the cases, existing comment contained a variation
of the text "fall through" (for example, "FALL THROUGH" or "drop through").
In such cases, the existing comment is modified to contain "fall through".
Lastly, in two cases, code segments were described in comments as "fall
througs", but were in reality "breaks out" of switch statement. In such
cases, existing comments are accordingly modified.
Apart from making code easier to follow and debug, this change enables
some static code analysers to interpret newly inserted comments as their
annotations (and, therefore, not issue warnings of type "fall through in
switch statement", which is desireable, since marked fallthroughs are
intentional).
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
Cc: Douglas Leung <douglas.leung@mips.com>
Cc: Goran Ferenc <goran.ferenc@mips.com>
Cc: James Hogan <james.hogan@mips.com>
Cc: Maciej W. Rozycki <macro@mips.com>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Miodrag Dinic <miodrag.dinic@mips.com>
Cc: Paul Burton <paul.burton@mips.com>
Cc: Petar Jovanovic <petar.jovanovic@mips.com>
Cc: Raghu Gandham <raghu.gandham@mips.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17588/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-11-02 11:14:05 +00:00
|
|
|
/* continue to real computations */
|
2015-08-13 07:56:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Finally get to do some computation */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Do the multiplication bit first
|
|
|
|
*
|
|
|
|
* rm = xm * ym, re = xe + ye basically
|
|
|
|
*
|
|
|
|
* At this point xm and ym should have been normalized.
|
|
|
|
*/
|
|
|
|
assert(xm & DP_HIDDEN_BIT);
|
|
|
|
assert(ym & DP_HIDDEN_BIT);
|
|
|
|
|
|
|
|
re = xe + ye;
|
|
|
|
|
|
|
|
/* shunt to top of word */
|
|
|
|
xm <<= 64 - (DP_FBITS + 1);
|
|
|
|
ym <<= 64 - (DP_FBITS + 1);
|
|
|
|
|
|
|
|
/*
|
2017-07-27 16:08:59 +00:00
|
|
|
* Multiply 64 bits xm and ym to give 128 bits result in hrm:lrm.
|
2015-08-13 07:56:31 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
lxm = xm;
|
|
|
|
hxm = xm >> 32;
|
|
|
|
lym = ym;
|
|
|
|
hym = ym >> 32;
|
|
|
|
|
|
|
|
lrm = DPXMULT(lxm, lym);
|
|
|
|
hrm = DPXMULT(hxm, hym);
|
|
|
|
|
|
|
|
t = DPXMULT(lxm, hym);
|
|
|
|
|
|
|
|
at = lrm + (t << 32);
|
|
|
|
hrm += at < lrm;
|
|
|
|
lrm = at;
|
|
|
|
|
|
|
|
hrm = hrm + (t >> 32);
|
|
|
|
|
|
|
|
t = DPXMULT(hxm, lym);
|
|
|
|
|
|
|
|
at = lrm + (t << 32);
|
|
|
|
hrm += at < lrm;
|
|
|
|
lrm = at;
|
|
|
|
|
|
|
|
hrm = hrm + (t >> 32);
|
|
|
|
|
2017-07-27 16:08:59 +00:00
|
|
|
/* Put explicit bit at bit 126 if necessary */
|
|
|
|
if ((int64_t)hrm < 0) {
|
|
|
|
lrm = (hrm << 63) | (lrm >> 1);
|
|
|
|
hrm = hrm >> 1;
|
2016-04-21 13:04:53 +00:00
|
|
|
re++;
|
2015-08-13 07:56:31 +00:00
|
|
|
}
|
|
|
|
|
2017-07-27 16:08:59 +00:00
|
|
|
assert(hrm & (1 << 62));
|
2017-06-19 15:50:12 +00:00
|
|
|
|
2017-07-27 16:08:59 +00:00
|
|
|
if (zc == IEEE754_CLASS_ZERO) {
|
|
|
|
/*
|
|
|
|
* Move explicit bit from bit 126 to bit 55 since the
|
|
|
|
* ieee754dp_format code expects the mantissa to be
|
|
|
|
* 56 bits wide (53 + 3 rounding bits).
|
|
|
|
*/
|
|
|
|
srl128(&hrm, &lrm, (126 - 55));
|
|
|
|
return ieee754dp_format(rs, re, lrm);
|
|
|
|
}
|
2015-08-13 07:56:31 +00:00
|
|
|
|
2017-07-27 16:08:59 +00:00
|
|
|
/* Move explicit bit from bit 52 to bit 126 */
|
|
|
|
lzm = 0;
|
|
|
|
hzm = zm << 10;
|
|
|
|
assert(hzm & (1 << 62));
|
2015-08-13 07:56:31 +00:00
|
|
|
|
2017-07-27 16:08:59 +00:00
|
|
|
/* Make the exponents the same */
|
2015-08-13 07:56:31 +00:00
|
|
|
if (ze > re) {
|
|
|
|
/*
|
|
|
|
* Have to shift y fraction right to align.
|
|
|
|
*/
|
|
|
|
s = ze - re;
|
2017-07-27 16:08:59 +00:00
|
|
|
srl128(&hrm, &lrm, s);
|
2015-08-13 07:56:31 +00:00
|
|
|
re += s;
|
|
|
|
} else if (re > ze) {
|
|
|
|
/*
|
|
|
|
* Have to shift x fraction right to align.
|
|
|
|
*/
|
|
|
|
s = re - ze;
|
2017-07-27 16:08:59 +00:00
|
|
|
srl128(&hzm, &lzm, s);
|
2015-08-13 07:56:31 +00:00
|
|
|
ze += s;
|
|
|
|
}
|
|
|
|
assert(ze == re);
|
|
|
|
assert(ze <= DP_EMAX);
|
|
|
|
|
2017-07-27 16:08:59 +00:00
|
|
|
/* Do the addition */
|
2015-08-13 07:56:31 +00:00
|
|
|
if (zs == rs) {
|
|
|
|
/*
|
2017-07-27 16:08:59 +00:00
|
|
|
* Generate 128 bit result by adding two 127 bit numbers
|
|
|
|
* leaving result in hzm:lzm, zs and ze.
|
2015-08-13 07:56:31 +00:00
|
|
|
*/
|
2017-07-27 16:08:59 +00:00
|
|
|
hzm = hzm + hrm + (lzm > (lzm + lrm));
|
|
|
|
lzm = lzm + lrm;
|
|
|
|
if ((int64_t)hzm < 0) { /* carry out */
|
|
|
|
srl128(&hzm, &lzm, 1);
|
2015-08-13 07:56:31 +00:00
|
|
|
ze++;
|
|
|
|
}
|
|
|
|
} else {
|
2017-07-27 16:08:59 +00:00
|
|
|
if (hzm > hrm || (hzm == hrm && lzm >= lrm)) {
|
|
|
|
hzm = hzm - hrm - (lzm < lrm);
|
|
|
|
lzm = lzm - lrm;
|
2015-08-13 07:56:31 +00:00
|
|
|
} else {
|
2017-07-27 16:08:59 +00:00
|
|
|
hzm = hrm - hzm - (lrm < lzm);
|
|
|
|
lzm = lrm - lzm;
|
2015-08-13 07:56:31 +00:00
|
|
|
zs = rs;
|
|
|
|
}
|
2017-07-27 16:08:59 +00:00
|
|
|
if (lzm == 0 && hzm == 0)
|
2015-08-13 07:56:31 +00:00
|
|
|
return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
|
|
|
|
|
|
|
|
/*
|
2017-07-27 16:08:59 +00:00
|
|
|
* Put explicit bit at bit 126 if necessary.
|
2015-08-13 07:56:31 +00:00
|
|
|
*/
|
2017-07-27 16:08:59 +00:00
|
|
|
if (hzm == 0) {
|
|
|
|
/* left shift by 63 or 64 bits */
|
|
|
|
if ((int64_t)lzm < 0) {
|
|
|
|
/* MSB of lzm is the explicit bit */
|
|
|
|
hzm = lzm >> 1;
|
|
|
|
lzm = lzm << 63;
|
|
|
|
ze -= 63;
|
|
|
|
} else {
|
|
|
|
hzm = lzm;
|
|
|
|
lzm = 0;
|
|
|
|
ze -= 64;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
t = 0;
|
|
|
|
while ((hzm >> (62 - t)) == 0)
|
|
|
|
t++;
|
|
|
|
|
|
|
|
assert(t <= 62);
|
|
|
|
if (t) {
|
|
|
|
hzm = hzm << t | lzm >> (64 - t);
|
|
|
|
lzm = lzm << t;
|
|
|
|
ze -= t;
|
2015-08-13 07:56:31 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-27 16:08:59 +00:00
|
|
|
/*
|
|
|
|
* Move explicit bit from bit 126 to bit 55 since the
|
|
|
|
* ieee754dp_format code expects the mantissa to be
|
|
|
|
* 56 bits wide (53 + 3 rounding bits).
|
|
|
|
*/
|
|
|
|
srl128(&hzm, &lzm, (126 - 55));
|
|
|
|
|
|
|
|
return ieee754dp_format(zs, ze, lzm);
|
2015-08-13 07:56:31 +00:00
|
|
|
}
|
2016-04-21 13:04:50 +00:00
|
|
|
|
|
|
|
union ieee754dp ieee754dp_maddf(union ieee754dp z, union ieee754dp x,
|
|
|
|
union ieee754dp y)
|
|
|
|
{
|
|
|
|
return _dp_maddf(z, x, y, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
union ieee754dp ieee754dp_msubf(union ieee754dp z, union ieee754dp x,
|
|
|
|
union ieee754dp y)
|
|
|
|
{
|
2017-07-27 16:08:57 +00:00
|
|
|
return _dp_maddf(z, x, y, MADDF_NEGATE_PRODUCT);
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2016-04-21 13:04:50 +00:00
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}
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2020-01-13 10:16:11 +00:00
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union ieee754dp ieee754dp_madd(union ieee754dp z, union ieee754dp x,
|
|
|
|
union ieee754dp y)
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|
|
|
{
|
|
|
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return _dp_maddf(z, x, y, 0);
|
|
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}
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|
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union ieee754dp ieee754dp_msub(union ieee754dp z, union ieee754dp x,
|
|
|
|
union ieee754dp y)
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|
|
|
{
|
|
|
|
return _dp_maddf(z, x, y, MADDF_NEGATE_ADDITION);
|
|
|
|
}
|
|
|
|
|
|
|
|
union ieee754dp ieee754dp_nmadd(union ieee754dp z, union ieee754dp x,
|
|
|
|
union ieee754dp y)
|
|
|
|
{
|
|
|
|
return _dp_maddf(z, x, y, MADDF_NEGATE_PRODUCT|MADDF_NEGATE_ADDITION);
|
|
|
|
}
|
|
|
|
|
|
|
|
union ieee754dp ieee754dp_nmsub(union ieee754dp z, union ieee754dp x,
|
|
|
|
union ieee754dp y)
|
|
|
|
{
|
|
|
|
return _dp_maddf(z, x, y, MADDF_NEGATE_PRODUCT);
|
|
|
|
}
|