2010-04-01 11:30:58 +00:00
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/*
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* arch/arm/mach-spear3xx/spear310.c
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*
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* SPEAr310 machine source file
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*
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2012-03-22 18:47:43 +00:00
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* Copyright (C) 2009-2012 ST Microelectronics
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* Viresh Kumar <viresh.kumar@st.com>
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2010-04-01 11:30:58 +00:00
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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2012-03-26 05:09:43 +00:00
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#define pr_fmt(fmt) "SPEAr310: " fmt
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2012-03-22 18:47:43 +00:00
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#include <linux/amba/pl08x.h>
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#include <linux/amba/serial.h>
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#include <linux/of_platform.h>
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#include <asm/hardware/vic.h>
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#include <asm/mach/arch.h>
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2011-03-07 04:57:01 +00:00
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#include <plat/shirq.h>
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2010-04-01 11:30:58 +00:00
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#include <mach/generic.h>
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2012-04-11 17:30:11 +00:00
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#include <mach/spear.h>
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#define SPEAR310_UART1_BASE UL(0xB2000000)
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#define SPEAR310_UART2_BASE UL(0xB2080000)
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#define SPEAR310_UART3_BASE UL(0xB2100000)
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#define SPEAR310_UART4_BASE UL(0xB2180000)
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#define SPEAR310_UART5_BASE UL(0xB2200000)
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#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
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/* Interrupt registers offsets and masks */
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#define SPEAR310_INT_STS_MASK_REG 0x04
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#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
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#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
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#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
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#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
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#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
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#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
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#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
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#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
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#define SPEAR310_UART1_IRQ_MASK (1 << 8)
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#define SPEAR310_UART2_IRQ_MASK (1 << 9)
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#define SPEAR310_UART3_IRQ_MASK (1 << 10)
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#define SPEAR310_UART4_IRQ_MASK (1 << 11)
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#define SPEAR310_UART5_IRQ_MASK (1 << 12)
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#define SPEAR310_EMI_IRQ_MASK (1 << 13)
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#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
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#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
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#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
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#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
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#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
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#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
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#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
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/* SPEAr310 Virtual irq definitions */
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/* IRQs sharing IRQ_GEN_RAS_1 */
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#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
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#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
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#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
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#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
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#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
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#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
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#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
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#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
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/* IRQs sharing IRQ_GEN_RAS_2 */
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#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
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#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
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#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
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#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
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#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
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/* IRQs sharing IRQ_GEN_RAS_3 */
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#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
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#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
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/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
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#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
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#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
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#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
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2010-04-01 11:30:58 +00:00
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2010-05-03 08:24:30 +00:00
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/* spear3xx shared irq */
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2011-05-20 07:34:20 +00:00
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static struct shirq_dev_config shirq_ras1_config[] = {
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2010-05-03 08:24:30 +00:00
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{
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_SMII0,
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.status_mask = SPEAR310_SMII0_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_SMII1,
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.status_mask = SPEAR310_SMII1_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_SMII2,
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.status_mask = SPEAR310_SMII2_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_SMII3,
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.status_mask = SPEAR310_SMII3_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_WAKEUP_SMII0,
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.status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_WAKEUP_SMII1,
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.status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_WAKEUP_SMII2,
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.status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_WAKEUP_SMII3,
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.status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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},
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};
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2011-05-20 07:34:20 +00:00
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static struct spear_shirq shirq_ras1 = {
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2011-05-20 07:34:21 +00:00
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.irq = SPEAR3XX_IRQ_GEN_RAS_1,
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2010-05-03 08:24:30 +00:00
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.dev_config = shirq_ras1_config,
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.dev_count = ARRAY_SIZE(shirq_ras1_config),
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.regs = {
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.enb_reg = -1,
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2011-05-20 07:34:21 +00:00
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
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2010-05-03 08:24:30 +00:00
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.clear_reg = -1,
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},
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};
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2011-05-20 07:34:20 +00:00
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static struct shirq_dev_config shirq_ras2_config[] = {
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2010-05-03 08:24:30 +00:00
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{
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_UART1,
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.status_mask = SPEAR310_UART1_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_UART2,
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.status_mask = SPEAR310_UART2_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_UART3,
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.status_mask = SPEAR310_UART3_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_UART4,
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.status_mask = SPEAR310_UART4_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_UART5,
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.status_mask = SPEAR310_UART5_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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},
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};
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2011-05-20 07:34:20 +00:00
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static struct spear_shirq shirq_ras2 = {
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2011-05-20 07:34:21 +00:00
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.irq = SPEAR3XX_IRQ_GEN_RAS_2,
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2010-05-03 08:24:30 +00:00
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.dev_config = shirq_ras2_config,
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.dev_count = ARRAY_SIZE(shirq_ras2_config),
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.regs = {
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.enb_reg = -1,
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2011-05-20 07:34:21 +00:00
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
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2010-05-03 08:24:30 +00:00
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.clear_reg = -1,
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},
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};
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2011-05-20 07:34:20 +00:00
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static struct shirq_dev_config shirq_ras3_config[] = {
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2010-05-03 08:24:30 +00:00
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{
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_EMI,
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.status_mask = SPEAR310_EMI_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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},
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};
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2011-05-20 07:34:20 +00:00
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static struct spear_shirq shirq_ras3 = {
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2011-05-20 07:34:21 +00:00
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.irq = SPEAR3XX_IRQ_GEN_RAS_3,
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2010-05-03 08:24:30 +00:00
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.dev_config = shirq_ras3_config,
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.dev_count = ARRAY_SIZE(shirq_ras3_config),
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.regs = {
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.enb_reg = -1,
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2011-05-20 07:34:21 +00:00
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
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2010-05-03 08:24:30 +00:00
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.clear_reg = -1,
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},
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};
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2011-05-20 07:34:20 +00:00
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static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
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2010-05-03 08:24:30 +00:00
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{
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_TDM_HDLC,
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.status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_RS485_0,
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.status_mask = SPEAR310_RS485_0_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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}, {
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2011-05-20 07:34:21 +00:00
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.virq = SPEAR310_VIRQ_RS485_1,
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.status_mask = SPEAR310_RS485_1_IRQ_MASK,
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2010-05-03 08:24:30 +00:00
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},
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};
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2011-05-20 07:34:20 +00:00
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static struct spear_shirq shirq_intrcomm_ras = {
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2011-05-20 07:34:21 +00:00
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.irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
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2010-05-03 08:24:30 +00:00
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.dev_config = shirq_intrcomm_ras_config,
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.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
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.regs = {
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.enb_reg = -1,
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2011-05-20 07:34:21 +00:00
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
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2010-05-03 08:24:30 +00:00
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.clear_reg = -1,
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},
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};
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2012-03-26 04:59:23 +00:00
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/* DMAC platform data's slave info */
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struct pl08x_channel_data spear310_dma_info[] = {
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{
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.bus_id = "uart0_rx",
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.min_signal = 2,
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.max_signal = 2,
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.muxval = 0,
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.cctl = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart0_tx",
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.min_signal = 3,
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.max_signal = 3,
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.muxval = 0,
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.cctl = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ssp0_rx",
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.min_signal = 8,
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.max_signal = 8,
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.muxval = 0,
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.cctl = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ssp0_tx",
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.min_signal = 9,
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.max_signal = 9,
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.muxval = 0,
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.cctl = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "i2c_rx",
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.min_signal = 10,
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.max_signal = 10,
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.muxval = 0,
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.cctl = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "i2c_tx",
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.min_signal = 11,
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.max_signal = 11,
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.muxval = 0,
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.cctl = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "irda",
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.min_signal = 12,
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.max_signal = 12,
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.muxval = 0,
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.cctl = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "adc",
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.min_signal = 13,
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.max_signal = 13,
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.muxval = 0,
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.cctl = 0,
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.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "to_jpeg",
|
|
|
|
|
.min_signal = 14,
|
|
|
|
|
.max_signal = 14,
|
|
|
|
|
.muxval = 0,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "from_jpeg",
|
|
|
|
|
.min_signal = 15,
|
|
|
|
|
.max_signal = 15,
|
|
|
|
|
.muxval = 0,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "uart1_rx",
|
|
|
|
|
.min_signal = 0,
|
|
|
|
|
.max_signal = 0,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "uart1_tx",
|
|
|
|
|
.min_signal = 1,
|
|
|
|
|
.max_signal = 1,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "uart2_rx",
|
|
|
|
|
.min_signal = 2,
|
|
|
|
|
.max_signal = 2,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "uart2_tx",
|
|
|
|
|
.min_signal = 3,
|
|
|
|
|
.max_signal = 3,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "uart3_rx",
|
|
|
|
|
.min_signal = 4,
|
|
|
|
|
.max_signal = 4,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "uart3_tx",
|
|
|
|
|
.min_signal = 5,
|
|
|
|
|
.max_signal = 5,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "uart4_rx",
|
|
|
|
|
.min_signal = 6,
|
|
|
|
|
.max_signal = 6,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "uart4_tx",
|
|
|
|
|
.min_signal = 7,
|
|
|
|
|
.max_signal = 7,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "uart5_rx",
|
|
|
|
|
.min_signal = 8,
|
|
|
|
|
.max_signal = 8,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "uart5_tx",
|
|
|
|
|
.min_signal = 9,
|
|
|
|
|
.max_signal = 9,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "ras5_rx",
|
|
|
|
|
.min_signal = 10,
|
|
|
|
|
.max_signal = 10,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "ras5_tx",
|
|
|
|
|
.min_signal = 11,
|
|
|
|
|
.max_signal = 11,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "ras6_rx",
|
|
|
|
|
.min_signal = 12,
|
|
|
|
|
.max_signal = 12,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "ras6_tx",
|
|
|
|
|
.min_signal = 13,
|
|
|
|
|
.max_signal = 13,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "ras7_rx",
|
|
|
|
|
.min_signal = 14,
|
|
|
|
|
.max_signal = 14,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
}, {
|
|
|
|
|
.bus_id = "ras7_tx",
|
|
|
|
|
.min_signal = 15,
|
|
|
|
|
.max_signal = 15,
|
|
|
|
|
.muxval = 1,
|
|
|
|
|
.cctl = 0,
|
|
|
|
|
.periph_buses = PL08X_AHB1,
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2012-03-22 18:47:43 +00:00
|
|
|
/* uart devices plat data */
|
|
|
|
|
static struct amba_pl011_data spear310_uart_data[] = {
|
|
|
|
|
{
|
|
|
|
|
.dma_filter = pl08x_filter_id,
|
|
|
|
|
.dma_tx_param = "uart1_tx",
|
|
|
|
|
.dma_rx_param = "uart1_rx",
|
|
|
|
|
}, {
|
|
|
|
|
.dma_filter = pl08x_filter_id,
|
|
|
|
|
.dma_tx_param = "uart2_tx",
|
|
|
|
|
.dma_rx_param = "uart2_rx",
|
|
|
|
|
}, {
|
|
|
|
|
.dma_filter = pl08x_filter_id,
|
|
|
|
|
.dma_tx_param = "uart3_tx",
|
|
|
|
|
.dma_rx_param = "uart3_rx",
|
|
|
|
|
}, {
|
|
|
|
|
.dma_filter = pl08x_filter_id,
|
|
|
|
|
.dma_tx_param = "uart4_tx",
|
|
|
|
|
.dma_rx_param = "uart4_rx",
|
|
|
|
|
}, {
|
|
|
|
|
.dma_filter = pl08x_filter_id,
|
|
|
|
|
.dma_tx_param = "uart5_tx",
|
|
|
|
|
.dma_rx_param = "uart5_rx",
|
|
|
|
|
},
|
|
|
|
|
};
|
2011-03-07 04:57:05 +00:00
|
|
|
|
2012-03-22 18:47:43 +00:00
|
|
|
/* Add SPEAr310 auxdata to pass platform data */
|
|
|
|
|
static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
|
|
|
|
|
OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
|
|
|
|
|
&pl022_plat_data),
|
2012-03-26 04:59:23 +00:00
|
|
|
OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
|
|
|
|
|
&pl080_plat_data),
|
2012-03-22 18:47:43 +00:00
|
|
|
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
|
|
|
|
|
&spear310_uart_data[0]),
|
|
|
|
|
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
|
|
|
|
|
&spear310_uart_data[1]),
|
|
|
|
|
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
|
|
|
|
|
&spear310_uart_data[2]),
|
|
|
|
|
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
|
|
|
|
|
&spear310_uart_data[3]),
|
|
|
|
|
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
|
|
|
|
|
&spear310_uart_data[4]),
|
|
|
|
|
{}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void __init spear310_dt_init(void)
|
2010-04-01 11:30:58 +00:00
|
|
|
{
|
2010-05-03 08:24:30 +00:00
|
|
|
void __iomem *base;
|
2012-04-03 11:57:10 +00:00
|
|
|
int ret;
|
2010-05-03 08:24:30 +00:00
|
|
|
|
2012-03-26 04:59:23 +00:00
|
|
|
pl080_plat_data.slave_channels = spear310_dma_info;
|
|
|
|
|
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
|
|
|
|
|
|
2012-03-22 18:47:43 +00:00
|
|
|
of_platform_populate(NULL, of_default_bus_match_table,
|
|
|
|
|
spear310_auxdata_lookup, NULL);
|
2010-05-03 08:24:30 +00:00
|
|
|
|
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01 19:38:34 +00:00
|
|
|
/* shared irq registration */
|
2011-03-07 04:57:06 +00:00
|
|
|
base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
|
2010-05-03 08:24:30 +00:00
|
|
|
if (base) {
|
|
|
|
|
/* shirq 1 */
|
|
|
|
|
shirq_ras1.regs.base = base;
|
|
|
|
|
ret = spear_shirq_register(&shirq_ras1);
|
|
|
|
|
if (ret)
|
2012-03-26 05:09:43 +00:00
|
|
|
pr_err("Error registering Shared IRQ 1\n");
|
2010-05-03 08:24:30 +00:00
|
|
|
|
|
|
|
|
/* shirq 2 */
|
|
|
|
|
shirq_ras2.regs.base = base;
|
|
|
|
|
ret = spear_shirq_register(&shirq_ras2);
|
|
|
|
|
if (ret)
|
2012-03-26 05:09:43 +00:00
|
|
|
pr_err("Error registering Shared IRQ 2\n");
|
2010-05-03 08:24:30 +00:00
|
|
|
|
|
|
|
|
/* shirq 3 */
|
|
|
|
|
shirq_ras3.regs.base = base;
|
|
|
|
|
ret = spear_shirq_register(&shirq_ras3);
|
|
|
|
|
if (ret)
|
2012-03-26 05:09:43 +00:00
|
|
|
pr_err("Error registering Shared IRQ 3\n");
|
2010-05-03 08:24:30 +00:00
|
|
|
|
|
|
|
|
/* shirq 4 */
|
|
|
|
|
shirq_intrcomm_ras.regs.base = base;
|
|
|
|
|
ret = spear_shirq_register(&shirq_intrcomm_ras);
|
|
|
|
|
if (ret)
|
2012-03-26 05:09:43 +00:00
|
|
|
pr_err("Error registering Shared IRQ 4\n");
|
2010-05-03 08:24:30 +00:00
|
|
|
}
|
2010-04-01 11:31:29 +00:00
|
|
|
}
|
2012-03-22 18:47:43 +00:00
|
|
|
|
|
|
|
|
static const char * const spear310_dt_board_compat[] = {
|
|
|
|
|
"st,spear310",
|
|
|
|
|
"st,spear310-evb",
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void __init spear310_map_io(void)
|
|
|
|
|
{
|
|
|
|
|
spear3xx_map_io();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
|
|
|
|
|
.map_io = spear310_map_io,
|
|
|
|
|
.init_irq = spear3xx_dt_init_irq,
|
|
|
|
|
.handle_irq = vic_handle_irq,
|
|
|
|
|
.timer = &spear3xx_timer,
|
|
|
|
|
.init_machine = spear310_dt_init,
|
|
|
|
|
.restart = spear_restart,
|
|
|
|
|
.dt_compat = spear310_dt_board_compat,
|
|
|
|
|
MACHINE_END
|
