2012-06-13 17:01:28 +00:00
|
|
|
/*
|
|
|
|
* Device Tree support for Armada 370 and XP platforms.
|
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*
|
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|
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
|
|
|
|
#include <linux/init.h>
|
2013-05-11 01:08:09 +00:00
|
|
|
#include <linux/clk-provider.h>
|
2013-06-05 07:04:59 +00:00
|
|
|
#include <linux/of_address.h>
|
2012-06-13 17:01:28 +00:00
|
|
|
#include <linux/of_platform.h>
|
|
|
|
#include <linux/io.h>
|
2013-08-13 14:43:12 +00:00
|
|
|
#include <linux/clocksource.h>
|
2012-10-26 12:30:46 +00:00
|
|
|
#include <linux/dma-mapping.h>
|
2013-03-21 16:59:15 +00:00
|
|
|
#include <linux/mbus.h>
|
2014-02-24 20:54:49 +00:00
|
|
|
#include <linux/signal.h>
|
2014-01-07 15:26:01 +00:00
|
|
|
#include <linux/slab.h>
|
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 15:09:32 +00:00
|
|
|
#include <linux/irqchip.h>
|
2013-04-09 21:26:14 +00:00
|
|
|
#include <asm/hardware/cache-l2x0.h>
|
2012-06-13 17:01:28 +00:00
|
|
|
#include <asm/mach/arch.h>
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|
|
|
#include <asm/mach/map.h>
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|
|
|
#include <asm/mach/time.h>
|
2014-04-14 13:47:03 +00:00
|
|
|
#include <asm/smp_scu.h>
|
2012-09-02 19:57:33 +00:00
|
|
|
#include "armada-370-xp.h"
|
2012-06-13 17:01:28 +00:00
|
|
|
#include "common.h"
|
2012-11-14 21:51:08 +00:00
|
|
|
#include "coherency.h"
|
2014-01-07 15:26:01 +00:00
|
|
|
#include "mvebu-soc-id.h"
|
2012-06-13 17:01:28 +00:00
|
|
|
|
2014-04-14 13:47:03 +00:00
|
|
|
/*
|
|
|
|
* Enables the SCU when available. Obviously, this is only useful on
|
|
|
|
* Cortex-A based SOCs, not on PJ4B based ones.
|
|
|
|
*/
|
|
|
|
static void __init mvebu_scu_enable(void)
|
|
|
|
{
|
|
|
|
void __iomem *scu_base;
|
|
|
|
|
|
|
|
struct device_node *np =
|
|
|
|
of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
|
|
|
|
if (np) {
|
|
|
|
scu_base = of_iomap(np, 0);
|
|
|
|
scu_enable(scu_base);
|
|
|
|
of_node_put(np);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-02-17 14:23:24 +00:00
|
|
|
/*
|
|
|
|
* Early versions of Armada 375 SoC have a bug where the BootROM
|
|
|
|
* leaves an external data abort pending. The kernel is hit by this
|
|
|
|
* data abort as soon as it enters userspace, because it unmasks the
|
|
|
|
* data aborts at this moment. We register a custom abort handler
|
|
|
|
* below to ignore the first data abort to work around this
|
|
|
|
* problem.
|
|
|
|
*/
|
|
|
|
static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
|
|
|
|
struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
static int ignore_first;
|
|
|
|
|
|
|
|
if (!ignore_first && fsr == 0x1406) {
|
|
|
|
ignore_first = 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 15:09:32 +00:00
|
|
|
static void __init mvebu_init_irq(void)
|
2013-06-05 07:04:59 +00:00
|
|
|
{
|
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 15:09:32 +00:00
|
|
|
irqchip_init();
|
2014-04-14 13:47:03 +00:00
|
|
|
mvebu_scu_enable();
|
2013-06-05 07:04:59 +00:00
|
|
|
coherency_init();
|
2014-04-14 13:47:01 +00:00
|
|
|
BUG_ON(mvebu_mbus_dt_init(coherency_available()));
|
2014-06-12 15:09:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init external_abort_quirk(void)
|
|
|
|
{
|
|
|
|
u32 dev, rev;
|
2014-02-17 14:23:24 +00:00
|
|
|
|
2014-06-12 15:09:31 +00:00
|
|
|
if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
|
|
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|
return;
|
|
|
|
|
|
|
|
hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
|
|
|
|
"imprecise external abort");
|
2012-10-26 12:30:46 +00:00
|
|
|
}
|
|
|
|
|
2014-01-07 15:26:01 +00:00
|
|
|
static void __init i2c_quirk(void)
|
|
|
|
{
|
|
|
|
struct device_node *np;
|
|
|
|
u32 dev, rev;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only revisons more recent than A0 support the offload
|
|
|
|
* mechanism. We can exit only if we are sure that we can
|
|
|
|
* get the SoC revision and it is more recent than A0.
|
|
|
|
*/
|
2014-04-19 16:32:50 +00:00
|
|
|
if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV)
|
2014-01-07 15:26:01 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
|
|
|
|
struct property *new_compat;
|
|
|
|
|
|
|
|
new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
|
|
|
|
|
|
|
|
new_compat->name = kstrdup("compatible", GFP_KERNEL);
|
|
|
|
new_compat->length = sizeof("marvell,mv78230-a0-i2c");
|
|
|
|
new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
|
|
|
of_update_property(np, new_compat);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-04-24 20:23:22 +00:00
|
|
|
#define A375_Z1_THERMAL_FIXUP_OFFSET 0xc
|
|
|
|
|
|
|
|
static void __init thermal_quirk(void)
|
|
|
|
{
|
|
|
|
struct device_node *np;
|
|
|
|
u32 dev, rev;
|
2014-06-10 18:34:43 +00:00
|
|
|
int res;
|
2014-04-24 20:23:22 +00:00
|
|
|
|
2014-06-10 18:34:43 +00:00
|
|
|
/*
|
|
|
|
* The early SoC Z1 revision needs a quirk to be applied in order
|
|
|
|
* for the thermal controller to work properly. This quirk breaks
|
|
|
|
* the thermal support if applied on a SoC that doesn't need it,
|
|
|
|
* so we enforce the SoC revision to be known.
|
|
|
|
*/
|
|
|
|
res = mvebu_get_soc_id(&dev, &rev);
|
|
|
|
if (res < 0 || (res == 0 && rev > ARMADA_375_Z1_REV))
|
2014-04-24 20:23:22 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
for_each_compatible_node(np, NULL, "marvell,armada375-thermal") {
|
|
|
|
struct property *prop;
|
|
|
|
__be32 newval, *newprop, *oldprop;
|
|
|
|
int len;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The register offset is at a wrong location. This quirk
|
|
|
|
* creates a new reg property as a clone of the previous
|
|
|
|
* one and corrects the offset.
|
|
|
|
*/
|
|
|
|
oldprop = (__be32 *)of_get_property(np, "reg", &len);
|
|
|
|
if (!oldprop)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Create a duplicate of the 'reg' property */
|
|
|
|
prop = kzalloc(sizeof(*prop), GFP_KERNEL);
|
|
|
|
prop->length = len;
|
|
|
|
prop->name = kstrdup("reg", GFP_KERNEL);
|
|
|
|
prop->value = kzalloc(len, GFP_KERNEL);
|
|
|
|
memcpy(prop->value, oldprop, len);
|
|
|
|
|
|
|
|
/* Fixup the register offset of the second entry */
|
|
|
|
oldprop += 2;
|
|
|
|
newprop = (__be32 *)prop->value + 2;
|
|
|
|
newval = cpu_to_be32(be32_to_cpu(*oldprop) -
|
|
|
|
A375_Z1_THERMAL_FIXUP_OFFSET);
|
|
|
|
*newprop = newval;
|
|
|
|
of_update_property(np, prop);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The thermal controller needs some quirk too, so let's change
|
2014-06-10 18:34:43 +00:00
|
|
|
* the compatible string to reflect this and allow the driver
|
|
|
|
* the take the necessary action.
|
2014-04-24 20:23:22 +00:00
|
|
|
*/
|
|
|
|
prop = kzalloc(sizeof(*prop), GFP_KERNEL);
|
|
|
|
prop->name = kstrdup("compatible", GFP_KERNEL);
|
|
|
|
prop->length = sizeof("marvell,armada375-z1-thermal");
|
|
|
|
prop->value = kstrdup("marvell,armada375-z1-thermal",
|
|
|
|
GFP_KERNEL);
|
|
|
|
of_update_property(np, prop);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-02-17 14:23:19 +00:00
|
|
|
static void __init mvebu_dt_init(void)
|
2012-06-13 17:01:28 +00:00
|
|
|
{
|
2014-01-07 15:26:01 +00:00
|
|
|
if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
|
|
|
|
i2c_quirk();
|
2014-06-12 15:09:31 +00:00
|
|
|
if (of_machine_is_compatible("marvell,a375-db")) {
|
|
|
|
external_abort_quirk();
|
2014-04-24 20:23:22 +00:00
|
|
|
thermal_quirk();
|
2014-06-12 15:09:31 +00:00
|
|
|
}
|
2014-04-24 20:23:22 +00:00
|
|
|
|
2012-06-13 17:01:28 +00:00
|
|
|
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
|
|
|
}
|
|
|
|
|
2012-11-09 15:26:26 +00:00
|
|
|
static const char * const armada_370_xp_dt_compat[] = {
|
|
|
|
"marvell,armada-370-xp",
|
2012-06-13 17:01:28 +00:00
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
2014-02-17 14:23:20 +00:00
|
|
|
DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
|
2014-04-28 14:44:47 +00:00
|
|
|
.l2c_aux_val = 0,
|
|
|
|
.l2c_aux_mask = ~0,
|
2012-11-14 21:51:08 +00:00
|
|
|
.smp = smp_ops(armada_xp_smp_ops),
|
2014-02-17 14:23:19 +00:00
|
|
|
.init_machine = mvebu_dt_init,
|
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 15:09:32 +00:00
|
|
|
.init_irq = mvebu_init_irq,
|
2012-06-13 17:01:28 +00:00
|
|
|
.restart = mvebu_restart,
|
2012-11-09 15:26:26 +00:00
|
|
|
.dt_compat = armada_370_xp_dt_compat,
|
2012-06-13 17:01:28 +00:00
|
|
|
MACHINE_END
|
2014-02-17 14:23:23 +00:00
|
|
|
|
|
|
|
static const char * const armada_375_dt_compat[] = {
|
|
|
|
"marvell,armada375",
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
|
2014-04-28 14:44:47 +00:00
|
|
|
.l2c_aux_val = 0,
|
|
|
|
.l2c_aux_mask = ~0,
|
ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 15:09:32 +00:00
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.init_irq = mvebu_init_irq,
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2014-04-24 20:23:22 +00:00
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.init_machine = mvebu_dt_init,
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2014-02-17 14:23:23 +00:00
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.restart = mvebu_restart,
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.dt_compat = armada_375_dt_compat,
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MACHINE_END
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2014-02-17 14:23:27 +00:00
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static const char * const armada_38x_dt_compat[] = {
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"marvell,armada380",
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"marvell,armada385",
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NULL,
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};
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DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
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2014-04-28 14:44:47 +00:00
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.
However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).
In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.
In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-12 15:09:32 +00:00
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.init_irq = mvebu_init_irq,
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2014-02-17 14:23:27 +00:00
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.restart = mvebu_restart,
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.dt_compat = armada_38x_dt_compat,
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MACHINE_END
|