License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2011-09-19 17:45:05 +00:00
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#ifndef __POWERNV_PCI_H
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#define __POWERNV_PCI_H
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2017-03-30 10:19:25 +00:00
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#include <linux/compiler.h> /* for __printf */
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2016-07-13 21:17:00 +00:00
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#include <linux/iommu.h>
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#include <asm/iommu.h>
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#include <asm/msi_bitmap.h>
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2011-09-19 17:45:05 +00:00
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struct pci_dn;
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enum pnv_phb_type {
|
2021-03-26 06:13:11 +00:00
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PNV_PHB_IODA1,
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PNV_PHB_IODA2,
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PNV_PHB_NPU_OCAPI,
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2011-09-19 17:45:05 +00:00
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};
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2011-11-29 18:22:53 +00:00
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/* Precise PHB model for error management */
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enum pnv_phb_model {
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PNV_PHB_MODEL_UNKNOWN,
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PNV_PHB_MODEL_P7IOC,
|
2013-04-25 19:20:57 +00:00
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PNV_PHB_MODEL_PHB3,
|
2011-11-29 18:22:53 +00:00
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};
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2013-09-06 01:00:03 +00:00
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#define PNV_PCI_DIAG_BUF_SIZE 8192
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2012-08-20 03:49:15 +00:00
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#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
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#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
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#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
|
2014-07-21 04:42:30 +00:00
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#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
|
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#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
|
2015-03-25 08:23:57 +00:00
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#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
|
2011-11-29 18:22:53 +00:00
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2020-04-14 23:35:02 +00:00
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/*
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* A brief note on PNV_IODA_PE_BUS_ALL
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*
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* This is needed because of the behaviour of PCIe-to-PCI bridges. The PHB uses
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* the Requester ID field of the PCIe request header to determine the device
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* (and PE) that initiated a DMA. In legacy PCI individual memory read/write
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* requests aren't tagged with the RID. To work around this the PCIe-to-PCI
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* bridge will use (secondary_bus_no << 8) | 0x00 as the RID on the PCIe side.
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*
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* PCIe-to-X bridges have a similar issue even though PCI-X requests also have
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* a RID in the transaction header. The PCIe-to-X bridge is permitted to "take
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* ownership" of a transaction by a PCI-X device when forwarding it to the PCIe
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* side of the bridge.
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*
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* To work around these problems we use the BUS_ALL flag since every subordinate
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* bus of the bridge should go into the same PE.
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*/
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|
2017-06-14 04:19:58 +00:00
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/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
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#define PNV_IODA_STOPPED_STATE 0x8000000000000000
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|
2011-11-15 17:29:08 +00:00
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/* Data associated with a PE, including IOMMU tracking etc.. */
|
2013-04-25 19:21:00 +00:00
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struct pnv_phb;
|
2011-11-15 17:29:08 +00:00
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struct pnv_ioda_pe {
|
2012-08-20 03:49:15 +00:00
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unsigned long flags;
|
2013-04-25 19:21:00 +00:00
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struct pnv_phb *phb;
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2016-05-20 06:41:35 +00:00
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int device_count;
|
2012-08-20 03:49:15 +00:00
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2011-11-15 17:29:08 +00:00
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/* A PE can be associated with a single device or an
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* entire bus (& children). In the former case, pdev
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* is populated, in the later case, pbus is.
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*/
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2015-03-25 08:23:57 +00:00
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#ifdef CONFIG_PCI_IOV
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struct pci_dev *parent_dev;
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#endif
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2011-11-15 17:29:08 +00:00
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struct pci_dev *pdev;
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struct pci_bus *pbus;
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/* Effective RID (device RID for a device PE and base bus
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* RID with devfn 0 for a bus PE)
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*/
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unsigned int rid;
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/* PE number */
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unsigned int pe_number;
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/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
|
2015-06-05 06:35:08 +00:00
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struct iommu_table_group table_group;
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2011-11-15 17:29:08 +00:00
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2014-02-11 00:32:38 +00:00
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/* 64-bit TCE bypass region */
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bool tce_bypass_enabled;
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uint64_t tce_bypass_base;
|
2011-11-15 17:29:08 +00:00
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2020-07-22 06:57:02 +00:00
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/*
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* Used to track whether we've done DMA setup for this PE or not. We
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* want to defer allocating TCE tables, etc until we've added a
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* non-bridge device to the PE.
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*/
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bool dma_setup_done;
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2020-07-26 00:38:09 +00:00
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/* MSIs. MVE index is identical for 32 and 64 bit MSI
|
2011-11-15 17:29:08 +00:00
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* and -1 if not supported. (It's actually identical to the
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* PE number)
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*/
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int mve_number;
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|
2014-07-21 04:42:30 +00:00
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/* PEs in compound case */
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struct pnv_ioda_pe *master;
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struct list_head slaves;
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2011-11-15 17:29:08 +00:00
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/* Link in list of PE#s */
|
2012-08-20 03:49:15 +00:00
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struct list_head list;
|
2011-11-15 17:29:08 +00:00
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};
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|
2014-04-24 08:00:09 +00:00
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#define PNV_PHB_FLAG_EEH (1 << 0)
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|
2011-09-19 17:45:05 +00:00
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struct pnv_phb {
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struct pci_controller *hose;
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enum pnv_phb_type type;
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2011-11-29 18:22:53 +00:00
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enum pnv_phb_model model;
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2013-06-20 05:21:06 +00:00
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u64 hub_id;
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2011-09-19 17:45:05 +00:00
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u64 opal_id;
|
2014-04-24 08:00:09 +00:00
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int flags;
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2011-09-19 17:45:05 +00:00
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void __iomem *regs;
|
2016-07-08 06:37:14 +00:00
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u64 regs_phys;
|
2011-09-19 17:45:05 +00:00
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spinlock_t lock;
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|
2013-06-20 10:13:25 +00:00
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#ifdef CONFIG_DEBUG_FS
|
2014-04-24 08:00:18 +00:00
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int has_dbgfs;
|
2013-06-20 10:13:25 +00:00
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struct dentry *dbgfs;
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#endif
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2011-09-19 17:45:06 +00:00
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unsigned int msi_base;
|
2013-03-05 21:12:37 +00:00
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struct msi_bitmap msi_bmp;
|
2014-07-21 04:42:30 +00:00
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int (*init_m64)(struct pnv_phb *phb);
|
2014-07-21 04:42:33 +00:00
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int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
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void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
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int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
|
2011-09-19 17:45:05 +00:00
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2016-02-08 04:08:20 +00:00
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struct {
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/* Global bridge info */
|
2016-05-03 05:41:24 +00:00
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unsigned int total_pe_num;
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unsigned int reserved_pe_idx;
|
2016-05-20 06:41:32 +00:00
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unsigned int root_pe_idx;
|
2016-02-08 04:08:20 +00:00
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/* 32-bit MMIO window */
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unsigned int m32_size;
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unsigned int m32_segsize;
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unsigned int m32_pci_base;
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/* 64-bit MMIO window */
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unsigned int m64_bar_idx;
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unsigned long m64_size;
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unsigned long m64_segsize;
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unsigned long m64_base;
|
2020-07-22 06:57:07 +00:00
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#define MAX_M64_BARS 64
|
2016-02-08 04:08:20 +00:00
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unsigned long m64_bar_alloc;
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/* IO ports */
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unsigned int io_size;
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unsigned int io_segsize;
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unsigned int io_pci_base;
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|
2016-05-03 05:41:23 +00:00
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/* PE allocation */
|
2016-02-08 04:08:20 +00:00
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struct mutex pe_alloc_mutex;
|
2016-05-03 05:41:23 +00:00
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unsigned long *pe_alloc;
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struct pnv_ioda_pe *pe_array;
|
2016-02-08 04:08:20 +00:00
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/* M32 & IO segment maps */
|
2016-05-03 05:41:29 +00:00
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unsigned int *m64_segmap;
|
2016-02-08 04:08:20 +00:00
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unsigned int *m32_segmap;
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unsigned int *io_segmap;
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|
2016-05-05 02:04:16 +00:00
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/* DMA32 segment maps - IODA1 only */
|
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unsigned int dma32_count;
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unsigned int *dma32_segmap;
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|
2016-02-08 04:08:20 +00:00
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/* IRQ chip */
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int irq_chip_init;
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struct irq_chip irq_chip;
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/* Sorted list of used PE's based
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* on the sequence of creation
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*/
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struct list_head pe_list;
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struct mutex pe_list_mutex;
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|
2016-05-20 06:41:29 +00:00
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/* Reverse map of PEs, indexed by {bus, devfn} */
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unsigned int pe_rmap[0x10000];
|
2016-02-08 04:08:20 +00:00
|
|
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} ioda;
|
2011-11-29 18:22:53 +00:00
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|
2017-06-14 04:19:59 +00:00
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/* PHB and hub diagnostics */
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unsigned int diag_data_size;
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u8 *diag_data;
|
2011-09-19 17:45:05 +00:00
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};
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|
2020-07-22 06:57:04 +00:00
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/* IODA PE management */
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static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
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{
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/*
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* WARNING: We cannot rely on the resource flags. The Linux PCI
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* allocation code sometimes decides to put a 64-bit prefetchable
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* BAR in the 32-bit window, so we have to compare the addresses.
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*
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* For simplicity we only test resource start.
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*/
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return (r->start >= phb->ioda.m64_base &&
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r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
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}
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static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
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{
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unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
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return (resource_flags & flags) == flags;
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}
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int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
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int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
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void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe);
|
|
|
|
|
void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe);
|
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|
2020-07-22 06:57:09 +00:00
|
|
|
struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count);
|
2020-07-22 06:57:04 +00:00
|
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|
void pnv_ioda_free_pe(struct pnv_ioda_pe *pe);
|
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|
|
#ifdef CONFIG_PCI_IOV
|
|
|
|
|
/*
|
|
|
|
|
* For SR-IOV we want to put each VF's MMIO resource in to a separate PE.
|
|
|
|
|
* This requires a bit of acrobatics with the MMIO -> PE configuration
|
|
|
|
|
* and this structure is used to keep track of it all.
|
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|
|
|
*/
|
|
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|
|
struct pnv_iov_data {
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|
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|
/* number of VFs enabled */
|
|
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|
|
u16 num_vfs;
|
2020-07-22 06:57:10 +00:00
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|
2020-07-22 06:57:11 +00:00
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|
|
/* pointer to the array of VF PEs. num_vfs long*/
|
2020-07-22 06:57:10 +00:00
|
|
|
struct pnv_ioda_pe *vf_pe_arr;
|
2020-07-22 06:57:04 +00:00
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|
2020-07-22 06:57:14 +00:00
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|
/* Did we map the VF BAR with single-PE IODA BARs? */
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|
bool m64_single_mode[PCI_SRIOV_NUM_BARS];
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|
/*
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* True if we're using any segmented windows. In that case we need
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|
* shift the start of the IOV resource the segment corresponding to
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|
* the allocated PE.
|
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|
*/
|
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|
bool need_shift;
|
2020-07-22 06:57:04 +00:00
|
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|
2020-07-22 06:57:07 +00:00
|
|
|
/*
|
|
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|
* Bit mask used to track which m64 windows are used to map the
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|
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|
* SR-IOV BARs for this device.
|
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|
|
*/
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|
DECLARE_BITMAP(used_m64_bar_mask, MAX_M64_BARS);
|
2020-07-22 06:57:04 +00:00
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|
|
/*
|
|
|
|
|
* If we map the SR-IOV BARs with a segmented window then
|
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|
|
* parts of that window will be "claimed" by other PEs.
|
|
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|
*
|
|
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|
* "holes" here is used to reserve the leading portion
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|
* of the window that is used by other (non VF) PEs.
|
|
|
|
|
*/
|
|
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|
|
struct resource holes[PCI_SRIOV_NUM_BARS];
|
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|
|
};
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|
static inline struct pnv_iov_data *pnv_iov_get(struct pci_dev *pdev)
|
|
|
|
|
{
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|
|
return pdev->dev.archdata.iov_data;
|
|
|
|
|
}
|
|
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|
|
void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev);
|
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|
|
resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, int resno);
|
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|
|
int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
|
|
|
|
|
int pnv_pcibios_sriov_disable(struct pci_dev *pdev);
|
|
|
|
|
#endif /* CONFIG_PCI_IOV */
|
|
|
|
|
|
2011-09-19 17:45:05 +00:00
|
|
|
extern struct pci_ops pnv_pci_ops;
|
|
|
|
|
|
2013-11-22 08:28:45 +00:00
|
|
|
void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
|
|
|
|
|
unsigned char *log_buff);
|
2015-03-17 05:15:03 +00:00
|
|
|
int pnv_pci_cfg_read(struct pci_dn *pdn,
|
2013-06-27 05:46:48 +00:00
|
|
|
int where, int size, u32 *val);
|
2015-03-17 05:15:03 +00:00
|
|
|
int pnv_pci_cfg_write(struct pci_dn *pdn,
|
2013-06-27 05:46:48 +00:00
|
|
|
int where, int size, u32 val);
|
2015-06-05 06:35:09 +00:00
|
|
|
extern struct iommu_table *pnv_pci_table_alloc(int nid);
|
|
|
|
|
|
2011-11-15 17:29:08 +00:00
|
|
|
extern void pnv_pci_init_ioda_hub(struct device_node *np);
|
2013-04-25 19:20:57 +00:00
|
|
|
extern void pnv_pci_init_ioda2_phb(struct device_node *np);
|
2018-01-23 11:31:36 +00:00
|
|
|
extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
|
2014-04-24 08:00:24 +00:00
|
|
|
extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
|
2015-02-16 03:45:47 +00:00
|
|
|
extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
|
2013-05-10 06:59:18 +00:00
|
|
|
|
2020-04-17 07:35:05 +00:00
|
|
|
extern struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn);
|
2016-07-13 21:17:00 +00:00
|
|
|
extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
|
|
|
|
|
extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
|
2018-12-19 08:52:26 +00:00
|
|
|
extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
|
|
|
|
|
__u64 window_size, __u32 levels);
|
2017-09-07 06:35:44 +00:00
|
|
|
extern int pnv_eeh_post_init(void);
|
2015-04-28 05:12:05 +00:00
|
|
|
|
2017-03-30 10:19:25 +00:00
|
|
|
__printf(3, 4)
|
2016-04-29 08:55:21 +00:00
|
|
|
extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
|
|
|
|
|
const char *fmt, ...);
|
|
|
|
|
#define pe_err(pe, fmt, ...) \
|
|
|
|
|
pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
|
|
|
|
|
#define pe_warn(pe, fmt, ...) \
|
|
|
|
|
pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
|
|
|
|
|
#define pe_info(pe, fmt, ...) \
|
|
|
|
|
pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
|
|
|
|
|
|
2018-07-04 06:13:45 +00:00
|
|
|
/* pci-ioda-tce.c */
|
powerpc/powernv/ioda2: Allocate TCE table levels on demand for default DMA window
We allocate only the first level of multilevel TCE tables for KVM
already (alloc_userspace_copy==true), and the rest is allocated on demand.
This is not enabled though for bare metal.
This removes the KVM limitation (implicit, via the alloc_userspace_copy
parameter) and always allocates just the first level. The on-demand
allocation of missing levels is already implemented.
As from now on DMA map might happen with disabled interrupts, this
allocates TCEs with GFP_ATOMIC; otherwise lockdep reports errors 1].
In practice just a single page is allocated there so chances for failure
are quite low.
To save time when creating a new clean table, this skips non-allocated
indirect TCE entries in pnv_tce_free just like we already do in
the VFIO IOMMU TCE driver.
This changes the default level number from 1 to 2 to reduce the amount
of memory required for the default 32bit DMA window at the boot time.
The default window size is up to 2GB which requires 4MB of TCEs which is
unlikely to be used entirely or at all as most devices these days are
64bit capable so by switching to 2 levels by default we save 4032KB of
RAM per a device.
While at this, add __GFP_NOWARN to alloc_pages_node() as the userspace
can trigger this path via VFIO, see the failure and try creating a table
again with different parameters which might succeed.
[1]:
===
BUG: sleeping function called from invalid context at mm/page_alloc.c:4596
in_atomic(): 1, irqs_disabled(): 1, pid: 1038, name: scsi_eh_1
2 locks held by scsi_eh_1/1038:
#0: 000000005efd659a (&host->eh_mutex){+.+.}, at: ata_eh_acquire+0x34/0x80
#1: 0000000006cf56a6 (&(&host->lock)->rlock){....}, at: ata_exec_internal_sg+0xb0/0x5c0
irq event stamp: 500
hardirqs last enabled at (499): [<c000000000cb8a74>] _raw_spin_unlock_irqrestore+0x94/0xd0
hardirqs last disabled at (500): [<c000000000cb85c4>] _raw_spin_lock_irqsave+0x44/0x120
softirqs last enabled at (0): [<c000000000101120>] copy_process.isra.4.part.5+0x640/0x1a80
softirqs last disabled at (0): [<0000000000000000>] 0x0
CPU: 73 PID: 1038 Comm: scsi_eh_1 Not tainted 5.2.0-rc6-le_nv2_aikATfstn1-p1 #634
Call Trace:
[c000003d064cef50] [c000000000c8e6c4] dump_stack+0xe8/0x164 (unreliable)
[c000003d064cefa0] [c00000000014ed78] ___might_sleep+0x2f8/0x310
[c000003d064cf020] [c0000000003ca084] __alloc_pages_nodemask+0x2a4/0x1560
[c000003d064cf220] [c0000000000c2530] pnv_alloc_tce_level.isra.0+0x90/0x130
[c000003d064cf290] [c0000000000c2888] pnv_tce+0x128/0x3b0
[c000003d064cf360] [c0000000000c2c00] pnv_tce_build+0xb0/0xf0
[c000003d064cf3c0] [c0000000000bbd9c] pnv_ioda2_tce_build+0x3c/0xb0
[c000003d064cf400] [c00000000004cfe0] ppc_iommu_map_sg+0x210/0x550
[c000003d064cf510] [c00000000004b7a4] dma_iommu_map_sg+0x74/0xb0
[c000003d064cf530] [c000000000863944] ata_qc_issue+0x134/0x470
[c000003d064cf5b0] [c000000000863ec4] ata_exec_internal_sg+0x244/0x5c0
[c000003d064cf700] [c0000000008642d0] ata_exec_internal+0x90/0xe0
[c000003d064cf780] [c0000000008650ac] ata_dev_read_id+0x2ec/0x640
[c000003d064cf8d0] [c000000000878e28] ata_eh_recover+0x948/0x16d0
[c000003d064cfa10] [c00000000087d760] sata_pmp_error_handler+0x480/0xbf0
[c000003d064cfbc0] [c000000000884624] ahci_error_handler+0x74/0xe0
[c000003d064cfbf0] [c000000000879fa8] ata_scsi_port_error_handler+0x2d8/0x7c0
[c000003d064cfca0] [c00000000087a544] ata_scsi_error+0xb4/0x100
[c000003d064cfd00] [c000000000802450] scsi_error_handler+0x120/0x510
[c000003d064cfdb0] [c000000000140c48] kthread+0x1b8/0x1c0
[c000003d064cfe20] [c00000000000bd8c] ret_from_kernel_thread+0x5c/0x70
ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
irq event stamp: 2305
========================================================
hardirqs last enabled at (2305): [<c00000000000e4c8>] fast_exc_return_irq+0x28/0x34
hardirqs last disabled at (2303): [<c000000000cb9fd0>] __do_softirq+0x4a0/0x654
WARNING: possible irq lock inversion dependency detected
5.2.0-rc6-le_nv2_aikATfstn1-p1 #634 Tainted: G W
softirqs last enabled at (2304): [<c000000000cba054>] __do_softirq+0x524/0x654
softirqs last disabled at (2297): [<c00000000010f278>] irq_exit+0x128/0x180
--------------------------------------------------------
swapper/0/0 just changed the state of lock:
0000000006cf56a6 (&(&host->lock)->rlock){-...}, at: ahci_single_level_irq_intr+0xac/0x120
but this lock took another, HARDIRQ-unsafe lock in the past:
(fs_reclaim){+.+.}
and interrupts could create inverse lock ordering between them.
other info that might help us debug this:
Possible interrupt unsafe locking scenario:
CPU0 CPU1
---- ----
lock(fs_reclaim);
local_irq_disable();
lock(&(&host->lock)->rlock);
lock(fs_reclaim);
<Interrupt>
lock(&(&host->lock)->rlock);
*** DEADLOCK ***
no locks held by swapper/0/0.
the shortest dependencies between 2nd lock and 1st lock:
-> (fs_reclaim){+.+.} ops: 167579 {
HARDIRQ-ON-W at:
lock_acquire+0xf8/0x2a0
fs_reclaim_acquire.part.23+0x44/0x60
kmem_cache_alloc_node_trace+0x80/0x590
alloc_desc+0x64/0x270
__irq_alloc_descs+0x2e4/0x3a0
irq_domain_alloc_descs+0xb0/0x150
irq_create_mapping+0x168/0x2c0
xics_smp_probe+0x2c/0x98
pnv_smp_probe+0x40/0x9c
smp_prepare_cpus+0x524/0x6c4
kernel_init_freeable+0x1b4/0x650
kernel_init+0x2c/0x148
ret_from_kernel_thread+0x5c/0x70
SOFTIRQ-ON-W at:
lock_acquire+0xf8/0x2a0
fs_reclaim_acquire.part.23+0x44/0x60
kmem_cache_alloc_node_trace+0x80/0x590
alloc_desc+0x64/0x270
__irq_alloc_descs+0x2e4/0x3a0
irq_domain_alloc_descs+0xb0/0x150
irq_create_mapping+0x168/0x2c0
xics_smp_probe+0x2c/0x98
pnv_smp_probe+0x40/0x9c
smp_prepare_cpus+0x524/0x6c4
kernel_init_freeable+0x1b4/0x650
kernel_init+0x2c/0x148
ret_from_kernel_thread+0x5c/0x70
INITIAL USE at:
lock_acquire+0xf8/0x2a0
fs_reclaim_acquire.part.23+0x44/0x60
kmem_cache_alloc_node_trace+0x80/0x590
alloc_desc+0x64/0x270
__irq_alloc_descs+0x2e4/0x3a0
irq_domain_alloc_descs+0xb0/0x150
irq_create_mapping+0x168/0x2c0
xics_smp_probe+0x2c/0x98
pnv_smp_probe+0x40/0x9c
smp_prepare_cpus+0x524/0x6c4
kernel_init_freeable+0x1b4/0x650
kernel_init+0x2c/0x148
ret_from_kernel_thread+0x5c/0x70
}
===
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190718051139.74787-4-aik@ozlabs.ru
2019-07-18 05:11:38 +00:00
|
|
|
#define POWERNV_IOMMU_DEFAULT_LEVELS 2
|
2018-07-04 06:13:45 +00:00
|
|
|
#define POWERNV_IOMMU_MAX_LEVELS 5
|
|
|
|
|
|
|
|
|
|
extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
|
|
|
|
|
unsigned long uaddr, enum dma_data_direction direction,
|
|
|
|
|
unsigned long attrs);
|
|
|
|
|
extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
|
|
|
|
|
extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
|
2022-05-06 05:37:55 +00:00
|
|
|
unsigned long *hpa, enum dma_data_direction *direction);
|
2018-07-04 06:13:49 +00:00
|
|
|
extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index,
|
|
|
|
|
bool alloc);
|
2018-07-04 06:13:45 +00:00
|
|
|
extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
|
|
|
|
|
|
|
|
|
|
extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
|
|
|
|
|
__u32 page_shift, __u64 window_size, __u32 levels,
|
2018-07-04 06:13:47 +00:00
|
|
|
bool alloc_userspace_copy, struct iommu_table *tbl);
|
2018-07-04 06:13:45 +00:00
|
|
|
extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
|
|
|
|
|
|
|
|
|
|
extern long pnv_pci_link_table_and_group(int node, int num,
|
|
|
|
|
struct iommu_table *tbl,
|
|
|
|
|
struct iommu_table_group *table_group);
|
|
|
|
|
extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
|
|
|
|
|
struct iommu_table_group *table_group);
|
|
|
|
|
extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
|
|
|
|
|
void *tce_mem, u64 tce_size,
|
|
|
|
|
u64 dma_offset, unsigned int page_shift);
|
|
|
|
|
|
2020-04-06 03:07:44 +00:00
|
|
|
extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
|
|
|
|
|
|
2020-07-22 06:57:00 +00:00
|
|
|
static inline struct pnv_phb *pci_bus_to_pnvhb(struct pci_bus *bus)
|
|
|
|
|
{
|
|
|
|
|
struct pci_controller *hose = bus->sysdata;
|
|
|
|
|
|
|
|
|
|
if (hose)
|
|
|
|
|
return hose->private_data;
|
|
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2011-09-19 17:45:05 +00:00
|
|
|
#endif /* __POWERNV_PCI_H */
|
