License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2013-02-13 16:21:35 +00:00
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/*
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* Transactional memory support routines to reclaim and recheckpoint
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* transactional process state.
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*
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* Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
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*/
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#include <asm/asm-offsets.h>
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#include <asm/ppc_asm.h>
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#include <asm/ppc-opcode.h>
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#include <asm/ptrace.h>
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#include <asm/reg.h>
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2014-03-28 05:40:34 +00:00
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#include <asm/bug.h>
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2018-05-23 07:01:46 +00:00
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#include <asm/export.h>
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2013-02-13 16:21:35 +00:00
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#ifdef CONFIG_VSX
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2013-09-10 10:20:42 +00:00
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/* See fpu.S, this is borrowed from there */
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#define __SAVE_32FPRS_VSRS(n,c,base) \
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2013-02-13 16:21:35 +00:00
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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2013-09-10 10:20:42 +00:00
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SAVE_32FPRS(n,base); \
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2013-02-13 16:21:35 +00:00
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b 3f; \
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2013-09-10 10:20:42 +00:00
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2: SAVE_32VSRS(n,c,base); \
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2013-02-13 16:21:35 +00:00
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3:
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#define __REST_32FPRS_VSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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REST_32FPRS(n,base); \
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b 3f; \
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2: REST_32VSRS(n,c,base); \
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3:
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#else
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2013-09-10 10:20:42 +00:00
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#define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
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#define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
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2013-02-13 16:21:35 +00:00
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#endif
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2013-09-10 10:20:42 +00:00
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#define SAVE_32FPRS_VSRS(n,c,base) \
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__SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
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2013-02-13 16:21:35 +00:00
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#define REST_32FPRS_VSRS(n,c,base) \
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__REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
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/* Stack frame offsets for local variables. */
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#define TM_FRAME_L0 TM_FRAME_SIZE-16
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#define TM_FRAME_L1 TM_FRAME_SIZE-8
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/* In order to access the TM SPRs, TM must be enabled. So, do so: */
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_GLOBAL(tm_enable)
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mfmsr r4
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li r3, MSR_TM >> 32
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sldi r3, r3, 32
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and. r0, r4, r3
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bne 1f
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or r4, r4, r3
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mtmsrd r4
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1: blr
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2018-05-23 07:01:46 +00:00
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EXPORT_SYMBOL_GPL(tm_enable);
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_GLOBAL(tm_disable)
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mfmsr r4
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li r3, MSR_TM >> 32
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sldi r3, r3, 32
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andc r4, r4, r3
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mtmsrd r4
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blr
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EXPORT_SYMBOL_GPL(tm_disable);
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2013-02-13 16:21:35 +00:00
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_GLOBAL(tm_save_sprs)
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mfspr r0, SPRN_TFHAR
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std r0, THREAD_TM_TFHAR(r3)
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mfspr r0, SPRN_TEXASR
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std r0, THREAD_TM_TEXASR(r3)
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mfspr r0, SPRN_TFIAR
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std r0, THREAD_TM_TFIAR(r3)
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blr
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_GLOBAL(tm_restore_sprs)
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ld r0, THREAD_TM_TFHAR(r3)
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mtspr SPRN_TFHAR, r0
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ld r0, THREAD_TM_TEXASR(r3)
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mtspr SPRN_TEXASR, r0
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ld r0, THREAD_TM_TFIAR(r3)
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mtspr SPRN_TFIAR, r0
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blr
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/* Passed an 8-bit failure cause as first argument. */
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_GLOBAL(tm_abort)
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TABORT(R3)
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blr
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2018-05-23 07:01:46 +00:00
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EXPORT_SYMBOL_GPL(tm_abort);
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2013-02-13 16:21:35 +00:00
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/* void tm_reclaim(struct thread_struct *thread,
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* uint8_t cause)
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*
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* - Performs a full reclaim. This destroys outstanding
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* transactions and updates thread->regs.tm_ckpt_* with the
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* original checkpointed state. Note that thread->regs is
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* unchanged.
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*
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* Purpose is to both abort transactions of, and preserve the state of,
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* a transactions at a context switch. We preserve/restore both sets of process
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* state to restore them when the thread's scheduled again. We continue in
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* userland as though nothing happened, but when the transaction is resumed
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* they will abort back to the checkpointed state we save out here.
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*
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* Call with IRQs off, stacks get all out of sync for some periods in here!
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*/
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_GLOBAL(tm_reclaim)
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2017-11-02 03:09:05 +00:00
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mfcr r5
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2013-02-13 16:21:35 +00:00
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mflr r0
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2017-11-02 03:09:05 +00:00
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stw r5, 8(r1)
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2013-02-13 16:21:35 +00:00
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std r0, 16(r1)
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2014-03-09 23:52:17 +00:00
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std r2, STK_GOT(r1)
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2013-02-13 16:21:35 +00:00
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stdu r1, -TM_FRAME_SIZE(r1)
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/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
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2014-03-09 23:48:44 +00:00
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std r3, STK_PARAM(R3)(r1)
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2013-02-13 16:21:35 +00:00
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SAVE_NVGPRS(r1)
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2016-06-28 03:01:04 +00:00
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/* We need to setup MSR for VSX register save instructions. */
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2013-02-13 16:21:35 +00:00
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mfmsr r14
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mr r15, r14
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ori r15, r15, MSR_FP
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2016-06-28 03:01:04 +00:00
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li r16, 0
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2013-10-02 07:15:15 +00:00
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ori r16, r16, MSR_EE /* IRQs hard off */
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2013-06-28 08:17:09 +00:00
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andc r15, r15, r16
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2013-02-13 16:21:35 +00:00
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oris r15, r15, MSR_VEC@h
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r15,r15, MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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mtmsrd r15
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std r14, TM_FRAME_L0(r1)
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2014-03-28 05:40:34 +00:00
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/* Do sanity check on MSR to make sure we are suspended */
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li r7, (MSR_TS_S)@higher
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srdi r6, r14, 32
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and r6, r6, r7
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1: tdeqi r6, 0
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
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2016-09-23 06:18:24 +00:00
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/* Stash the stack pointer away for use after reclaim */
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std r1, PACAR1(r13)
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2016-06-28 03:01:04 +00:00
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/* Clear MSR RI since we are about to change r1, EE is already off. */
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2017-11-02 03:09:05 +00:00
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li r5, 0
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mtmsrd r5, 1
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2016-06-28 03:01:04 +00:00
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/*
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* BE CAREFUL HERE:
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* At this point we can't take an SLB miss since we have MSR_RI
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* off. Load only to/from the stack/paca which are in SLB bolted regions
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* until we turn MSR RI back on.
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*
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* The moment we treclaim, ALL of our GPRs will switch
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2013-02-13 16:21:35 +00:00
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* to user register state. (FPRs, CCR etc. also!)
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* Use an sprg and a tm_scratch in the PACA to shuffle.
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*/
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2017-11-02 03:09:05 +00:00
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TRECLAIM(R4) /* Cause in r4 */
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2013-02-13 16:21:35 +00:00
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/* ******************** GPRs ******************** */
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/* Stash the checkpointed r13 away in the scratch SPR and get the real
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* paca
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*/
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SET_SCRATCH0(r13)
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GET_PACA(r13)
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/* Stash the checkpointed r1 away in paca tm_scratch and get the real
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* stack pointer back
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*/
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std r1, PACATMSCRATCH(r13)
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ld r1, PACAR1(r13)
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2013-09-26 03:29:09 +00:00
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/* Store the PPR in r11 and reset to decent value */
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std r11, GPR11(r1) /* Temporary stash */
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2016-06-28 03:01:04 +00:00
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/* Reset MSR RI so we can take SLB faults again */
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li r11, MSR_RI
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mtmsrd r11, 1
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2013-09-26 03:29:09 +00:00
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mfspr r11, SPRN_PPR
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HMT_MEDIUM
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2013-02-13 16:21:35 +00:00
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/* Now get some more GPRS free */
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std r7, GPR7(r1) /* Temporary stash */
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std r12, GPR12(r1) /* '' '' '' */
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2014-03-09 23:48:44 +00:00
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ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
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2013-02-13 16:21:35 +00:00
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2013-09-26 03:29:09 +00:00
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std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
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2013-02-13 16:21:35 +00:00
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addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
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/* Make r7 look like an exception frame so that we
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* can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
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*/
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subi r7, r7, STACK_FRAME_OVERHEAD
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/* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
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SAVE_GPR(0, r7) /* user r0 */
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SAVE_GPR(2, r7) /* user r2 */
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SAVE_4GPRS(3, r7) /* user r3-r6 */
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2013-09-26 03:29:09 +00:00
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SAVE_GPR(8, r7) /* user r8 */
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SAVE_GPR(9, r7) /* user r9 */
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SAVE_GPR(10, r7) /* user r10 */
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2013-02-13 16:21:35 +00:00
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ld r3, PACATMSCRATCH(r13) /* user r1 */
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ld r4, GPR7(r1) /* user r7 */
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2013-09-26 03:29:09 +00:00
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ld r5, GPR11(r1) /* user r11 */
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ld r6, GPR12(r1) /* user r12 */
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GET_SCRATCH0(8) /* user r13 */
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2013-02-13 16:21:35 +00:00
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std r3, GPR1(r7)
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std r4, GPR7(r7)
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2013-09-26 03:29:09 +00:00
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std r5, GPR11(r7)
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std r6, GPR12(r7)
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std r8, GPR13(r7)
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2013-02-13 16:21:35 +00:00
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SAVE_NVGPRS(r7) /* user r14-r31 */
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/* ******************** NIP ******************** */
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mfspr r3, SPRN_TFHAR
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std r3, _NIP(r7) /* Returns to failhandler */
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/* The checkpointed NIP is ignored when rescheduling/rechkpting,
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* but is used in signal return to 'wind back' to the abort handler.
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*/
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/* ******************** CR,LR,CCR,MSR ********** */
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mfctr r3
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mflr r4
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mfcr r5
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mfxer r6
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|
|
|
|
|
std r3, _CTR(r7)
|
|
|
|
std r4, _LINK(r7)
|
|
|
|
std r5, _CCR(r7)
|
|
|
|
std r6, _XER(r7)
|
|
|
|
|
2013-08-09 07:29:31 +00:00
|
|
|
|
2013-09-26 03:29:09 +00:00
|
|
|
/* ******************** TAR, DSCR ********** */
|
2013-08-09 07:29:31 +00:00
|
|
|
mfspr r3, SPRN_TAR
|
2013-09-26 03:29:09 +00:00
|
|
|
mfspr r4, SPRN_DSCR
|
2013-08-09 07:29:31 +00:00
|
|
|
|
|
|
|
std r3, THREAD_TM_TAR(r12)
|
2013-09-26 03:29:09 +00:00
|
|
|
std r4, THREAD_TM_DSCR(r12)
|
2013-08-09 07:29:31 +00:00
|
|
|
|
2013-02-13 16:21:35 +00:00
|
|
|
/* MSR and flags: We don't change CRs, and we don't need to alter
|
|
|
|
* MSR.
|
|
|
|
*/
|
|
|
|
|
2016-09-23 06:18:24 +00:00
|
|
|
|
|
|
|
/* ******************** FPR/VR/VSRs ************
|
2017-11-02 03:09:05 +00:00
|
|
|
* After reclaiming, capture the checkpointed FPRs/VRs.
|
2016-09-23 06:18:24 +00:00
|
|
|
*
|
|
|
|
* We enabled VEC/FP/VSX in the msr above, so we can execute these
|
|
|
|
* instructions!
|
|
|
|
*/
|
|
|
|
mr r3, r12
|
|
|
|
|
2017-11-02 03:09:05 +00:00
|
|
|
/* Altivec (VEC/VMX/VR)*/
|
2016-09-23 06:18:25 +00:00
|
|
|
addi r7, r3, THREAD_CKVRSTATE
|
2016-09-23 06:18:24 +00:00
|
|
|
SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
|
|
|
|
mfvscr v0
|
|
|
|
li r6, VRSTATE_VSCR
|
|
|
|
stvx v0, r7, r6
|
2017-11-02 03:09:05 +00:00
|
|
|
|
|
|
|
/* VRSAVE */
|
2016-09-23 06:18:24 +00:00
|
|
|
mfspr r0, SPRN_VRSAVE
|
2016-09-23 06:18:25 +00:00
|
|
|
std r0, THREAD_CKVRSAVE(r3)
|
2016-09-23 06:18:24 +00:00
|
|
|
|
2017-11-02 03:09:05 +00:00
|
|
|
/* Floating Point (FP) */
|
2016-09-23 06:18:25 +00:00
|
|
|
addi r7, r3, THREAD_CKFPSTATE
|
2016-09-23 06:18:24 +00:00
|
|
|
SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
|
|
|
|
mffs fr0
|
|
|
|
stfd fr0,FPSTATE_FPSCR(r7)
|
|
|
|
|
|
|
|
|
2013-02-13 16:21:35 +00:00
|
|
|
/* TM regs, incl TEXASR -- these live in thread_struct. Note they've
|
|
|
|
* been updated by the treclaim, to explain to userland the failure
|
|
|
|
* cause (aborted).
|
|
|
|
*/
|
|
|
|
mfspr r0, SPRN_TEXASR
|
|
|
|
mfspr r3, SPRN_TFHAR
|
|
|
|
mfspr r4, SPRN_TFIAR
|
|
|
|
std r0, THREAD_TM_TEXASR(r12)
|
|
|
|
std r3, THREAD_TM_TFHAR(r12)
|
|
|
|
std r4, THREAD_TM_TFIAR(r12)
|
|
|
|
|
2013-09-26 03:29:09 +00:00
|
|
|
/* AMR is checkpointed too, but is unsupported by Linux. */
|
2013-02-13 16:21:35 +00:00
|
|
|
|
|
|
|
/* Restore original MSR/IRQ state & clear TM mode */
|
|
|
|
ld r14, TM_FRAME_L0(r1) /* Orig MSR */
|
2016-09-23 06:18:24 +00:00
|
|
|
|
2013-02-13 16:21:35 +00:00
|
|
|
li r15, 0
|
|
|
|
rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
|
|
|
|
mtmsrd r14
|
|
|
|
|
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
|
|
|
addi r1, r1, TM_FRAME_SIZE
|
2013-10-15 03:36:31 +00:00
|
|
|
lwz r4, 8(r1)
|
2013-02-13 16:21:35 +00:00
|
|
|
ld r0, 16(r1)
|
|
|
|
mtcr r4
|
|
|
|
mtlr r0
|
2014-03-09 23:52:17 +00:00
|
|
|
ld r2, STK_GOT(r1)
|
2013-09-26 03:29:09 +00:00
|
|
|
|
2014-05-21 06:32:38 +00:00
|
|
|
/* Load CPU's default DSCR */
|
2015-05-21 06:43:03 +00:00
|
|
|
ld r0, PACA_DSCR_DEFAULT(r13)
|
2013-09-26 03:29:09 +00:00
|
|
|
mtspr SPRN_DSCR, r0
|
|
|
|
|
2013-02-13 16:21:35 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
2018-02-05 05:17:16 +00:00
|
|
|
/*
|
|
|
|
* void __tm_recheckpoint(struct thread_struct *thread)
|
2013-02-13 16:21:35 +00:00
|
|
|
* - Restore the checkpointed register state saved by tm_reclaim
|
|
|
|
* when we switch_to a process.
|
|
|
|
*
|
|
|
|
* Call with IRQs off, stacks get all out of sync for
|
|
|
|
* some periods in here!
|
|
|
|
*/
|
2014-04-04 09:19:48 +00:00
|
|
|
_GLOBAL(__tm_recheckpoint)
|
2013-02-13 16:21:35 +00:00
|
|
|
mfcr r5
|
|
|
|
mflr r0
|
2013-10-15 03:36:31 +00:00
|
|
|
stw r5, 8(r1)
|
2013-02-13 16:21:35 +00:00
|
|
|
std r0, 16(r1)
|
2014-03-09 23:52:17 +00:00
|
|
|
std r2, STK_GOT(r1)
|
2013-02-13 16:21:35 +00:00
|
|
|
stdu r1, -TM_FRAME_SIZE(r1)
|
|
|
|
|
|
|
|
/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
|
|
|
|
* This is used for backing up the NVGPRs:
|
|
|
|
*/
|
|
|
|
SAVE_NVGPRS(r1)
|
|
|
|
|
|
|
|
/* Load complete register state from ts_ckpt* registers */
|
|
|
|
|
|
|
|
addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
|
|
|
|
|
|
|
|
/* Make r7 look like an exception frame so that we
|
|
|
|
* can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
|
|
|
|
*/
|
|
|
|
subi r7, r7, STACK_FRAME_OVERHEAD
|
|
|
|
|
2017-11-02 03:09:05 +00:00
|
|
|
/* We need to setup MSR for FP/VMX/VSX register save instructions. */
|
2013-02-13 16:21:35 +00:00
|
|
|
mfmsr r6
|
2017-11-02 03:09:05 +00:00
|
|
|
mr r5, r6
|
2013-02-13 16:21:35 +00:00
|
|
|
ori r5, r5, MSR_FP
|
2017-11-02 03:09:05 +00:00
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
oris r5, r5, MSR_VEC@h
|
|
|
|
#endif
|
2013-02-13 16:21:35 +00:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
BEGIN_FTR_SECTION
|
2017-11-02 03:09:05 +00:00
|
|
|
oris r5,r5, MSR_VSX@h
|
2013-02-13 16:21:35 +00:00
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_VSX)
|
|
|
|
#endif
|
2017-11-02 03:09:05 +00:00
|
|
|
mtmsrd r5
|
2013-02-13 16:21:35 +00:00
|
|
|
|
2013-04-09 06:18:55 +00:00
|
|
|
#ifdef CONFIG_ALTIVEC
|
2016-09-23 06:18:24 +00:00
|
|
|
/*
|
|
|
|
* FP and VEC registers: These are recheckpointed from
|
|
|
|
* thread.ckfp_state and thread.ckvr_state respectively. The
|
|
|
|
* thread.fp_state[] version holds the 'live' (transactional)
|
|
|
|
* and will be loaded subsequently by any FPUnavailable trap.
|
2013-02-13 16:21:35 +00:00
|
|
|
*/
|
2016-09-23 06:18:25 +00:00
|
|
|
addi r8, r3, THREAD_CKVRSTATE
|
2013-09-10 10:20:42 +00:00
|
|
|
li r5, VRSTATE_VSCR
|
2015-02-09 22:51:22 +00:00
|
|
|
lvx v0, r8, r5
|
|
|
|
mtvscr v0
|
2013-09-10 10:20:42 +00:00
|
|
|
REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
|
2016-09-23 06:18:25 +00:00
|
|
|
ld r5, THREAD_CKVRSAVE(r3)
|
2013-02-13 16:21:35 +00:00
|
|
|
mtspr SPRN_VRSAVE, r5
|
2013-04-09 06:18:55 +00:00
|
|
|
#endif
|
2013-02-13 16:21:35 +00:00
|
|
|
|
2016-09-23 06:18:25 +00:00
|
|
|
addi r8, r3, THREAD_CKFPSTATE
|
2013-09-10 10:20:42 +00:00
|
|
|
lfd fr0, FPSTATE_FPSCR(r8)
|
2013-02-13 16:21:35 +00:00
|
|
|
MTFSF_L(fr0)
|
2013-09-10 10:20:42 +00:00
|
|
|
REST_32FPRS_VSRS(0, R4, R8)
|
2013-02-13 16:21:35 +00:00
|
|
|
|
|
|
|
mtmsr r6 /* FP/Vec off again! */
|
|
|
|
|
|
|
|
restore_gprs:
|
2013-08-09 07:29:31 +00:00
|
|
|
|
2013-09-26 03:29:09 +00:00
|
|
|
/* ******************** CR,LR,CCR,MSR ********** */
|
|
|
|
ld r4, _CTR(r7)
|
|
|
|
ld r5, _LINK(r7)
|
|
|
|
ld r8, _XER(r7)
|
2013-08-09 07:29:31 +00:00
|
|
|
|
2013-09-26 03:29:09 +00:00
|
|
|
mtctr r4
|
|
|
|
mtlr r5
|
|
|
|
mtxer r8
|
2013-08-09 07:29:31 +00:00
|
|
|
|
2013-09-26 03:29:09 +00:00
|
|
|
/* ******************** TAR ******************** */
|
|
|
|
ld r4, THREAD_TM_TAR(r3)
|
|
|
|
mtspr SPRN_TAR, r4
|
2013-02-13 16:21:35 +00:00
|
|
|
|
2013-09-26 03:29:09 +00:00
|
|
|
/* Load up the PPR and DSCR in GPRs only at this stage */
|
|
|
|
ld r5, THREAD_TM_DSCR(r3)
|
|
|
|
ld r6, THREAD_TM_PPR(r3)
|
2013-02-13 16:21:35 +00:00
|
|
|
|
2014-03-28 05:40:34 +00:00
|
|
|
REST_GPR(0, r7) /* GPR0 */
|
|
|
|
REST_2GPRS(2, r7) /* GPR2-3 */
|
2013-09-26 03:29:09 +00:00
|
|
|
REST_GPR(4, r7) /* GPR4 */
|
2013-02-13 16:21:35 +00:00
|
|
|
REST_4GPRS(8, r7) /* GPR8-11 */
|
|
|
|
REST_2GPRS(12, r7) /* GPR12-13 */
|
|
|
|
|
|
|
|
REST_NVGPRS(r7) /* GPR14-31 */
|
|
|
|
|
2013-09-26 03:29:09 +00:00
|
|
|
/* Load up PPR and DSCR here so we don't run with user values for long
|
|
|
|
*/
|
|
|
|
mtspr SPRN_DSCR, r5
|
|
|
|
mtspr SPRN_PPR, r6
|
|
|
|
|
2014-03-28 05:40:34 +00:00
|
|
|
/* Do final sanity check on TEXASR to make sure FS is set. Do this
|
|
|
|
* here before we load up the userspace r1 so any bugs we hit will get
|
|
|
|
* a call chain */
|
|
|
|
mfspr r5, SPRN_TEXASR
|
|
|
|
srdi r5, r5, 16
|
|
|
|
li r6, (TEXASR_FS)@h
|
|
|
|
and r6, r6, r5
|
|
|
|
1: tdeqi r6, 0
|
|
|
|
EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
|
|
|
|
|
|
|
|
/* Do final sanity check on MSR to make sure we are not transactional
|
|
|
|
* or suspended
|
|
|
|
*/
|
|
|
|
mfmsr r6
|
|
|
|
li r5, (MSR_TS_MASK)@higher
|
|
|
|
srdi r6, r6, 32
|
|
|
|
and r6, r6, r5
|
|
|
|
1: tdnei r6, 0
|
|
|
|
EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
|
|
|
|
|
|
|
|
/* Restore CR */
|
|
|
|
ld r6, _CCR(r7)
|
|
|
|
mtcr r6
|
|
|
|
|
2013-09-26 03:29:09 +00:00
|
|
|
REST_GPR(6, r7)
|
2016-06-28 03:01:04 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Store r1 and r5 on the stack so that we can access them
|
|
|
|
* after we clear MSR RI.
|
|
|
|
*/
|
|
|
|
|
|
|
|
REST_GPR(5, r7)
|
|
|
|
std r5, -8(r1)
|
|
|
|
ld r5, GPR1(r7)
|
|
|
|
std r5, -16(r1)
|
|
|
|
|
|
|
|
REST_GPR(7, r7)
|
|
|
|
|
|
|
|
/* Clear MSR RI since we are about to change r1. EE is already off */
|
|
|
|
li r5, 0
|
|
|
|
mtmsrd r5, 1
|
|
|
|
|
|
|
|
/*
|
|
|
|
* BE CAREFUL HERE:
|
|
|
|
* At this point we can't take an SLB miss since we have MSR_RI
|
|
|
|
* off. Load only to/from the stack/paca which are in SLB bolted regions
|
|
|
|
* until we turn MSR RI back on.
|
|
|
|
*/
|
|
|
|
|
2016-07-06 04:58:06 +00:00
|
|
|
SET_SCRATCH0(r1)
|
2016-06-28 03:01:04 +00:00
|
|
|
ld r5, -8(r1)
|
|
|
|
ld r1, -16(r1)
|
2013-02-13 16:21:35 +00:00
|
|
|
|
|
|
|
/* Commit register state as checkpointed state: */
|
|
|
|
TRECHKPT
|
|
|
|
|
2013-09-26 03:29:09 +00:00
|
|
|
HMT_MEDIUM
|
|
|
|
|
2013-02-13 16:21:35 +00:00
|
|
|
/* Our transactional state has now changed.
|
|
|
|
*
|
|
|
|
* Now just get out of here. Transactional (current) state will be
|
|
|
|
* updated once restore is called on the return path in the _switch-ed
|
|
|
|
* -to process.
|
|
|
|
*/
|
|
|
|
|
|
|
|
GET_PACA(r13)
|
|
|
|
GET_SCRATCH0(r1)
|
|
|
|
|
2013-06-28 08:17:09 +00:00
|
|
|
/* R1 is restored, so we are recoverable again. EE is still off */
|
|
|
|
li r4, MSR_RI
|
|
|
|
mtmsrd r4, 1
|
|
|
|
|
2013-02-13 16:21:35 +00:00
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
|
|
|
addi r1, r1, TM_FRAME_SIZE
|
2013-10-15 03:36:31 +00:00
|
|
|
lwz r4, 8(r1)
|
2013-02-13 16:21:35 +00:00
|
|
|
ld r0, 16(r1)
|
|
|
|
mtcr r4
|
|
|
|
mtlr r0
|
2014-03-09 23:52:17 +00:00
|
|
|
ld r2, STK_GOT(r1)
|
2013-09-26 03:29:09 +00:00
|
|
|
|
2014-05-21 06:32:38 +00:00
|
|
|
/* Load CPU's default DSCR */
|
2015-05-21 06:43:03 +00:00
|
|
|
ld r0, PACA_DSCR_DEFAULT(r13)
|
2013-09-26 03:29:09 +00:00
|
|
|
mtspr SPRN_DSCR, r0
|
|
|
|
|
2013-02-13 16:21:35 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
/* ****************************************************************** */
|