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38 lines
1.5 KiB
Plaintext
38 lines
1.5 KiB
Plaintext
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* ARM SMMUv3 Architecture Implementation
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The SMMUv3 architecture is a significant deparature from previous
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revisions, replacing the MMIO register interface with in-memory command
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and event queues and adding support for the ATS and PRI components of
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the PCIe specification.
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** SMMUv3 required properties:
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- compatible : Should include:
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* "arm,smmu-v3" for any SMMUv3 compliant
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implementation. This entry should be last in the
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compatible list.
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- reg : Base address and size of the SMMU.
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- interrupts : Non-secure interrupt list describing the wired
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interrupt sources corresponding to entries in
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interrupt-names. If no wired interrupts are
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present then this property may be omitted.
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- interrupt-names : When the interrupts property is present, should
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include the following:
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* "eventq" - Event Queue not empty
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* "priq" - PRI Queue not empty
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* "cmdq-sync" - CMD_SYNC complete
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* "gerror" - Global Error activated
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** SMMUv3 optional properties:
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- dma-coherent : Present if DMA operations made by the SMMU (page
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table walks, stream table accesses etc) are cache
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coherent with the CPU.
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NOTE: this only applies to the SMMU itself, not
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masters connected upstream of the SMMU.
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