2012-04-27 12:26:17 +00:00
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/*
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* imx6q pinctrl driver based on imx pinmux core
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*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Copyright (C) 2012 Linaro, Inc.
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*
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* Author: Dong Aisheng <dong.aisheng@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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enum imx6q_pads {
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2013-02-20 02:32:52 +00:00
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MX6Q_PAD_RESERVE0 = 0,
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MX6Q_PAD_RESERVE1 = 1,
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MX6Q_PAD_RESERVE2 = 2,
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MX6Q_PAD_RESERVE3 = 3,
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MX6Q_PAD_RESERVE4 = 4,
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MX6Q_PAD_RESERVE5 = 5,
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MX6Q_PAD_RESERVE6 = 6,
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MX6Q_PAD_RESERVE7 = 7,
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MX6Q_PAD_RESERVE8 = 8,
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MX6Q_PAD_RESERVE9 = 9,
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MX6Q_PAD_RESERVE10 = 10,
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MX6Q_PAD_RESERVE11 = 11,
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MX6Q_PAD_RESERVE12 = 12,
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MX6Q_PAD_RESERVE13 = 13,
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MX6Q_PAD_RESERVE14 = 14,
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MX6Q_PAD_RESERVE15 = 15,
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MX6Q_PAD_RESERVE16 = 16,
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MX6Q_PAD_RESERVE17 = 17,
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MX6Q_PAD_RESERVE18 = 18,
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MX6Q_PAD_SD2_DAT1 = 19,
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MX6Q_PAD_SD2_DAT2 = 20,
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MX6Q_PAD_SD2_DAT0 = 21,
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MX6Q_PAD_RGMII_TXC = 22,
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MX6Q_PAD_RGMII_TD0 = 23,
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MX6Q_PAD_RGMII_TD1 = 24,
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MX6Q_PAD_RGMII_TD2 = 25,
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MX6Q_PAD_RGMII_TD3 = 26,
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MX6Q_PAD_RGMII_RX_CTL = 27,
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MX6Q_PAD_RGMII_RD0 = 28,
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MX6Q_PAD_RGMII_TX_CTL = 29,
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MX6Q_PAD_RGMII_RD1 = 30,
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MX6Q_PAD_RGMII_RD2 = 31,
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MX6Q_PAD_RGMII_RD3 = 32,
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MX6Q_PAD_RGMII_RXC = 33,
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MX6Q_PAD_EIM_A25 = 34,
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MX6Q_PAD_EIM_EB2 = 35,
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MX6Q_PAD_EIM_D16 = 36,
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MX6Q_PAD_EIM_D17 = 37,
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MX6Q_PAD_EIM_D18 = 38,
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MX6Q_PAD_EIM_D19 = 39,
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MX6Q_PAD_EIM_D20 = 40,
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MX6Q_PAD_EIM_D21 = 41,
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MX6Q_PAD_EIM_D22 = 42,
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MX6Q_PAD_EIM_D23 = 43,
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MX6Q_PAD_EIM_EB3 = 44,
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MX6Q_PAD_EIM_D24 = 45,
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MX6Q_PAD_EIM_D25 = 46,
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MX6Q_PAD_EIM_D26 = 47,
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MX6Q_PAD_EIM_D27 = 48,
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MX6Q_PAD_EIM_D28 = 49,
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MX6Q_PAD_EIM_D29 = 50,
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MX6Q_PAD_EIM_D30 = 51,
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MX6Q_PAD_EIM_D31 = 52,
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MX6Q_PAD_EIM_A24 = 53,
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MX6Q_PAD_EIM_A23 = 54,
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MX6Q_PAD_EIM_A22 = 55,
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MX6Q_PAD_EIM_A21 = 56,
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MX6Q_PAD_EIM_A20 = 57,
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MX6Q_PAD_EIM_A19 = 58,
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MX6Q_PAD_EIM_A18 = 59,
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MX6Q_PAD_EIM_A17 = 60,
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MX6Q_PAD_EIM_A16 = 61,
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MX6Q_PAD_EIM_CS0 = 62,
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MX6Q_PAD_EIM_CS1 = 63,
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MX6Q_PAD_EIM_OE = 64,
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MX6Q_PAD_EIM_RW = 65,
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MX6Q_PAD_EIM_LBA = 66,
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MX6Q_PAD_EIM_EB0 = 67,
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MX6Q_PAD_EIM_EB1 = 68,
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MX6Q_PAD_EIM_DA0 = 69,
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MX6Q_PAD_EIM_DA1 = 70,
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MX6Q_PAD_EIM_DA2 = 71,
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MX6Q_PAD_EIM_DA3 = 72,
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MX6Q_PAD_EIM_DA4 = 73,
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MX6Q_PAD_EIM_DA5 = 74,
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MX6Q_PAD_EIM_DA6 = 75,
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MX6Q_PAD_EIM_DA7 = 76,
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MX6Q_PAD_EIM_DA8 = 77,
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MX6Q_PAD_EIM_DA9 = 78,
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MX6Q_PAD_EIM_DA10 = 79,
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MX6Q_PAD_EIM_DA11 = 80,
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MX6Q_PAD_EIM_DA12 = 81,
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MX6Q_PAD_EIM_DA13 = 82,
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MX6Q_PAD_EIM_DA14 = 83,
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MX6Q_PAD_EIM_DA15 = 84,
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MX6Q_PAD_EIM_WAIT = 85,
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MX6Q_PAD_EIM_BCLK = 86,
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MX6Q_PAD_DI0_DISP_CLK = 87,
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MX6Q_PAD_DI0_PIN15 = 88,
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MX6Q_PAD_DI0_PIN2 = 89,
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MX6Q_PAD_DI0_PIN3 = 90,
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MX6Q_PAD_DI0_PIN4 = 91,
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MX6Q_PAD_DISP0_DAT0 = 92,
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MX6Q_PAD_DISP0_DAT1 = 93,
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MX6Q_PAD_DISP0_DAT2 = 94,
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MX6Q_PAD_DISP0_DAT3 = 95,
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MX6Q_PAD_DISP0_DAT4 = 96,
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MX6Q_PAD_DISP0_DAT5 = 97,
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MX6Q_PAD_DISP0_DAT6 = 98,
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MX6Q_PAD_DISP0_DAT7 = 99,
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MX6Q_PAD_DISP0_DAT8 = 100,
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MX6Q_PAD_DISP0_DAT9 = 101,
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MX6Q_PAD_DISP0_DAT10 = 102,
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MX6Q_PAD_DISP0_DAT11 = 103,
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MX6Q_PAD_DISP0_DAT12 = 104,
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MX6Q_PAD_DISP0_DAT13 = 105,
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MX6Q_PAD_DISP0_DAT14 = 106,
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MX6Q_PAD_DISP0_DAT15 = 107,
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MX6Q_PAD_DISP0_DAT16 = 108,
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MX6Q_PAD_DISP0_DAT17 = 109,
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MX6Q_PAD_DISP0_DAT18 = 110,
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MX6Q_PAD_DISP0_DAT19 = 111,
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MX6Q_PAD_DISP0_DAT20 = 112,
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MX6Q_PAD_DISP0_DAT21 = 113,
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MX6Q_PAD_DISP0_DAT22 = 114,
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MX6Q_PAD_DISP0_DAT23 = 115,
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MX6Q_PAD_ENET_MDIO = 116,
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MX6Q_PAD_ENET_REF_CLK = 117,
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MX6Q_PAD_ENET_RX_ER = 118,
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MX6Q_PAD_ENET_CRS_DV = 119,
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MX6Q_PAD_ENET_RXD1 = 120,
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MX6Q_PAD_ENET_RXD0 = 121,
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MX6Q_PAD_ENET_TX_EN = 122,
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MX6Q_PAD_ENET_TXD1 = 123,
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MX6Q_PAD_ENET_TXD0 = 124,
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MX6Q_PAD_ENET_MDC = 125,
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MX6Q_PAD_KEY_COL0 = 126,
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MX6Q_PAD_KEY_ROW0 = 127,
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MX6Q_PAD_KEY_COL1 = 128,
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MX6Q_PAD_KEY_ROW1 = 129,
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MX6Q_PAD_KEY_COL2 = 130,
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MX6Q_PAD_KEY_ROW2 = 131,
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MX6Q_PAD_KEY_COL3 = 132,
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MX6Q_PAD_KEY_ROW3 = 133,
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MX6Q_PAD_KEY_COL4 = 134,
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MX6Q_PAD_KEY_ROW4 = 135,
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MX6Q_PAD_GPIO_0 = 136,
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MX6Q_PAD_GPIO_1 = 137,
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MX6Q_PAD_GPIO_9 = 138,
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MX6Q_PAD_GPIO_3 = 139,
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MX6Q_PAD_GPIO_6 = 140,
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MX6Q_PAD_GPIO_2 = 141,
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MX6Q_PAD_GPIO_4 = 142,
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MX6Q_PAD_GPIO_5 = 143,
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MX6Q_PAD_GPIO_7 = 144,
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MX6Q_PAD_GPIO_8 = 145,
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MX6Q_PAD_GPIO_16 = 146,
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MX6Q_PAD_GPIO_17 = 147,
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MX6Q_PAD_GPIO_18 = 148,
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MX6Q_PAD_GPIO_19 = 149,
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MX6Q_PAD_CSI0_PIXCLK = 150,
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MX6Q_PAD_CSI0_MCLK = 151,
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MX6Q_PAD_CSI0_DATA_EN = 152,
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MX6Q_PAD_CSI0_VSYNC = 153,
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MX6Q_PAD_CSI0_DAT4 = 154,
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MX6Q_PAD_CSI0_DAT5 = 155,
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MX6Q_PAD_CSI0_DAT6 = 156,
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MX6Q_PAD_CSI0_DAT7 = 157,
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MX6Q_PAD_CSI0_DAT8 = 158,
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MX6Q_PAD_CSI0_DAT9 = 159,
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MX6Q_PAD_CSI0_DAT10 = 160,
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MX6Q_PAD_CSI0_DAT11 = 161,
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MX6Q_PAD_CSI0_DAT12 = 162,
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MX6Q_PAD_CSI0_DAT13 = 163,
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MX6Q_PAD_CSI0_DAT14 = 164,
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MX6Q_PAD_CSI0_DAT15 = 165,
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MX6Q_PAD_CSI0_DAT16 = 166,
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MX6Q_PAD_CSI0_DAT17 = 167,
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MX6Q_PAD_CSI0_DAT18 = 168,
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MX6Q_PAD_CSI0_DAT19 = 169,
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MX6Q_PAD_SD3_DAT7 = 170,
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MX6Q_PAD_SD3_DAT6 = 171,
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MX6Q_PAD_SD3_DAT5 = 172,
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MX6Q_PAD_SD3_DAT4 = 173,
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MX6Q_PAD_SD3_CMD = 174,
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MX6Q_PAD_SD3_CLK = 175,
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MX6Q_PAD_SD3_DAT0 = 176,
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MX6Q_PAD_SD3_DAT1 = 177,
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MX6Q_PAD_SD3_DAT2 = 178,
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MX6Q_PAD_SD3_DAT3 = 179,
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MX6Q_PAD_SD3_RST = 180,
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MX6Q_PAD_NANDF_CLE = 181,
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MX6Q_PAD_NANDF_ALE = 182,
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MX6Q_PAD_NANDF_WP_B = 183,
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MX6Q_PAD_NANDF_RB0 = 184,
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MX6Q_PAD_NANDF_CS0 = 185,
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MX6Q_PAD_NANDF_CS1 = 186,
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MX6Q_PAD_NANDF_CS2 = 187,
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MX6Q_PAD_NANDF_CS3 = 188,
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MX6Q_PAD_SD4_CMD = 189,
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MX6Q_PAD_SD4_CLK = 190,
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MX6Q_PAD_NANDF_D0 = 191,
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MX6Q_PAD_NANDF_D1 = 192,
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MX6Q_PAD_NANDF_D2 = 193,
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MX6Q_PAD_NANDF_D3 = 194,
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MX6Q_PAD_NANDF_D4 = 195,
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MX6Q_PAD_NANDF_D5 = 196,
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MX6Q_PAD_NANDF_D6 = 197,
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MX6Q_PAD_NANDF_D7 = 198,
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MX6Q_PAD_SD4_DAT0 = 199,
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MX6Q_PAD_SD4_DAT1 = 200,
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MX6Q_PAD_SD4_DAT2 = 201,
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MX6Q_PAD_SD4_DAT3 = 202,
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MX6Q_PAD_SD4_DAT4 = 203,
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MX6Q_PAD_SD4_DAT5 = 204,
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MX6Q_PAD_SD4_DAT6 = 205,
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MX6Q_PAD_SD4_DAT7 = 206,
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MX6Q_PAD_SD1_DAT1 = 207,
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MX6Q_PAD_SD1_DAT0 = 208,
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MX6Q_PAD_SD1_DAT3 = 209,
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MX6Q_PAD_SD1_CMD = 210,
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MX6Q_PAD_SD1_DAT2 = 211,
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MX6Q_PAD_SD1_CLK = 212,
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MX6Q_PAD_SD2_CLK = 213,
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MX6Q_PAD_SD2_CMD = 214,
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MX6Q_PAD_SD2_DAT3 = 215,
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2012-04-27 12:26:17 +00:00
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE0),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE1),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE2),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE3),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE4),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE5),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE6),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE7),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE8),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE9),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE10),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE11),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE12),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE13),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE14),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE15),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE16),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE17),
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IMX_PINCTRL_PIN(MX6Q_PAD_RESERVE18),
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2012-04-27 12:26:17 +00:00
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IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
|
|
|
|
|
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
|
|
|
|
|
.pins = imx6q_pinctrl_pads,
|
|
|
|
|
.npins = ARRAY_SIZE(imx6q_pinctrl_pads),
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-19 18:24:27 +00:00
|
|
|
static struct of_device_id imx6q_pinctrl_of_match[] = {
|
2012-04-27 12:26:17 +00:00
|
|
|
{ .compatible = "fsl,imx6q-iomuxc", },
|
|
|
|
|
{ /* sentinel */ }
|
|
|
|
|
};
|
|
|
|
|
|
2012-12-21 21:10:23 +00:00
|
|
|
static int imx6q_pinctrl_probe(struct platform_device *pdev)
|
2012-04-27 12:26:17 +00:00
|
|
|
{
|
|
|
|
|
return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct platform_driver imx6q_pinctrl_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "imx6q-pinctrl",
|
|
|
|
|
.owner = THIS_MODULE,
|
2013-09-28 12:08:48 +00:00
|
|
|
.of_match_table = imx6q_pinctrl_of_match,
|
2012-04-27 12:26:17 +00:00
|
|
|
},
|
|
|
|
|
.probe = imx6q_pinctrl_probe,
|
2012-11-19 18:21:27 +00:00
|
|
|
.remove = imx_pinctrl_remove,
|
2012-04-27 12:26:17 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init imx6q_pinctrl_init(void)
|
|
|
|
|
{
|
|
|
|
|
return platform_driver_register(&imx6q_pinctrl_driver);
|
|
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}
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arch_initcall(imx6q_pinctrl_init);
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static void __exit imx6q_pinctrl_exit(void)
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{
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platform_driver_unregister(&imx6q_pinctrl_driver);
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}
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module_exit(imx6q_pinctrl_exit);
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MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
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MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
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MODULE_LICENSE("GPL v2");
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