linux/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt

NVIDIA Tegra20 timer

The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
running counter. The first two channels may also trigger a watchdog reset.

Required properties:

- compatible : should be "nvidia,tegra20-timer".
- reg : Specifies base physical address and size of the registers.
- interrupts : A list of 4 interrupts; one per timer channel.
- clocks : Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.

Example:

timer {
	compatible = "nvidia,tegra20-timer";
	reg = <0x60005000 0x60>;
	interrupts = <0 0 0x04
			0 1 0x04
			0 41 0x04
			0 42 0x04>;
	clocks = <&tegra_car 132>;
};
ARM: tegra: define DT bindings for and instantiate timer The Tegra timer provides a number of 29-bit timer channels, a single 32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules. The first two channels may also trigger a legacy watchdog reset. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com> 2012-09-19 18:02:31 +00:00			`NVIDIA Tegra20 timer`

			`The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free`
			`running counter. The first two channels may also trigger a watchdog reset.`

			`Required properties:`

			`- compatible : should be "nvidia,tegra20-timer".`
			`- reg : Specifies base physical address and size of the registers.`
			`- interrupts : A list of 4 interrupts; one per timer channel.`
ARM: tegra: add missing clock documentation to DT bindings Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com> 2013-11-06 21:00:25 +00:00			`- clocks : Must contain one entry, for the module clock.`
			`See ../clocks/clock-bindings.txt for details.`
ARM: tegra: define DT bindings for and instantiate timer The Tegra timer provides a number of 29-bit timer channels, a single 32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules. The first two channels may also trigger a legacy watchdog reset. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com> 2012-09-19 18:02:31 +00:00
			`Example:`

			`timer {`
			`compatible = "nvidia,tegra20-timer";`
			`reg = <0x60005000 0x60>;`
			`interrupts = <0 0 0x04`
			`0 1 0x04`
			`0 41 0x04`
			`0 42 0x04>;`
ARM: tegra: add missing clock documentation to DT bindings Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com> 2013-11-06 21:00:25 +00:00			`clocks = <&tegra_car 132>;`
ARM: tegra: define DT bindings for and instantiate timer The Tegra timer provides a number of 29-bit timer channels, a single 32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules. The first two channels may also trigger a legacy watchdog reset. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com> 2012-09-19 18:02:31 +00:00			`};`