2018-05-01 12:20:40 +00:00
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// SPDX-License-Identifier: GPL-2.0
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//
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// Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
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//
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// Author: Timur Tabi <timur@freescale.com>
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//
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// Copyright 2007-2010 Freescale Semiconductor, Inc.
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//
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// Some notes why imx-pcm-fiq is used instead of DMA on some boards:
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//
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// The i.MX SSI core has some nasty limitations in AC97 mode. While most
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// sane processor vendors have a FIFO per AC97 slot, the i.MX has only
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// one FIFO which combines all valid receive slots. We cannot even select
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// which slots we want to receive. The WM9712 with which this driver
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// was developed with always sends GPIO status data in slot 12 which
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// we receive in our (PCM-) data stream. The only chance we have is to
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// manually skip this data in the FIQ handler. With sampling rates different
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// from 48000Hz not every frame has valid receive data, so the ratio
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// between pcm data and GPIO status data changes. Our FIQ handler is not
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// able to handle this, hence this driver only works with 48000Hz sampling
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// rate.
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// Reading and writing AC97 registers is another challenge. The core
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// provides us status bits when the read register is updated with *another*
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// value. When we read the same register two times (and the register still
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// contains the same value) these status bits are not set. We work
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// around this by not polling these bits but only wait a fixed delay.
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2008-01-11 17:15:26 +00:00
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#include <linux/init.h>
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2012-03-16 08:56:42 +00:00
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#include <linux/io.h>
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2008-01-11 17:15:26 +00:00
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#include <linux/module.h>
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#include <linux/interrupt.h>
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2012-03-29 02:53:41 +00:00
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#include <linux/clk.h>
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2017-04-05 19:44:06 +00:00
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#include <linux/ctype.h>
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2008-01-11 17:15:26 +00:00
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#include <linux/device.h>
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#include <linux/delay.h>
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2017-11-20 22:16:07 +00:00
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#include <linux/mutex.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2013-12-12 10:44:45 +00:00
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#include <linux/spinlock.h>
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2014-04-15 11:02:02 +00:00
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#include <linux/of.h>
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2012-03-16 08:56:42 +00:00
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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2010-03-17 20:15:21 +00:00
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#include <linux/of_platform.h>
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2022-05-10 11:56:48 +00:00
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#include <linux/dma/imx-dma.h>
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2008-01-11 17:15:26 +00:00
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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2013-04-03 09:06:04 +00:00
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#include <sound/dmaengine_pcm.h>
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2008-01-11 17:15:26 +00:00
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#include "fsl_ssi.h"
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2012-03-16 08:56:43 +00:00
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#include "imx-pcm.h"
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2008-01-11 17:15:26 +00:00
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2018-02-12 22:03:09 +00:00
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/* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
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#define RX 0
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#define TX 1
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2008-01-11 17:15:26 +00:00
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/**
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* FSLSSI_I2S_FORMATS: audio formats supported by the SSI
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*
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* The SSI has a limitation in that the samples must be in the same byte
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* order as the host CPU. This is because when multiple bytes are written
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* to the STX register, the bytes and bits must be written in the same
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* order. The STX is a shift register, so all the bits need to be aligned
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* (bit-endianness must match byte-endianness). Processors typically write
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* the bits within a byte in the same order that the bytes of a word are
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* written in. So if the host CPU is big-endian, then only big-endian
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* samples will be written to STX properly.
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*/
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#ifdef __BIG_ENDIAN
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2017-12-18 02:52:04 +00:00
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#define FSLSSI_I2S_FORMATS \
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(SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_BE | \
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SNDRV_PCM_FMTBIT_S18_3BE | \
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SNDRV_PCM_FMTBIT_S20_3BE | \
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SNDRV_PCM_FMTBIT_S24_3BE | \
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SNDRV_PCM_FMTBIT_S24_BE)
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2008-01-11 17:15:26 +00:00
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#else
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2017-12-18 02:52:04 +00:00
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#define FSLSSI_I2S_FORMATS \
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(SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S18_3LE | \
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SNDRV_PCM_FMTBIT_S20_3LE | \
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SNDRV_PCM_FMTBIT_S24_3LE | \
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SNDRV_PCM_FMTBIT_S24_LE)
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2008-01-11 17:15:26 +00:00
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#endif
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2018-02-12 22:03:16 +00:00
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/*
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* In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1:
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* - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS
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* - Also have NB_NF to mark these two clocks will not be inverted
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*/
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#define FSLSSI_AC97_DAIFMT \
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(SND_SOC_DAIFMT_AC97 | \
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2022-05-19 15:42:30 +00:00
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SND_SOC_DAIFMT_BC_FP | \
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2018-02-12 22:03:16 +00:00
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SND_SOC_DAIFMT_NB_NF)
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2017-12-18 02:52:04 +00:00
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#define FSLSSI_SIER_DBG_RX_FLAGS \
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(SSI_SIER_RFF0_EN | \
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SSI_SIER_RLS_EN | \
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SSI_SIER_RFS_EN | \
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SSI_SIER_ROE0_EN | \
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SSI_SIER_RFRC_EN)
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#define FSLSSI_SIER_DBG_TX_FLAGS \
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(SSI_SIER_TFE0_EN | \
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SSI_SIER_TLS_EN | \
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SSI_SIER_TFS_EN | \
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SSI_SIER_TUE0_EN | \
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SSI_SIER_TFRC_EN)
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2013-12-20 13:11:30 +00:00
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enum fsl_ssi_type {
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FSL_SSI_MCP8610,
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FSL_SSI_MX21,
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2013-12-20 13:11:31 +00:00
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FSL_SSI_MX35,
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2013-12-20 13:11:30 +00:00
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FSL_SSI_MX51,
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};
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2017-12-18 02:52:08 +00:00
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struct fsl_ssi_regvals {
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2013-12-20 13:11:33 +00:00
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u32 sier;
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u32 srcr;
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u32 stcr;
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u32 scr;
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};
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2015-09-18 03:09:12 +00:00
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static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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2017-12-18 02:52:03 +00:00
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case REG_SSI_SACCEN:
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case REG_SSI_SACCDIS:
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2015-09-18 03:09:12 +00:00
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return false;
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default:
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return true;
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}
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}
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static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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2017-12-18 02:52:03 +00:00
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case REG_SSI_STX0:
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case REG_SSI_STX1:
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case REG_SSI_SRX0:
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case REG_SSI_SRX1:
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case REG_SSI_SISR:
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case REG_SSI_SFCSR:
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case REG_SSI_SACNT:
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case REG_SSI_SACADD:
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case REG_SSI_SACDAT:
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case REG_SSI_SATAG:
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case REG_SSI_SACCST:
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case REG_SSI_SOR:
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2015-09-18 03:09:12 +00:00
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return true;
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default:
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return false;
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}
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}
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2015-12-20 20:31:48 +00:00
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static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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2017-12-18 02:52:03 +00:00
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case REG_SSI_SRX0:
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case REG_SSI_SRX1:
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case REG_SSI_SISR:
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case REG_SSI_SACADD:
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case REG_SSI_SACDAT:
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case REG_SSI_SATAG:
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2015-12-20 20:31:48 +00:00
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return true;
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default:
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return false;
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}
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}
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2015-09-18 03:09:12 +00:00
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static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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2017-12-18 02:52:03 +00:00
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case REG_SSI_SRX0:
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case REG_SSI_SRX1:
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case REG_SSI_SACCST:
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2015-09-18 03:09:12 +00:00
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return false;
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default:
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return true;
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}
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}
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2014-05-27 08:24:25 +00:00
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static const struct regmap_config fsl_ssi_regconfig = {
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2017-12-18 02:52:03 +00:00
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.max_register = REG_SSI_SACCDIS,
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2014-05-27 08:24:25 +00:00
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.val_format_endian = REGMAP_ENDIAN_NATIVE,
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2017-12-18 02:52:03 +00:00
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.num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1,
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2015-09-18 03:09:12 +00:00
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.readable_reg = fsl_ssi_readable_reg,
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.volatile_reg = fsl_ssi_volatile_reg,
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2015-12-20 20:31:48 +00:00
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.precious_reg = fsl_ssi_precious_reg,
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2015-09-18 03:09:12 +00:00
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.writeable_reg = fsl_ssi_writeable_reg,
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2016-09-19 19:30:28 +00:00
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.cache_type = REGCACHE_FLAT,
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2014-05-27 08:24:25 +00:00
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};
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2009-03-26 16:42:38 +00:00
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2014-05-27 08:24:18 +00:00
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struct fsl_ssi_soc_data {
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bool imx;
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2016-01-18 19:07:44 +00:00
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bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
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2014-05-27 08:24:18 +00:00
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bool offline_config;
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u32 sisr_write_mask;
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};
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2008-01-11 17:15:26 +00:00
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/**
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2020-07-02 19:21:37 +00:00
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* struct fsl_ssi - per-SSI private data
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2017-12-18 02:52:02 +00:00
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* @regs: Pointer to the regmap registers
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2008-01-11 17:15:26 +00:00
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* @irq: IRQ of this SSI
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2014-05-27 08:24:24 +00:00
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* @cpu_dai_drv: CPU DAI driver for this device
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* @dai_fmt: DAI configuration this device is currently used with
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2018-02-12 22:03:12 +00:00
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* @streams: Mask of current active streams: BIT(TX) and BIT(RX)
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2017-12-18 02:52:09 +00:00
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* @i2s_net: I2S and Network mode configurations of SCR register
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2018-04-08 04:40:21 +00:00
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* (this is the initial settings based on the DAI format)
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2018-02-12 22:03:23 +00:00
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* @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
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2014-05-27 08:24:24 +00:00
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* @use_dma: DMA is used or FIQ with stream filter
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2017-12-18 02:52:02 +00:00
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* @use_dual_fifo: DMA with support for dual FIFO mode
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2022-05-10 11:56:48 +00:00
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* @use_dyna_fifo: DMA with support for multi FIFO script
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2017-12-18 02:52:02 +00:00
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* @has_ipg_clk_name: If "ipg" is in the clock name list of device tree
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* @fifo_depth: Depth of the SSI FIFOs
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* @slot_width: Width of each DAI slot
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* @slots: Number of slots
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2017-12-18 02:52:08 +00:00
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* @regvals: Specific RX/TX register settings
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2017-12-18 02:52:02 +00:00
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* @clk: Clock source to access register
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* @baudclk: Clock source to generate bit and frame-sync clocks
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2014-05-27 08:24:24 +00:00
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* @baudclk_streams: Active streams that are using baudclk
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2017-12-18 02:52:02 +00:00
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* @regcache_sfcsr: Cache sfcsr register value during suspend and resume
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* @regcache_sacnt: Cache sacnt register value during suspend and resume
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2014-05-27 08:24:24 +00:00
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* @dma_params_tx: DMA transmit parameters
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* @dma_params_rx: DMA receive parameters
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* @ssi_phys: physical address of the SSI registers
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* @fiq_params: FIQ stream filtering parameters
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2018-02-12 22:03:24 +00:00
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* @card_pdev: Platform_device pointer to register a sound card for PowerPC or
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* to register a CODEC platform device for AC97
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* @card_name: Platform_device name to register a sound card for PowerPC or
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* to register a CODEC platform device for AC97
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* @card_idx: The index of SSI to register a sound card for PowerPC or
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* to register a CODEC platform device for AC97
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2014-05-27 08:24:24 +00:00
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* @dbg_stats: Debugging statistics
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2015-08-12 06:38:18 +00:00
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* @soc: SoC specific data
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2017-12-18 02:52:02 +00:00
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* @dev: Pointer to &pdev->dev
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|
|
* @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are
|
|
|
|
* @fifo_watermark or fewer words in TX fifo or
|
|
|
|
* @fifo_watermark or more empty words in RX fifo.
|
|
|
|
* @dma_maxburst: Max number of words to transfer in one go. So far,
|
|
|
|
* this is always the same as fifo_watermark.
|
|
|
|
* @ac97_reg_lock: Mutex lock to serialize AC97 register access operations
|
2022-05-10 11:56:48 +00:00
|
|
|
* @audio_config: configure for dma multi fifo script
|
2008-01-11 17:15:26 +00:00
|
|
|
*/
|
2017-12-18 02:52:00 +00:00
|
|
|
struct fsl_ssi {
|
2014-05-27 08:24:25 +00:00
|
|
|
struct regmap *regs;
|
2015-01-14 12:48:59 +00:00
|
|
|
int irq;
|
2010-03-17 20:15:21 +00:00
|
|
|
struct snd_soc_dai_driver cpu_dai_drv;
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2014-05-27 08:24:24 +00:00
|
|
|
unsigned int dai_fmt;
|
2018-02-12 22:03:12 +00:00
|
|
|
u8 streams;
|
2017-12-18 02:52:09 +00:00
|
|
|
u8 i2s_net;
|
2018-02-12 22:03:23 +00:00
|
|
|
bool synchronous;
|
2013-07-27 11:31:53 +00:00
|
|
|
bool use_dma;
|
2013-11-13 14:55:26 +00:00
|
|
|
bool use_dual_fifo;
|
2022-05-10 11:56:48 +00:00
|
|
|
bool use_dyna_fifo;
|
2014-09-16 02:13:16 +00:00
|
|
|
bool has_ipg_clk_name;
|
2014-05-27 08:24:24 +00:00
|
|
|
unsigned int fifo_depth;
|
2017-09-14 03:07:09 +00:00
|
|
|
unsigned int slot_width;
|
|
|
|
unsigned int slots;
|
2017-12-18 02:52:08 +00:00
|
|
|
struct fsl_ssi_regvals regvals[2];
|
2014-05-27 08:24:24 +00:00
|
|
|
|
2012-03-29 02:53:41 +00:00
|
|
|
struct clk *clk;
|
2014-05-27 08:24:24 +00:00
|
|
|
struct clk *baudclk;
|
2014-05-27 08:24:23 +00:00
|
|
|
unsigned int baudclk_streams;
|
2014-05-27 08:24:24 +00:00
|
|
|
|
2015-09-18 03:09:12 +00:00
|
|
|
u32 regcache_sfcsr;
|
2015-12-20 20:30:25 +00:00
|
|
|
u32 regcache_sacnt;
|
2015-09-18 03:09:12 +00:00
|
|
|
|
2013-04-03 09:06:04 +00:00
|
|
|
struct snd_dmaengine_dai_dma_data dma_params_tx;
|
|
|
|
struct snd_dmaengine_dai_dma_data dma_params_rx;
|
2014-05-27 08:24:24 +00:00
|
|
|
dma_addr_t ssi_phys;
|
|
|
|
|
2013-07-27 11:31:53 +00:00
|
|
|
struct imx_pcm_fiq_params fiq_params;
|
2014-05-27 08:24:24 +00:00
|
|
|
|
2018-02-12 22:03:24 +00:00
|
|
|
struct platform_device *card_pdev;
|
|
|
|
char card_name[32];
|
|
|
|
u32 card_idx;
|
2012-03-16 08:56:43 +00:00
|
|
|
|
2014-04-28 10:54:43 +00:00
|
|
|
struct fsl_ssi_dbg dbg_stats;
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2014-05-27 08:24:18 +00:00
|
|
|
const struct fsl_ssi_soc_data *soc;
|
2016-05-03 12:13:57 +00:00
|
|
|
struct device *dev;
|
2017-01-03 18:22:57 +00:00
|
|
|
|
|
|
|
u32 fifo_watermark;
|
|
|
|
u32 dma_maxburst;
|
2017-11-20 22:16:07 +00:00
|
|
|
|
|
|
|
struct mutex ac97_reg_lock;
|
2022-05-10 11:56:48 +00:00
|
|
|
struct sdma_peripheral_config audio_config[2];
|
2013-12-20 13:11:30 +00:00
|
|
|
};
|
2014-04-28 10:54:48 +00:00
|
|
|
|
|
|
|
/*
|
2017-12-18 02:52:02 +00:00
|
|
|
* SoC specific data
|
2014-04-28 10:54:48 +00:00
|
|
|
*
|
2017-12-18 02:52:02 +00:00
|
|
|
* Notes:
|
|
|
|
* 1) SSI in earlier SoCS has critical bits in control registers that
|
|
|
|
* cannot be changed after SSI starts running -- a software reset
|
|
|
|
* (set SSIEN to 0) is required to change their values. So adding
|
|
|
|
* an offline_config flag for these SoCs.
|
|
|
|
* 2) SDMA is available since imx35. However, imx35 does not support
|
|
|
|
* DMA bits changing when SSI is running, so set offline_config.
|
|
|
|
* 3) imx51 and later versions support register configurations when
|
|
|
|
* SSI is running (SSIEN); For these versions, DMA needs to be
|
|
|
|
* configured before SSI sends DMA request to avoid an undefined
|
|
|
|
* DMA request on the SDMA side.
|
2014-04-28 10:54:48 +00:00
|
|
|
*/
|
|
|
|
|
2014-05-27 08:24:18 +00:00
|
|
|
static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
|
|
|
|
.imx = false,
|
|
|
|
.offline_config = true,
|
2017-12-18 02:52:03 +00:00
|
|
|
.sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
|
2017-12-18 02:52:04 +00:00
|
|
|
SSI_SISR_ROE0 | SSI_SISR_ROE1 |
|
|
|
|
SSI_SISR_TUE0 | SSI_SISR_TUE1,
|
2014-05-27 08:24:18 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
|
|
|
|
.imx = true,
|
2016-01-18 19:07:44 +00:00
|
|
|
.imx21regs = true,
|
2014-05-27 08:24:18 +00:00
|
|
|
.offline_config = true,
|
|
|
|
.sisr_write_mask = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
|
|
|
|
.imx = true,
|
|
|
|
.offline_config = true,
|
2017-12-18 02:52:03 +00:00
|
|
|
.sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
|
2017-12-18 02:52:04 +00:00
|
|
|
SSI_SISR_ROE0 | SSI_SISR_ROE1 |
|
|
|
|
SSI_SISR_TUE0 | SSI_SISR_TUE1,
|
2014-05-27 08:24:18 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
|
|
|
|
.imx = true,
|
|
|
|
.offline_config = false,
|
2017-12-18 02:52:03 +00:00
|
|
|
.sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
|
2017-12-18 02:52:04 +00:00
|
|
|
SSI_SISR_TUE0 | SSI_SISR_TUE1,
|
2014-05-27 08:24:18 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct of_device_id fsl_ssi_ids[] = {
|
|
|
|
{ .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
|
|
|
|
{ .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
|
|
|
|
{ .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
|
|
|
|
{ .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi)
|
2014-05-27 08:24:18 +00:00
|
|
|
{
|
2017-12-18 02:52:00 +00:00
|
|
|
return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
|
2015-09-16 09:13:19 +00:00
|
|
|
SND_SOC_DAIFMT_AC97;
|
2014-04-28 10:54:48 +00:00
|
|
|
}
|
|
|
|
|
2021-09-21 21:35:33 +00:00
|
|
|
static bool fsl_ssi_is_i2s_clock_provider(struct fsl_ssi *ssi)
|
2014-05-27 08:24:20 +00:00
|
|
|
{
|
2021-09-21 21:35:33 +00:00
|
|
|
return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
|
2022-05-19 15:42:30 +00:00
|
|
|
SND_SOC_DAIFMT_BP_FP;
|
2014-05-27 08:24:20 +00:00
|
|
|
}
|
|
|
|
|
2022-05-19 15:42:30 +00:00
|
|
|
static bool fsl_ssi_is_i2s_bc_fp(struct fsl_ssi *ssi)
|
2014-08-04 15:08:07 +00:00
|
|
|
{
|
2021-09-21 21:35:33 +00:00
|
|
|
return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
|
2022-05-19 15:42:30 +00:00
|
|
|
SND_SOC_DAIFMT_BC_FP;
|
2014-08-04 15:08:07 +00:00
|
|
|
}
|
2017-12-18 02:52:02 +00:00
|
|
|
|
2008-01-11 17:15:26 +00:00
|
|
|
/**
|
2021-03-02 20:59:23 +00:00
|
|
|
* fsl_ssi_isr - Interrupt handler to gather states
|
2020-07-02 19:21:37 +00:00
|
|
|
* @irq: irq number
|
|
|
|
* @dev_id: context
|
2008-01-11 17:15:26 +00:00
|
|
|
*/
|
|
|
|
static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
|
|
|
|
{
|
2017-12-18 02:52:00 +00:00
|
|
|
struct fsl_ssi *ssi = dev_id;
|
|
|
|
struct regmap *regs = ssi->regs;
|
2018-04-25 22:53:52 +00:00
|
|
|
u32 sisr, sisr2;
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_read(regs, REG_SSI_SISR, &sisr);
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
sisr2 = sisr & ssi->soc->sisr_write_mask;
|
2008-01-11 17:15:26 +00:00
|
|
|
/* Clear the bits that we set */
|
|
|
|
if (sisr2)
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_write(regs, REG_SSI_SISR, sisr2);
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
|
2013-12-20 13:11:29 +00:00
|
|
|
|
2014-04-28 10:54:43 +00:00
|
|
|
return IRQ_HANDLED;
|
2013-12-20 13:11:29 +00:00
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/**
|
2020-07-02 19:21:37 +00:00
|
|
|
* fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with
|
|
|
|
* cached values in regvals
|
|
|
|
* @ssi: SSI context
|
|
|
|
* @tx: direction
|
2018-02-12 22:03:15 +00:00
|
|
|
*
|
|
|
|
* Notes:
|
|
|
|
* 1) For offline_config SoCs, enable all necessary bits of both streams
|
|
|
|
* when 1st stream starts, even if the opposite stream will not start
|
|
|
|
* 2) It also clears FIFO before setting regvals; SOR is safe to set online
|
2013-12-20 13:11:33 +00:00
|
|
|
*/
|
2018-02-12 22:03:15 +00:00
|
|
|
static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx)
|
2013-12-20 13:11:33 +00:00
|
|
|
{
|
2017-12-18 02:52:08 +00:00
|
|
|
struct fsl_ssi_regvals *vals = ssi->regvals;
|
2018-02-12 22:03:15 +00:00
|
|
|
int dir = tx ? TX : RX;
|
|
|
|
u32 sier, srcr, stcr;
|
2013-12-20 13:11:33 +00:00
|
|
|
|
2018-02-12 22:03:15 +00:00
|
|
|
/* Clear dirty data in the FIFO; It also prevents channel slipping */
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SOR,
|
|
|
|
SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On offline_config SoCs, SxCR and SIER are already configured when
|
|
|
|
* the previous stream started. So skip all SxCR and SIER settings
|
|
|
|
* to prevent online reconfigurations, then jump to set SCR directly
|
|
|
|
*/
|
|
|
|
if (ssi->soc->offline_config && ssi->streams)
|
|
|
|
goto enable_scr;
|
|
|
|
|
|
|
|
if (ssi->soc->offline_config) {
|
|
|
|
/*
|
|
|
|
* Online reconfiguration not supported, so enable all bits for
|
|
|
|
* both streams at once to avoid necessity of reconfigurations
|
|
|
|
*/
|
|
|
|
srcr = vals[RX].srcr | vals[TX].srcr;
|
|
|
|
stcr = vals[RX].stcr | vals[TX].stcr;
|
|
|
|
sier = vals[RX].sier | vals[TX].sier;
|
2013-12-20 13:11:33 +00:00
|
|
|
} else {
|
2018-02-12 22:03:15 +00:00
|
|
|
/* Otherwise, only set bits for the current stream */
|
|
|
|
srcr = vals[dir].srcr;
|
|
|
|
stcr = vals[dir].stcr;
|
|
|
|
sier = vals[dir].sier;
|
2013-12-20 13:11:33 +00:00
|
|
|
}
|
2018-02-12 22:03:15 +00:00
|
|
|
|
|
|
|
/* Configure SRCR, STCR and SIER at once */
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr);
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr);
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier);
|
|
|
|
|
|
|
|
enable_scr:
|
|
|
|
/*
|
|
|
|
* Start DMA before setting TE to avoid FIFO underrun
|
|
|
|
* which may cause a channel slip or a channel swap
|
|
|
|
*
|
|
|
|
* TODO: FIQ cases might also need this upon testing
|
|
|
|
*/
|
|
|
|
if (ssi->use_dma && tx) {
|
|
|
|
int try = 100;
|
|
|
|
u32 sfcsr;
|
|
|
|
|
|
|
|
/* Enable SSI first to send TX DMA request */
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SCR,
|
|
|
|
SSI_SCR_SSIEN, SSI_SCR_SSIEN);
|
|
|
|
|
|
|
|
/* Busy wait until TX FIFO not empty -- DMA working */
|
|
|
|
do {
|
|
|
|
regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr);
|
|
|
|
if (SSI_SFCSR_TFCNT0(sfcsr))
|
|
|
|
break;
|
|
|
|
} while (--try);
|
|
|
|
|
|
|
|
/* FIFO still empty -- something might be wrong */
|
|
|
|
if (!SSI_SFCSR_TFCNT0(sfcsr))
|
|
|
|
dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
|
|
|
|
}
|
|
|
|
/* Enable all remaining bits in SCR */
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SCR,
|
|
|
|
vals[dir].scr, vals[dir].scr);
|
|
|
|
|
|
|
|
/* Log the enabled stream to the mask */
|
|
|
|
ssi->streams |= BIT(dir);
|
2013-12-20 13:11:33 +00:00
|
|
|
}
|
|
|
|
|
2020-07-02 19:21:37 +00:00
|
|
|
/*
|
2018-02-12 22:03:13 +00:00
|
|
|
* Exclude bits that are used by the opposite stream
|
2014-04-28 10:54:42 +00:00
|
|
|
*
|
2018-02-12 22:03:13 +00:00
|
|
|
* When both streams are active, disabling some bits for the current stream
|
|
|
|
* might break the other stream if these bits are used by it.
|
2014-04-28 10:54:42 +00:00
|
|
|
*
|
2018-02-12 22:03:13 +00:00
|
|
|
* @vals : regvals of the current stream
|
|
|
|
* @avals: regvals of the opposite stream
|
|
|
|
* @aactive: active state of the opposite stream
|
2014-04-28 10:54:42 +00:00
|
|
|
*
|
2018-02-12 22:03:13 +00:00
|
|
|
* 1) XOR vals and avals to get the differences if the other stream is active;
|
|
|
|
* Otherwise, return current vals if the other stream is not active
|
|
|
|
* 2) AND the result of 1) with the current vals
|
2014-04-28 10:54:42 +00:00
|
|
|
*/
|
2018-02-12 22:03:13 +00:00
|
|
|
#define _ssi_xor_shared_bits(vals, avals, aactive) \
|
|
|
|
((vals) ^ ((avals) * (aactive)))
|
|
|
|
|
|
|
|
#define ssi_excl_shared_bits(vals, avals, aactive) \
|
|
|
|
((vals) & _ssi_xor_shared_bits(vals, avals, aactive))
|
2014-04-28 10:54:42 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/**
|
2020-07-02 19:21:37 +00:00
|
|
|
* fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers
|
|
|
|
* with cached values in regvals
|
|
|
|
* @ssi: SSI context
|
|
|
|
* @tx: direction
|
2018-02-12 22:03:15 +00:00
|
|
|
*
|
|
|
|
* Notes:
|
|
|
|
* 1) For offline_config SoCs, to avoid online reconfigurations, disable all
|
|
|
|
* bits of both streams at once when the last stream is abort to end
|
|
|
|
* 2) It also clears FIFO after unsetting regvals; SOR is safe to set online
|
2013-12-20 13:11:33 +00:00
|
|
|
*/
|
2018-02-12 22:03:15 +00:00
|
|
|
static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx)
|
2013-12-20 13:11:33 +00:00
|
|
|
{
|
2018-02-12 22:03:15 +00:00
|
|
|
struct fsl_ssi_regvals *vals, *avals;
|
|
|
|
u32 sier, srcr, stcr, scr;
|
2018-02-12 22:03:14 +00:00
|
|
|
int adir = tx ? RX : TX;
|
|
|
|
int dir = tx ? TX : RX;
|
2018-02-12 22:03:13 +00:00
|
|
|
bool aactive;
|
2014-05-27 08:24:25 +00:00
|
|
|
|
2018-02-12 22:03:13 +00:00
|
|
|
/* Check if the opposite stream is active */
|
|
|
|
aactive = ssi->streams & BIT(adir);
|
2013-12-20 13:11:33 +00:00
|
|
|
|
2018-02-12 22:03:15 +00:00
|
|
|
vals = &ssi->regvals[dir];
|
2018-02-12 22:03:12 +00:00
|
|
|
|
2018-02-12 22:03:15 +00:00
|
|
|
/* Get regvals of the opposite stream to keep opposite stream safe */
|
|
|
|
avals = &ssi->regvals[adir];
|
2013-12-20 13:11:33 +00:00
|
|
|
|
|
|
|
/*
|
2018-02-12 22:03:15 +00:00
|
|
|
* To keep the other stream safe, exclude shared bits between
|
|
|
|
* both streams, and get safe bits to disable current stream
|
2013-12-20 13:11:33 +00:00
|
|
|
*/
|
2018-02-12 22:03:15 +00:00
|
|
|
scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive);
|
2013-12-20 13:11:33 +00:00
|
|
|
|
2018-02-12 22:03:15 +00:00
|
|
|
/* Disable safe bits of SCR register for the current stream */
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0);
|
2013-12-20 13:11:33 +00:00
|
|
|
|
2018-02-12 22:03:15 +00:00
|
|
|
/* Log the disabled stream to the mask */
|
|
|
|
ssi->streams &= ~BIT(dir);
|
2016-05-03 12:14:00 +00:00
|
|
|
|
2018-02-12 22:03:15 +00:00
|
|
|
/*
|
|
|
|
* On offline_config SoCs, if the other stream is active, skip
|
|
|
|
* SxCR and SIER settings to prevent online reconfigurations
|
|
|
|
*/
|
|
|
|
if (ssi->soc->offline_config && aactive)
|
|
|
|
goto fifo_clear;
|
2013-12-20 13:11:33 +00:00
|
|
|
|
2018-02-12 22:03:15 +00:00
|
|
|
if (ssi->soc->offline_config) {
|
|
|
|
/* Now there is only current stream active, disable all bits */
|
|
|
|
srcr = vals->srcr | avals->srcr;
|
|
|
|
stcr = vals->stcr | avals->stcr;
|
|
|
|
sier = vals->sier | avals->sier;
|
|
|
|
} else {
|
2013-12-20 13:11:33 +00:00
|
|
|
/*
|
2017-12-18 02:52:02 +00:00
|
|
|
* To keep the other stream safe, exclude shared bits between
|
|
|
|
* both streams, and get safe bits to disable current stream
|
2013-12-20 13:11:33 +00:00
|
|
|
*/
|
2018-02-12 22:03:13 +00:00
|
|
|
sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive);
|
|
|
|
srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive);
|
|
|
|
stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive);
|
2013-12-20 13:11:33 +00:00
|
|
|
}
|
|
|
|
|
2018-02-12 22:03:15 +00:00
|
|
|
/* Clear configurations of SRCR, STCR and SIER at once */
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0);
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0);
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0);
|
2013-12-20 13:11:33 +00:00
|
|
|
|
2018-02-12 22:03:15 +00:00
|
|
|
fifo_clear:
|
|
|
|
/* Clear remaining data in the FIFO */
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SOR,
|
|
|
|
SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
|
2013-12-20 13:11:33 +00:00
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
|
2017-11-21 23:54:26 +00:00
|
|
|
{
|
2017-12-18 02:52:00 +00:00
|
|
|
struct regmap *regs = ssi->regs;
|
2017-11-21 23:54:26 +00:00
|
|
|
|
|
|
|
/* no SACC{ST,EN,DIS} regs on imx21-class SSI */
|
2017-12-18 02:52:00 +00:00
|
|
|
if (!ssi->soc->imx21regs) {
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Disable all channel slots */
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_write(regs, REG_SSI_SACCDIS, 0xff);
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Enable slots 3 & 4 -- PCM Playback Left & Right channels */
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_write(regs, REG_SSI_SACCEN, 0x300);
|
2017-11-21 23:54:26 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/**
|
2020-07-02 19:21:37 +00:00
|
|
|
* fsl_ssi_setup_regvals - Cache critical bits of SIER, SRCR, STCR and
|
|
|
|
* SCR to later set them safely
|
|
|
|
* @ssi: SSI context
|
2013-12-20 13:11:34 +00:00
|
|
|
*/
|
2017-12-18 02:52:08 +00:00
|
|
|
static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
|
2013-12-20 13:11:34 +00:00
|
|
|
{
|
2017-12-18 02:52:08 +00:00
|
|
|
struct fsl_ssi_regvals *vals = ssi->regvals;
|
2013-12-20 13:11:34 +00:00
|
|
|
|
2018-02-12 22:03:17 +00:00
|
|
|
vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
|
2017-12-18 02:52:08 +00:00
|
|
|
vals[RX].srcr = SSI_SRCR_RFEN0;
|
2018-02-12 22:03:17 +00:00
|
|
|
vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
|
|
|
|
vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
|
2017-12-18 02:52:08 +00:00
|
|
|
vals[TX].stcr = SSI_STCR_TFEN0;
|
2018-02-12 22:03:17 +00:00
|
|
|
vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
|
2013-12-20 13:11:34 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* AC97 has already enabled SSIEN, RE and TE, so ignore them */
|
2018-02-12 22:03:17 +00:00
|
|
|
if (fsl_ssi_is_ac97(ssi))
|
|
|
|
vals[RX].scr = vals[TX].scr = 0;
|
2013-12-20 13:11:34 +00:00
|
|
|
|
2018-02-12 22:03:18 +00:00
|
|
|
if (ssi->use_dual_fifo) {
|
|
|
|
vals[RX].srcr |= SSI_SRCR_RFEN1;
|
|
|
|
vals[TX].stcr |= SSI_STCR_TFEN1;
|
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (ssi->use_dma) {
|
2017-12-18 02:52:08 +00:00
|
|
|
vals[RX].sier |= SSI_SIER_RDMAE;
|
|
|
|
vals[TX].sier |= SSI_SIER_TDMAE;
|
2013-12-20 13:11:34 +00:00
|
|
|
} else {
|
2017-12-18 02:52:08 +00:00
|
|
|
vals[RX].sier |= SSI_SIER_RIE;
|
|
|
|
vals[TX].sier |= SSI_SIER_TIE;
|
2013-12-20 13:11:34 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
|
2013-11-20 09:04:15 +00:00
|
|
|
{
|
2017-12-18 02:52:00 +00:00
|
|
|
struct regmap *regs = ssi->regs;
|
2013-11-20 09:04:15 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Setup the clock control register */
|
2017-12-18 02:52:04 +00:00
|
|
|
regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
|
|
|
|
regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
|
2013-11-20 09:04:15 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Enable AC97 mode and startup the SSI */
|
2017-12-18 02:52:04 +00:00
|
|
|
regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);
|
2016-01-18 19:07:44 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* AC97 has to communicate with codec before starting a stream */
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_update_bits(regs, REG_SSI_SCR,
|
2017-12-18 02:52:04 +00:00
|
|
|
SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
|
|
|
|
SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
|
2013-11-20 09:04:15 +00:00
|
|
|
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
|
2013-11-20 09:04:15 +00:00
|
|
|
}
|
|
|
|
|
2008-11-18 22:11:38 +00:00
|
|
|
static int fsl_ssi_startup(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
2008-01-11 17:15:26 +00:00
|
|
|
{
|
2020-07-20 01:18:38 +00:00
|
|
|
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
|
2020-03-23 05:18:30 +00:00
|
|
|
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
|
2014-09-16 02:13:16 +00:00
|
|
|
int ret;
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
ret = clk_prepare_enable(ssi->clk);
|
2014-09-16 02:13:16 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/*
|
|
|
|
* When using dual fifo mode, it is safer to ensure an even period
|
2013-11-13 14:55:26 +00:00
|
|
|
* size. If appearing to an odd number while DMA always starts its
|
|
|
|
* task from fifo0, fifo1 would be neglected at the end of each
|
|
|
|
* period. But SSI would still access fifo1 with an invalid data.
|
|
|
|
*/
|
2022-05-10 11:56:48 +00:00
|
|
|
if (ssi->use_dual_fifo || ssi->use_dyna_fifo)
|
2013-11-13 14:55:26 +00:00
|
|
|
snd_pcm_hw_constraint_step(substream->runtime, 0,
|
2017-12-18 02:52:04 +00:00
|
|
|
SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
|
2013-11-13 14:55:26 +00:00
|
|
|
|
2008-01-11 17:15:26 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-09-16 02:13:16 +00:00
|
|
|
static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
|
2017-12-18 02:52:04 +00:00
|
|
|
struct snd_soc_dai *dai)
|
2014-09-16 02:13:16 +00:00
|
|
|
{
|
2020-07-20 01:18:38 +00:00
|
|
|
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
|
2020-03-23 05:18:30 +00:00
|
|
|
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
|
2014-09-16 02:13:16 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
clk_disable_unprepare(ssi->clk);
|
2014-09-16 02:13:16 +00:00
|
|
|
}
|
|
|
|
|
2014-04-28 10:54:52 +00:00
|
|
|
/**
|
2020-07-02 19:21:37 +00:00
|
|
|
* fsl_ssi_set_bclk - Configure Digital Audio Interface bit clock
|
|
|
|
* @substream: ASoC substream
|
|
|
|
* @dai: pointer to DAI
|
|
|
|
* @hw_params: pointers to hw_params
|
2014-04-28 10:54:52 +00:00
|
|
|
*
|
2020-07-02 19:21:37 +00:00
|
|
|
* Notes: This function can be only called when using SSI as DAI master
|
2014-04-28 10:54:52 +00:00
|
|
|
*
|
|
|
|
* Quick instruction for parameters:
|
2017-09-14 03:07:09 +00:00
|
|
|
* freq: Output BCLK frequency = samplerate * slots * slot_width
|
|
|
|
* (In 2-channel I2S Master mode, slot_width is fixed 32)
|
2014-04-28 10:54:52 +00:00
|
|
|
*/
|
2014-05-27 08:24:20 +00:00
|
|
|
static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
|
2017-12-18 02:52:06 +00:00
|
|
|
struct snd_soc_dai *dai,
|
2017-12-18 02:52:04 +00:00
|
|
|
struct snd_pcm_hw_params *hw_params)
|
2014-04-28 10:54:52 +00:00
|
|
|
{
|
2017-12-18 02:52:10 +00:00
|
|
|
bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
2017-12-18 02:52:06 +00:00
|
|
|
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
|
2017-12-18 02:52:00 +00:00
|
|
|
struct regmap *regs = ssi->regs;
|
2014-04-28 10:54:52 +00:00
|
|
|
u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
|
2014-05-27 08:24:21 +00:00
|
|
|
unsigned long clkrate, baudrate, tmprate;
|
2020-06-16 02:53:48 +00:00
|
|
|
unsigned int channels = params_channels(hw_params);
|
|
|
|
unsigned int slot_width = params_width(hw_params);
|
|
|
|
unsigned int slots = 2;
|
2014-04-28 10:54:52 +00:00
|
|
|
u64 sub, savesub = 100000;
|
2014-05-27 08:24:20 +00:00
|
|
|
unsigned int freq;
|
2014-05-27 08:24:23 +00:00
|
|
|
bool baudclk_is_used;
|
2018-02-12 22:03:23 +00:00
|
|
|
int ret;
|
2014-05-27 08:24:20 +00:00
|
|
|
|
2017-09-14 03:07:09 +00:00
|
|
|
/* Override slots and slot_width if being specifically set... */
|
2017-12-18 02:52:00 +00:00
|
|
|
if (ssi->slots)
|
|
|
|
slots = ssi->slots;
|
2020-06-16 02:53:48 +00:00
|
|
|
if (ssi->slot_width)
|
2017-12-18 02:52:00 +00:00
|
|
|
slot_width = ssi->slot_width;
|
2017-09-14 03:07:09 +00:00
|
|
|
|
2020-06-16 02:53:48 +00:00
|
|
|
/* ...but force 32 bits for stereo audio using I2S Master Mode */
|
|
|
|
if (channels == 2 &&
|
|
|
|
(ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER)
|
|
|
|
slot_width = 32;
|
|
|
|
|
2017-09-14 03:07:09 +00:00
|
|
|
/* Generate bit clock based on the slot number and slot width */
|
|
|
|
freq = slots * slot_width * params_rate(hw_params);
|
2014-04-28 10:54:52 +00:00
|
|
|
|
|
|
|
/* Don't apply it to any non-baudclk circumstance */
|
2017-12-18 02:52:00 +00:00
|
|
|
if (IS_ERR(ssi->baudclk))
|
2014-04-28 10:54:52 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
2016-05-03 12:13:56 +00:00
|
|
|
/*
|
|
|
|
* Hardware limitation: The bclk rate must be
|
|
|
|
* never greater than 1/5 IPG clock rate
|
|
|
|
*/
|
2017-12-18 02:52:00 +00:00
|
|
|
if (freq * 5 > clk_get_rate(ssi->clk)) {
|
2017-12-18 02:52:06 +00:00
|
|
|
dev_err(dai->dev, "bitclk > ipgclk / 5\n");
|
2016-05-03 12:13:56 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream));
|
2014-05-27 08:24:23 +00:00
|
|
|
|
2014-04-28 10:54:52 +00:00
|
|
|
/* It should be already enough to divide clock by setting pm alone */
|
|
|
|
psr = 0;
|
|
|
|
div2 = 0;
|
|
|
|
|
|
|
|
factor = (div2 + 1) * (7 * psr + 1) * 2;
|
|
|
|
|
|
|
|
for (i = 0; i < 255; i++) {
|
2015-03-05 05:05:04 +00:00
|
|
|
tmprate = freq * factor * (i + 1);
|
2014-05-27 08:24:23 +00:00
|
|
|
|
|
|
|
if (baudclk_is_used)
|
2017-12-18 02:52:00 +00:00
|
|
|
clkrate = clk_get_rate(ssi->baudclk);
|
2014-05-27 08:24:23 +00:00
|
|
|
else
|
2017-12-18 02:52:00 +00:00
|
|
|
clkrate = clk_round_rate(ssi->baudclk, tmprate);
|
2014-04-28 10:54:52 +00:00
|
|
|
|
2014-06-13 12:42:40 +00:00
|
|
|
clkrate /= factor;
|
|
|
|
afreq = clkrate / (i + 1);
|
2014-04-28 10:54:52 +00:00
|
|
|
|
|
|
|
if (freq == afreq)
|
|
|
|
sub = 0;
|
|
|
|
else if (freq / afreq == 1)
|
|
|
|
sub = freq - afreq;
|
|
|
|
else if (afreq / freq == 1)
|
|
|
|
sub = afreq - freq;
|
|
|
|
else
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Calculate the fraction */
|
|
|
|
sub *= 100000;
|
|
|
|
do_div(sub, freq);
|
|
|
|
|
2021-02-19 23:29:33 +00:00
|
|
|
if (sub < savesub && !(i == 0)) {
|
2014-04-28 10:54:52 +00:00
|
|
|
baudrate = tmprate;
|
|
|
|
savesub = sub;
|
|
|
|
pm = i;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We are lucky */
|
|
|
|
if (savesub == 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* No proper pm found if it is still remaining the initial value */
|
|
|
|
if (pm == 999) {
|
2017-12-18 02:52:06 +00:00
|
|
|
dev_err(dai->dev, "failed to handle the required sysclk\n");
|
2014-04-28 10:54:52 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2021-02-19 23:29:33 +00:00
|
|
|
stccr = SSI_SxCCR_PM(pm + 1);
|
2017-12-18 02:52:04 +00:00
|
|
|
mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
|
2014-04-28 10:54:52 +00:00
|
|
|
|
2017-12-18 02:52:10 +00:00
|
|
|
/* STCCR is used for RX in synchronous mode */
|
2018-02-12 22:03:23 +00:00
|
|
|
tx2 = tx || ssi->synchronous;
|
2017-12-18 02:52:10 +00:00
|
|
|
regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr);
|
2014-04-28 10:54:52 +00:00
|
|
|
|
2014-05-27 08:24:23 +00:00
|
|
|
if (!baudclk_is_used) {
|
2017-12-18 02:52:00 +00:00
|
|
|
ret = clk_set_rate(ssi->baudclk, baudrate);
|
2014-04-28 10:54:52 +00:00
|
|
|
if (ret) {
|
2017-12-18 02:52:06 +00:00
|
|
|
dev_err(dai->dev, "failed to set baudclk rate\n");
|
2014-04-28 10:54:52 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-01-11 17:15:26 +00:00
|
|
|
/**
|
2020-07-02 19:21:37 +00:00
|
|
|
* fsl_ssi_hw_params - Configure SSI based on PCM hardware parameters
|
|
|
|
* @substream: ASoC substream
|
|
|
|
* @hw_params: pointers to hw_params
|
|
|
|
* @dai: pointer to DAI
|
2008-01-11 17:15:26 +00:00
|
|
|
*
|
2017-12-18 02:52:02 +00:00
|
|
|
* Notes:
|
|
|
|
* 1) SxCCR.WL bits are critical bits that require SSI to be temporarily
|
|
|
|
* disabled on offline_config SoCs. Even for online configurable SoCs
|
|
|
|
* running in synchronous mode (both TX and RX use STCCR), it is not
|
|
|
|
* safe to re-configure them when both two streams start running.
|
|
|
|
* 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the
|
|
|
|
* fsl_ssi_set_bclk() if SSI is the DAI clock master.
|
2008-01-11 17:15:26 +00:00
|
|
|
*/
|
2009-02-05 23:56:02 +00:00
|
|
|
static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
|
2017-12-18 02:52:04 +00:00
|
|
|
struct snd_pcm_hw_params *hw_params,
|
2017-12-18 02:52:06 +00:00
|
|
|
struct snd_soc_dai *dai)
|
2008-01-11 17:15:26 +00:00
|
|
|
{
|
2017-12-18 02:52:10 +00:00
|
|
|
bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
2017-12-18 02:52:06 +00:00
|
|
|
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
|
2022-05-10 11:56:48 +00:00
|
|
|
struct fsl_ssi_regvals *vals = ssi->regvals;
|
2017-12-18 02:52:00 +00:00
|
|
|
struct regmap *regs = ssi->regs;
|
2013-12-02 15:29:03 +00:00
|
|
|
unsigned int channels = params_channels(hw_params);
|
2015-11-24 07:32:09 +00:00
|
|
|
unsigned int sample_size = params_width(hw_params);
|
2017-12-18 02:52:03 +00:00
|
|
|
u32 wl = SSI_SxCCR_WL(sample_size);
|
2014-05-27 08:24:20 +00:00
|
|
|
int ret;
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2021-09-21 21:35:33 +00:00
|
|
|
if (fsl_ssi_is_i2s_clock_provider(ssi)) {
|
2017-12-18 02:52:06 +00:00
|
|
|
ret = fsl_ssi_set_bclk(substream, dai, hw_params);
|
2014-05-27 08:24:20 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-05-27 08:24:23 +00:00
|
|
|
|
|
|
|
/* Do not enable the clock if it is already enabled */
|
2017-12-18 02:52:00 +00:00
|
|
|
if (!(ssi->baudclk_streams & BIT(substream->stream))) {
|
|
|
|
ret = clk_prepare_enable(ssi->baudclk);
|
2014-05-27 08:24:23 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->baudclk_streams |= BIT(substream->stream);
|
2014-05-27 08:24:23 +00:00
|
|
|
}
|
2014-05-27 08:24:20 +00:00
|
|
|
}
|
|
|
|
|
2019-08-28 17:20:17 +00:00
|
|
|
/*
|
|
|
|
* SSI is properly configured if it is enabled and running in
|
|
|
|
* the synchronous mode; Note that AC97 mode is an exception
|
|
|
|
* that should set separate configurations for STCCR and SRCCR
|
|
|
|
* despite running in the synchronous mode.
|
|
|
|
*/
|
|
|
|
if (ssi->streams && ssi->synchronous)
|
|
|
|
return 0;
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (!fsl_ssi_is_ac97(ssi)) {
|
2018-04-08 04:40:21 +00:00
|
|
|
/*
|
|
|
|
* Keep the ssi->i2s_net intact while having a local variable
|
|
|
|
* to override settings for special use cases. Otherwise, the
|
|
|
|
* ssi->i2s_net will lose the settings for regular use cases.
|
|
|
|
*/
|
|
|
|
u8 i2s_net = ssi->i2s_net;
|
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Normal + Network mode to send 16-bit data in 32-bit frames */
|
2022-05-19 15:42:30 +00:00
|
|
|
if (fsl_ssi_is_i2s_bc_fp(ssi) && sample_size == 16)
|
2018-04-08 04:40:21 +00:00
|
|
|
i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
|
2018-02-12 22:03:10 +00:00
|
|
|
|
|
|
|
/* Use Normal mode to send mono data at 1st slot of 2 slots */
|
|
|
|
if (channels == 1)
|
2018-04-08 04:40:21 +00:00
|
|
|
i2s_net = SSI_SCR_I2S_MODE_NORMAL;
|
2014-08-04 15:08:07 +00:00
|
|
|
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_update_bits(regs, REG_SSI_SCR,
|
2018-04-08 04:40:21 +00:00
|
|
|
SSI_SCR_I2S_NET_MASK, i2s_net);
|
2014-08-04 15:08:07 +00:00
|
|
|
}
|
|
|
|
|
2011-09-13 17:59:37 +00:00
|
|
|
/* In synchronous mode, the SSI uses STCCR for capture */
|
2018-02-12 22:03:23 +00:00
|
|
|
tx2 = tx || ssi->synchronous;
|
2017-12-18 02:52:10 +00:00
|
|
|
regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2022-05-10 11:56:48 +00:00
|
|
|
if (ssi->use_dyna_fifo) {
|
|
|
|
if (channels == 1) {
|
|
|
|
ssi->audio_config[0].n_fifos_dst = 1;
|
|
|
|
ssi->audio_config[1].n_fifos_src = 1;
|
|
|
|
vals[RX].srcr &= ~SSI_SRCR_RFEN1;
|
|
|
|
vals[TX].stcr &= ~SSI_STCR_TFEN1;
|
|
|
|
vals[RX].scr &= ~SSI_SCR_TCH_EN;
|
|
|
|
vals[TX].scr &= ~SSI_SCR_TCH_EN;
|
|
|
|
} else {
|
|
|
|
ssi->audio_config[0].n_fifos_dst = 2;
|
|
|
|
ssi->audio_config[1].n_fifos_src = 2;
|
|
|
|
vals[RX].srcr |= SSI_SRCR_RFEN1;
|
|
|
|
vals[TX].stcr |= SSI_STCR_TFEN1;
|
|
|
|
vals[RX].scr |= SSI_SCR_TCH_EN;
|
|
|
|
vals[TX].scr |= SSI_SCR_TCH_EN;
|
|
|
|
}
|
|
|
|
ssi->dma_params_tx.peripheral_config = &ssi->audio_config[0];
|
|
|
|
ssi->dma_params_tx.peripheral_size = sizeof(ssi->audio_config[0]);
|
|
|
|
ssi->dma_params_rx.peripheral_config = &ssi->audio_config[1];
|
|
|
|
ssi->dma_params_rx.peripheral_size = sizeof(ssi->audio_config[1]);
|
|
|
|
}
|
|
|
|
|
2008-01-11 17:15:26 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-05-27 08:24:23 +00:00
|
|
|
static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
|
2017-12-18 02:52:06 +00:00
|
|
|
struct snd_soc_dai *dai)
|
2014-05-27 08:24:23 +00:00
|
|
|
{
|
2020-07-20 01:18:38 +00:00
|
|
|
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
|
2020-03-23 05:18:30 +00:00
|
|
|
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
|
2014-05-27 08:24:23 +00:00
|
|
|
|
2021-09-21 21:35:33 +00:00
|
|
|
if (fsl_ssi_is_i2s_clock_provider(ssi) &&
|
2017-12-18 02:52:04 +00:00
|
|
|
ssi->baudclk_streams & BIT(substream->stream)) {
|
2017-12-18 02:52:00 +00:00
|
|
|
clk_disable_unprepare(ssi->baudclk);
|
|
|
|
ssi->baudclk_streams &= ~BIT(substream->stream);
|
2014-05-27 08:24:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-02-12 22:03:22 +00:00
|
|
|
static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt)
|
2013-12-12 10:44:45 +00:00
|
|
|
{
|
2018-02-12 22:03:22 +00:00
|
|
|
u32 strcr = 0, scr = 0, stcr, srcr, mask;
|
2021-02-16 11:42:21 +00:00
|
|
|
unsigned int slots;
|
2014-03-15 12:44:09 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->dai_fmt = fmt;
|
2014-04-28 10:54:48 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Synchronize frame sync clock for TE to avoid data slipping */
|
2017-12-18 02:52:03 +00:00
|
|
|
scr |= SSI_SCR_SYNC_TX_FS;
|
2013-12-12 10:44:45 +00:00
|
|
|
|
2018-02-12 22:03:22 +00:00
|
|
|
/* Set to default shifting settings: LSB_ALIGNED */
|
|
|
|
strcr |= SSI_STCR_TXBIT0;
|
2013-12-12 10:44:45 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Use Network mode as default */
|
2017-12-18 02:52:09 +00:00
|
|
|
ssi->i2s_net = SSI_SCR_NET;
|
2013-12-12 10:44:45 +00:00
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_I2S:
|
2021-09-21 21:35:33 +00:00
|
|
|
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
|
2022-05-19 15:42:30 +00:00
|
|
|
case SND_SOC_DAIFMT_BP_FP:
|
2018-02-12 22:03:22 +00:00
|
|
|
if (IS_ERR(ssi->baudclk)) {
|
|
|
|
dev_err(ssi->dev,
|
|
|
|
"missing baudclk for master mode\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2020-08-23 22:36:59 +00:00
|
|
|
fallthrough;
|
2022-05-19 15:42:30 +00:00
|
|
|
case SND_SOC_DAIFMT_BC_FP:
|
2017-12-18 02:52:09 +00:00
|
|
|
ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER;
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
2022-05-19 15:42:30 +00:00
|
|
|
case SND_SOC_DAIFMT_BC_FC:
|
2017-12-18 02:52:09 +00:00
|
|
|
ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE;
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2021-02-16 11:42:21 +00:00
|
|
|
slots = ssi->slots ? : 2;
|
2018-02-12 22:03:22 +00:00
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_STCCR,
|
2021-02-16 11:42:21 +00:00
|
|
|
SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
|
2018-02-12 22:03:22 +00:00
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SRCCR,
|
2021-02-16 11:42:21 +00:00
|
|
|
SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
|
2018-02-12 22:03:22 +00:00
|
|
|
|
2013-12-12 10:44:45 +00:00
|
|
|
/* Data on rising edge of bclk, frame low, 1clk before data */
|
2018-02-12 22:03:22 +00:00
|
|
|
strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS;
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
|
|
/* Data on rising edge of bclk, frame high */
|
2018-02-12 22:03:22 +00:00
|
|
|
strcr |= SSI_STCR_TSCKP;
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
|
|
|
/* Data on rising edge of bclk, frame high, 1clk before data */
|
2018-02-12 22:03:22 +00:00
|
|
|
strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS;
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_DSP_B:
|
|
|
|
/* Data on rising edge of bclk, frame high */
|
2018-02-12 22:03:22 +00:00
|
|
|
strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP;
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
2014-03-15 12:44:09 +00:00
|
|
|
case SND_SOC_DAIFMT_AC97:
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Data on falling edge of bclk, frame high, 1clk before data */
|
2018-02-12 22:03:22 +00:00
|
|
|
strcr |= SSI_STCR_TEFS;
|
2014-03-15 12:44:09 +00:00
|
|
|
break;
|
2013-12-12 10:44:45 +00:00
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2018-02-12 22:03:22 +00:00
|
|
|
|
2017-12-18 02:52:09 +00:00
|
|
|
scr |= ssi->i2s_net;
|
2013-12-12 10:44:45 +00:00
|
|
|
|
|
|
|
/* DAI clock inversion */
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
|
|
/* Nothing to do for both normal cases */
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
|
|
/* Invert bit clock */
|
2017-12-18 02:52:03 +00:00
|
|
|
strcr ^= SSI_STCR_TSCKP;
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_NB_IF:
|
|
|
|
/* Invert frame clock */
|
2017-12-18 02:52:03 +00:00
|
|
|
strcr ^= SSI_STCR_TFSI;
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
|
|
/* Invert both clocks */
|
2017-12-18 02:52:03 +00:00
|
|
|
strcr ^= SSI_STCR_TSCKP;
|
|
|
|
strcr ^= SSI_STCR_TFSI;
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2021-09-21 21:35:33 +00:00
|
|
|
/* DAI clock provider masks */
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
|
2022-05-19 15:42:30 +00:00
|
|
|
case SND_SOC_DAIFMT_BP_FP:
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Output bit and frame sync clocks */
|
2017-12-18 02:52:03 +00:00
|
|
|
strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
|
|
|
|
scr |= SSI_SCR_SYS_CLK_EN;
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
2022-05-19 15:42:30 +00:00
|
|
|
case SND_SOC_DAIFMT_BC_FC:
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Input bit or frame sync clocks */
|
2013-12-12 10:44:45 +00:00
|
|
|
break;
|
2022-05-19 15:42:30 +00:00
|
|
|
case SND_SOC_DAIFMT_BC_FP:
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Input bit clock but output frame sync clock */
|
2017-12-18 02:52:03 +00:00
|
|
|
strcr |= SSI_STCR_TFDIR;
|
2014-08-04 15:08:07 +00:00
|
|
|
break;
|
2013-12-12 10:44:45 +00:00
|
|
|
default:
|
2018-02-12 22:03:16 +00:00
|
|
|
return -EINVAL;
|
2013-12-12 10:44:45 +00:00
|
|
|
}
|
|
|
|
|
2018-02-12 22:03:22 +00:00
|
|
|
stcr = strcr;
|
|
|
|
srcr = strcr;
|
2013-12-12 10:44:45 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */
|
2018-02-12 22:03:23 +00:00
|
|
|
if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) {
|
2017-12-18 02:52:03 +00:00
|
|
|
srcr &= ~SSI_SRCR_RXDIR;
|
|
|
|
scr |= SSI_SCR_SYN;
|
2013-12-12 10:44:45 +00:00
|
|
|
}
|
|
|
|
|
2018-02-12 22:03:22 +00:00
|
|
|
mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP |
|
|
|
|
SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
|
|
|
|
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr);
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr);
|
|
|
|
|
|
|
|
mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK |
|
|
|
|
SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN;
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr);
|
2013-12-12 10:44:45 +00:00
|
|
|
|
|
|
|
return 0;
|
2014-05-27 08:24:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2020-07-02 19:21:37 +00:00
|
|
|
* fsl_ssi_set_dai_fmt - Configure Digital Audio Interface (DAI) Format
|
|
|
|
* @dai: pointer to DAI
|
|
|
|
* @fmt: format mask
|
2014-05-27 08:24:19 +00:00
|
|
|
*/
|
2017-12-18 02:52:06 +00:00
|
|
|
static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
|
2014-05-27 08:24:19 +00:00
|
|
|
{
|
2017-12-18 02:52:06 +00:00
|
|
|
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
|
2014-05-27 08:24:19 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* AC97 configured DAIFMT earlier in the probe() */
|
2017-12-18 02:52:00 +00:00
|
|
|
if (fsl_ssi_is_ac97(ssi))
|
2017-11-21 23:55:14 +00:00
|
|
|
return 0;
|
|
|
|
|
2018-02-12 22:03:22 +00:00
|
|
|
return _fsl_ssi_set_dai_fmt(ssi, fmt);
|
2013-12-12 10:44:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2020-07-02 19:21:37 +00:00
|
|
|
* fsl_ssi_set_dai_tdm_slot - Set TDM slot number and slot width
|
|
|
|
* @dai: pointer to DAI
|
|
|
|
* @tx_mask: mask for TX
|
|
|
|
* @rx_mask: mask for RX
|
|
|
|
* @slots: number of slots
|
|
|
|
* @slot_width: number of bits per slot
|
2013-12-12 10:44:45 +00:00
|
|
|
*/
|
2017-12-18 02:52:06 +00:00
|
|
|
static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
|
2017-12-18 02:52:04 +00:00
|
|
|
u32 rx_mask, int slots, int slot_width)
|
2013-12-12 10:44:45 +00:00
|
|
|
{
|
2017-12-18 02:52:06 +00:00
|
|
|
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
|
2017-12-18 02:52:00 +00:00
|
|
|
struct regmap *regs = ssi->regs;
|
2013-12-12 10:44:45 +00:00
|
|
|
u32 val;
|
|
|
|
|
2017-09-14 03:07:09 +00:00
|
|
|
/* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */
|
|
|
|
if (slot_width & 1 || slot_width < 8 || slot_width > 24) {
|
2017-12-18 02:52:06 +00:00
|
|
|
dev_err(dai->dev, "invalid slot width: %d\n", slot_width);
|
2017-09-14 03:07:09 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-12-12 10:44:45 +00:00
|
|
|
/* The slot number should be >= 2 if using Network mode or I2S mode */
|
2018-02-12 22:03:11 +00:00
|
|
|
if (ssi->i2s_net && slots < 2) {
|
2017-12-18 02:52:06 +00:00
|
|
|
dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n");
|
2013-12-12 10:44:45 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:04 +00:00
|
|
|
regmap_update_bits(regs, REG_SSI_STCCR,
|
|
|
|
SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
|
|
|
|
regmap_update_bits(regs, REG_SSI_SRCCR,
|
|
|
|
SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
|
2013-12-12 10:44:45 +00:00
|
|
|
|
2018-02-12 22:03:11 +00:00
|
|
|
/* Save the SCR register value */
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_read(regs, REG_SSI_SCR, &val);
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Temporarily enable SSI to allow SxMSKs to be configurable */
|
2017-12-18 02:52:04 +00:00
|
|
|
regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);
|
2013-12-12 10:44:45 +00:00
|
|
|
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
|
|
|
|
regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
|
2013-12-12 10:44:45 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Restore the value of SSIEN bit */
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val);
|
2013-12-12 10:44:45 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->slot_width = slot_width;
|
|
|
|
ssi->slots = slots;
|
2017-09-14 03:07:09 +00:00
|
|
|
|
2013-12-12 10:44:45 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-01-11 17:15:26 +00:00
|
|
|
/**
|
2020-07-02 19:21:37 +00:00
|
|
|
* fsl_ssi_trigger - Start or stop SSI and corresponding DMA transaction.
|
|
|
|
* @substream: ASoC substream
|
|
|
|
* @cmd: trigger command
|
|
|
|
* @dai: pointer to DAI
|
2008-01-11 17:15:26 +00:00
|
|
|
*
|
|
|
|
* The DMA channel is in external master start and pause mode, which
|
|
|
|
* means the SSI completely controls the flow of data.
|
|
|
|
*/
|
2008-11-18 22:11:38 +00:00
|
|
|
static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
|
|
struct snd_soc_dai *dai)
|
2008-01-11 17:15:26 +00:00
|
|
|
{
|
2020-07-20 01:18:38 +00:00
|
|
|
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
|
2020-03-23 05:18:30 +00:00
|
|
|
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
|
2018-02-12 22:03:15 +00:00
|
|
|
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
2013-08-19 15:06:00 +00:00
|
|
|
|
2008-01-11 17:15:26 +00:00
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
2014-05-23 05:38:56 +00:00
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
2008-01-11 17:15:26 +00:00
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
2018-02-12 22:03:15 +00:00
|
|
|
/*
|
|
|
|
* SACCST might be modified via AC Link by a CODEC if it sends
|
|
|
|
* extra bits in their SLOTREQ requests, which'll accidentally
|
|
|
|
* send valid data to slots other than normal playback slots.
|
|
|
|
*
|
|
|
|
* To be safe, configure SACCST right before TX starts.
|
|
|
|
*/
|
|
|
|
if (tx && fsl_ssi_is_ac97(ssi))
|
|
|
|
fsl_ssi_tx_ac97_saccst_setup(ssi);
|
|
|
|
fsl_ssi_config_enable(ssi, tx);
|
2008-01-11 17:15:26 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
2014-05-23 05:38:56 +00:00
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
2008-01-11 17:15:26 +00:00
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
2018-02-12 22:03:15 +00:00
|
|
|
fsl_ssi_config_disable(ssi, tx);
|
2008-01-11 17:15:26 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-04-15 17:19:58 +00:00
|
|
|
static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
|
|
|
|
{
|
2017-12-18 02:52:00 +00:00
|
|
|
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
|
2013-04-15 17:19:58 +00:00
|
|
|
|
2018-02-12 22:03:19 +00:00
|
|
|
if (ssi->soc->imx && ssi->use_dma)
|
|
|
|
snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx,
|
|
|
|
&ssi->dma_params_rx);
|
2013-04-15 17:19:58 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-11-23 10:40:40 +00:00
|
|
|
static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
|
2017-12-18 02:52:04 +00:00
|
|
|
.startup = fsl_ssi_startup,
|
|
|
|
.shutdown = fsl_ssi_shutdown,
|
|
|
|
.hw_params = fsl_ssi_hw_params,
|
|
|
|
.hw_free = fsl_ssi_hw_free,
|
2022-05-19 15:42:57 +00:00
|
|
|
.set_fmt = fsl_ssi_set_dai_fmt,
|
2017-12-18 02:52:04 +00:00
|
|
|
.set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
|
|
|
|
.trigger = fsl_ssi_trigger,
|
2009-03-03 01:41:00 +00:00
|
|
|
};
|
|
|
|
|
2010-03-17 20:15:21 +00:00
|
|
|
static struct snd_soc_dai_driver fsl_ssi_dai_template = {
|
2013-04-15 17:19:58 +00:00
|
|
|
.probe = fsl_ssi_dai_probe,
|
2008-01-11 17:15:26 +00:00
|
|
|
.playback = {
|
2014-07-30 03:10:29 +00:00
|
|
|
.stream_name = "CPU-Playback",
|
2013-12-02 15:29:03 +00:00
|
|
|
.channels_min = 1,
|
2016-05-03 12:13:55 +00:00
|
|
|
.channels_max = 32,
|
2017-04-05 19:44:05 +00:00
|
|
|
.rates = SNDRV_PCM_RATE_CONTINUOUS,
|
2008-01-11 17:15:26 +00:00
|
|
|
.formats = FSLSSI_I2S_FORMATS,
|
|
|
|
},
|
|
|
|
.capture = {
|
2014-07-30 03:10:29 +00:00
|
|
|
.stream_name = "CPU-Capture",
|
2013-12-02 15:29:03 +00:00
|
|
|
.channels_min = 1,
|
2016-05-03 12:13:55 +00:00
|
|
|
.channels_max = 32,
|
2017-04-05 19:44:05 +00:00
|
|
|
.rates = SNDRV_PCM_RATE_CONTINUOUS,
|
2008-01-11 17:15:26 +00:00
|
|
|
.formats = FSLSSI_I2S_FORMATS,
|
|
|
|
},
|
2009-03-03 01:41:00 +00:00
|
|
|
.ops = &fsl_ssi_dai_ops,
|
2008-01-11 17:15:26 +00:00
|
|
|
};
|
|
|
|
|
2013-03-21 10:32:04 +00:00
|
|
|
static const struct snd_soc_component_driver fsl_ssi_component = {
|
2017-12-18 02:52:04 +00:00
|
|
|
.name = "fsl-ssi",
|
2022-06-23 12:51:34 +00:00
|
|
|
.legacy_dai_naming = 1,
|
2013-03-21 10:32:04 +00:00
|
|
|
};
|
|
|
|
|
2013-08-19 15:05:58 +00:00
|
|
|
static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
|
2018-02-12 22:03:24 +00:00
|
|
|
.symmetric_channels = 1,
|
2015-08-05 15:22:53 +00:00
|
|
|
.probe = fsl_ssi_dai_probe,
|
2013-08-19 15:05:58 +00:00
|
|
|
.playback = {
|
2023-01-06 23:15:06 +00:00
|
|
|
.stream_name = "CPU AC97 Playback",
|
2013-08-19 15:05:58 +00:00
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_8000_48000,
|
2017-11-27 22:34:44 +00:00
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20,
|
2013-08-19 15:05:58 +00:00
|
|
|
},
|
|
|
|
.capture = {
|
2023-01-06 23:15:06 +00:00
|
|
|
.stream_name = "CPU AC97 Capture",
|
2013-08-19 15:05:58 +00:00
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_48000,
|
2017-11-27 22:34:44 +00:00
|
|
|
/* 16-bit capture is broken (errata ERR003778) */
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S20,
|
2013-08-19 15:05:58 +00:00
|
|
|
},
|
2013-12-20 13:11:35 +00:00
|
|
|
.ops = &fsl_ssi_dai_ops,
|
2013-08-19 15:05:58 +00:00
|
|
|
};
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
static struct fsl_ssi *fsl_ac97_data;
|
2013-08-19 15:05:58 +00:00
|
|
|
|
2013-09-13 09:52:17 +00:00
|
|
|
static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
|
2017-12-18 02:52:04 +00:00
|
|
|
unsigned short val)
|
2013-08-19 15:05:58 +00:00
|
|
|
{
|
2014-05-27 08:24:25 +00:00
|
|
|
struct regmap *regs = fsl_ac97_data->regs;
|
2013-08-19 15:05:58 +00:00
|
|
|
unsigned int lreg;
|
|
|
|
unsigned int lval;
|
2015-08-05 15:21:35 +00:00
|
|
|
int ret;
|
2013-08-19 15:05:58 +00:00
|
|
|
|
|
|
|
if (reg > 0x7f)
|
|
|
|
return;
|
|
|
|
|
2017-11-20 22:16:07 +00:00
|
|
|
mutex_lock(&fsl_ac97_data->ac97_reg_lock);
|
|
|
|
|
2015-08-05 15:21:35 +00:00
|
|
|
ret = clk_prepare_enable(fsl_ac97_data->clk);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("ac97 write clk_prepare_enable failed: %d\n",
|
|
|
|
ret);
|
2017-11-20 22:16:07 +00:00
|
|
|
goto ret_unlock;
|
2015-08-05 15:21:35 +00:00
|
|
|
}
|
2013-08-19 15:05:58 +00:00
|
|
|
|
|
|
|
lreg = reg << 12;
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_write(regs, REG_SSI_SACADD, lreg);
|
2013-08-19 15:05:58 +00:00
|
|
|
|
|
|
|
lval = val << 4;
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_write(regs, REG_SSI_SACDAT, lval);
|
2013-08-19 15:05:58 +00:00
|
|
|
|
2017-12-18 02:52:04 +00:00
|
|
|
regmap_update_bits(regs, REG_SSI_SACNT,
|
|
|
|
SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);
|
2013-08-19 15:05:58 +00:00
|
|
|
udelay(100);
|
2015-08-05 15:21:35 +00:00
|
|
|
|
|
|
|
clk_disable_unprepare(fsl_ac97_data->clk);
|
2017-11-20 22:16:07 +00:00
|
|
|
|
|
|
|
ret_unlock:
|
|
|
|
mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
|
2013-08-19 15:05:58 +00:00
|
|
|
}
|
|
|
|
|
2013-09-13 09:52:17 +00:00
|
|
|
static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
|
2017-12-18 02:52:04 +00:00
|
|
|
unsigned short reg)
|
2013-08-19 15:05:58 +00:00
|
|
|
{
|
2014-05-27 08:24:25 +00:00
|
|
|
struct regmap *regs = fsl_ac97_data->regs;
|
2017-11-20 22:16:07 +00:00
|
|
|
unsigned short val = 0;
|
2014-05-27 08:24:25 +00:00
|
|
|
u32 reg_val;
|
2013-08-19 15:05:58 +00:00
|
|
|
unsigned int lreg;
|
2015-08-05 15:21:35 +00:00
|
|
|
int ret;
|
|
|
|
|
2017-11-20 22:16:07 +00:00
|
|
|
mutex_lock(&fsl_ac97_data->ac97_reg_lock);
|
|
|
|
|
2015-08-05 15:21:35 +00:00
|
|
|
ret = clk_prepare_enable(fsl_ac97_data->clk);
|
|
|
|
if (ret) {
|
2017-12-18 02:52:04 +00:00
|
|
|
pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
|
2017-11-20 22:16:07 +00:00
|
|
|
goto ret_unlock;
|
2015-08-05 15:21:35 +00:00
|
|
|
}
|
2013-08-19 15:05:58 +00:00
|
|
|
|
|
|
|
lreg = (reg & 0x7f) << 12;
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_write(regs, REG_SSI_SACADD, lreg);
|
2017-12-18 02:52:04 +00:00
|
|
|
regmap_update_bits(regs, REG_SSI_SACNT,
|
|
|
|
SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);
|
2013-08-19 15:05:58 +00:00
|
|
|
|
|
|
|
udelay(100);
|
|
|
|
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_read(regs, REG_SSI_SACDAT, ®_val);
|
2014-05-27 08:24:25 +00:00
|
|
|
val = (reg_val >> 4) & 0xffff;
|
2013-08-19 15:05:58 +00:00
|
|
|
|
2015-08-05 15:21:35 +00:00
|
|
|
clk_disable_unprepare(fsl_ac97_data->clk);
|
|
|
|
|
2017-11-20 22:16:07 +00:00
|
|
|
ret_unlock:
|
|
|
|
mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
|
2013-08-19 15:05:58 +00:00
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
|
2017-12-18 02:52:04 +00:00
|
|
|
.read = fsl_ssi_ac97_read,
|
|
|
|
.write = fsl_ssi_ac97_write,
|
2013-08-19 15:05:58 +00:00
|
|
|
};
|
|
|
|
|
2018-02-12 22:03:20 +00:00
|
|
|
/**
|
2020-07-02 19:21:37 +00:00
|
|
|
* fsl_ssi_hw_init - Initialize SSI registers
|
|
|
|
* @ssi: SSI context
|
2018-02-12 22:03:20 +00:00
|
|
|
*/
|
|
|
|
static int fsl_ssi_hw_init(struct fsl_ssi *ssi)
|
|
|
|
{
|
|
|
|
u32 wm = ssi->fifo_watermark;
|
|
|
|
|
|
|
|
/* Initialize regvals */
|
|
|
|
fsl_ssi_setup_regvals(ssi);
|
|
|
|
|
|
|
|
/* Set watermarks */
|
|
|
|
regmap_write(ssi->regs, REG_SSI_SFCSR,
|
|
|
|
SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
|
|
|
|
SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
|
|
|
|
|
|
|
|
/* Enable Dual FIFO mode */
|
|
|
|
if (ssi->use_dual_fifo)
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SCR,
|
|
|
|
SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
|
|
|
|
|
2018-02-12 22:03:21 +00:00
|
|
|
/* AC97 should start earlier to communicate with CODECs */
|
|
|
|
if (fsl_ssi_is_ac97(ssi)) {
|
2018-02-12 22:03:22 +00:00
|
|
|
_fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt);
|
2018-02-12 22:03:21 +00:00
|
|
|
fsl_ssi_setup_ac97(ssi);
|
|
|
|
}
|
|
|
|
|
2018-02-12 22:03:20 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-02-12 22:03:21 +00:00
|
|
|
/**
|
2020-07-02 19:21:37 +00:00
|
|
|
* fsl_ssi_hw_clean - Clear SSI registers
|
|
|
|
* @ssi: SSI context
|
2018-02-12 22:03:21 +00:00
|
|
|
*/
|
|
|
|
static void fsl_ssi_hw_clean(struct fsl_ssi *ssi)
|
|
|
|
{
|
|
|
|
/* Disable registers for AC97 */
|
|
|
|
if (fsl_ssi_is_ac97(ssi)) {
|
|
|
|
/* Disable TE and RE bits first */
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SCR,
|
|
|
|
SSI_SCR_TE | SSI_SCR_RE, 0);
|
|
|
|
/* Disable AC97 mode */
|
|
|
|
regmap_write(ssi->regs, REG_SSI_SACNT, 0);
|
|
|
|
/* Unset WAIT bits */
|
|
|
|
regmap_write(ssi->regs, REG_SSI_SOR, 0);
|
|
|
|
/* Disable SSI -- software reset */
|
|
|
|
regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0);
|
|
|
|
}
|
|
|
|
}
|
2020-07-02 19:21:37 +00:00
|
|
|
|
|
|
|
/*
|
2010-03-17 20:15:21 +00:00
|
|
|
* Make every character in a string lower-case
|
2008-01-11 17:15:26 +00:00
|
|
|
*/
|
2010-03-17 20:15:21 +00:00
|
|
|
static void make_lowercase(char *s)
|
|
|
|
{
|
2017-04-05 19:44:06 +00:00
|
|
|
if (!s)
|
|
|
|
return;
|
|
|
|
for (; *s; s++)
|
|
|
|
*s = tolower(*s);
|
2010-03-17 20:15:21 +00:00
|
|
|
}
|
|
|
|
|
2014-04-28 10:54:45 +00:00
|
|
|
static int fsl_ssi_imx_probe(struct platform_device *pdev,
|
2017-12-18 02:52:04 +00:00
|
|
|
struct fsl_ssi *ssi, void __iomem *iomem)
|
2014-04-28 10:54:45 +00:00
|
|
|
{
|
2017-12-18 02:52:01 +00:00
|
|
|
struct device *dev = &pdev->dev;
|
2014-04-28 10:54:45 +00:00
|
|
|
int ret;
|
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Backward compatible for a DT without ipg clock name assigned */
|
2017-12-18 02:52:00 +00:00
|
|
|
if (ssi->has_ipg_clk_name)
|
2017-12-18 02:52:01 +00:00
|
|
|
ssi->clk = devm_clk_get(dev, "ipg");
|
2014-09-16 02:13:16 +00:00
|
|
|
else
|
2017-12-18 02:52:01 +00:00
|
|
|
ssi->clk = devm_clk_get(dev, NULL);
|
2017-12-18 02:52:00 +00:00
|
|
|
if (IS_ERR(ssi->clk)) {
|
|
|
|
ret = PTR_ERR(ssi->clk);
|
2017-12-18 02:52:05 +00:00
|
|
|
dev_err(dev, "failed to get clock: %d\n", ret);
|
2014-04-28 10:54:45 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Enable the clock since regmap will not handle it in this case */
|
2017-12-18 02:52:00 +00:00
|
|
|
if (!ssi->has_ipg_clk_name) {
|
|
|
|
ret = clk_prepare_enable(ssi->clk);
|
2014-09-16 02:13:16 +00:00
|
|
|
if (ret) {
|
2017-12-18 02:52:01 +00:00
|
|
|
dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
|
2014-09-16 02:13:16 +00:00
|
|
|
return ret;
|
|
|
|
}
|
2014-04-28 10:54:45 +00:00
|
|
|
}
|
|
|
|
|
2021-09-21 21:35:33 +00:00
|
|
|
/* Do not error out for consumer cases that live without a baud clock */
|
2017-12-18 02:52:01 +00:00
|
|
|
ssi->baudclk = devm_clk_get(dev, "baud");
|
2017-12-18 02:52:00 +00:00
|
|
|
if (IS_ERR(ssi->baudclk))
|
2017-12-18 02:52:05 +00:00
|
|
|
dev_dbg(dev, "failed to get baud clock: %ld\n",
|
2017-12-18 02:52:00 +00:00
|
|
|
PTR_ERR(ssi->baudclk));
|
2014-04-28 10:54:45 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
|
|
|
|
ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
|
2017-12-18 02:52:03 +00:00
|
|
|
ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
|
|
|
|
ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
|
2014-04-28 10:54:45 +00:00
|
|
|
|
2018-02-12 22:03:24 +00:00
|
|
|
/* Use even numbers to avoid channel swap due to SDMA script design */
|
2022-05-10 11:56:48 +00:00
|
|
|
if (ssi->use_dual_fifo || ssi->use_dyna_fifo) {
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->dma_params_tx.maxburst &= ~0x1;
|
|
|
|
ssi->dma_params_rx.maxburst &= ~0x1;
|
2014-04-28 10:54:45 +00:00
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (!ssi->use_dma) {
|
2014-04-28 10:54:47 +00:00
|
|
|
/*
|
2017-12-18 02:52:02 +00:00
|
|
|
* Some boards use an incompatible codec. Use imx-fiq-pcm-audio
|
|
|
|
* to get it working, as DMA is not possible in this situation.
|
2014-04-28 10:54:47 +00:00
|
|
|
*/
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->fiq_params.irq = ssi->irq;
|
|
|
|
ssi->fiq_params.base = iomem;
|
|
|
|
ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
|
|
|
|
ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
|
2014-04-28 10:54:47 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
|
2014-04-28 10:54:47 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_pcm;
|
|
|
|
} else {
|
2022-02-23 13:06:25 +00:00
|
|
|
ret = imx_pcm_dma_init(pdev);
|
2014-04-28 10:54:47 +00:00
|
|
|
if (ret)
|
|
|
|
goto error_pcm;
|
|
|
|
}
|
|
|
|
|
2014-04-28 10:54:45 +00:00
|
|
|
return 0;
|
2014-04-28 10:54:47 +00:00
|
|
|
|
|
|
|
error_pcm:
|
2017-12-18 02:52:00 +00:00
|
|
|
if (!ssi->has_ipg_clk_name)
|
|
|
|
clk_disable_unprepare(ssi->clk);
|
2017-12-18 02:52:04 +00:00
|
|
|
|
2014-04-28 10:54:47 +00:00
|
|
|
return ret;
|
2014-04-28 10:54:45 +00:00
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:04 +00:00
|
|
|
static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
|
2014-04-28 10:54:45 +00:00
|
|
|
{
|
2017-12-18 02:52:00 +00:00
|
|
|
if (!ssi->use_dma)
|
2014-04-28 10:54:47 +00:00
|
|
|
imx_pcm_fiq_exit(pdev);
|
2017-12-18 02:52:00 +00:00
|
|
|
if (!ssi->has_ipg_clk_name)
|
|
|
|
clk_disable_unprepare(ssi->clk);
|
2014-04-28 10:54:45 +00:00
|
|
|
}
|
|
|
|
|
2018-02-12 22:03:24 +00:00
|
|
|
static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi)
|
2008-01-11 17:15:26 +00:00
|
|
|
{
|
2018-02-12 22:03:24 +00:00
|
|
|
struct device *dev = ssi->dev;
|
|
|
|
struct device_node *np = dev->of_node;
|
2010-03-17 20:15:21 +00:00
|
|
|
const char *p, *sprop;
|
2018-02-11 21:53:21 +00:00
|
|
|
const __be32 *iprop;
|
2018-02-12 22:03:24 +00:00
|
|
|
u32 dmas[4];
|
|
|
|
int ret;
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2018-02-12 22:03:24 +00:00
|
|
|
ret = of_property_match_string(np, "clock-names", "ipg");
|
|
|
|
/* Get error code if not found */
|
|
|
|
ssi->has_ipg_clk_name = ret >= 0;
|
2014-05-27 08:24:18 +00:00
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Check if being used in AC97 mode */
|
2014-05-27 08:24:19 +00:00
|
|
|
sprop = of_get_property(np, "fsl,mode", NULL);
|
2018-02-12 22:03:24 +00:00
|
|
|
if (sprop && !strcmp(sprop, "ac97-slave")) {
|
|
|
|
ssi->dai_fmt = FSLSSI_AC97_DAIFMT;
|
|
|
|
|
|
|
|
ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "failed to get SSI index property\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
strcpy(ssi->card_name, "ac97-codec");
|
2023-03-10 14:47:32 +00:00
|
|
|
} else if (!of_property_read_bool(np, "fsl,ssi-asynchronous")) {
|
2018-02-12 22:03:24 +00:00
|
|
|
/*
|
|
|
|
* In synchronous mode, STCK and STFS ports are used by RX
|
|
|
|
* as well. So the software should limit the sample rates,
|
|
|
|
* sample bits and channels to be symmetric.
|
|
|
|
*
|
|
|
|
* This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs
|
|
|
|
* in the SSI synchronous mode however it does not have to
|
|
|
|
* limit symmetric sample rates and sample bits.
|
|
|
|
*/
|
|
|
|
ssi->synchronous = true;
|
2014-05-27 08:24:19 +00:00
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Select DMA or FIQ */
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter");
|
2013-07-27 11:31:53 +00:00
|
|
|
|
2018-02-12 22:03:24 +00:00
|
|
|
/* Fetch FIFO depth; Set to 8 for older DT without this property */
|
|
|
|
iprop = of_get_property(np, "fsl,fifo-depth", NULL);
|
|
|
|
if (iprop)
|
|
|
|
ssi->fifo_depth = be32_to_cpup(iprop);
|
|
|
|
else
|
|
|
|
ssi->fifo_depth = 8;
|
|
|
|
|
|
|
|
/* Use dual FIFO mode depending on the support from SDMA script */
|
|
|
|
ret = of_property_read_u32_array(np, "dmas", dmas, 4);
|
|
|
|
if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
|
|
|
|
ssi->use_dual_fifo = true;
|
|
|
|
|
2022-05-10 11:56:48 +00:00
|
|
|
if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
|
|
|
|
ssi->use_dyna_fifo = true;
|
2018-02-12 22:03:24 +00:00
|
|
|
/*
|
|
|
|
* Backward compatible for older bindings by manually triggering the
|
|
|
|
* machine driver's probe(). Use /compatible property, including the
|
|
|
|
* address of CPU DAI driver structure, as the name of machine driver
|
|
|
|
*
|
|
|
|
* If card_name is set by AC97 earlier, bypass here since it uses a
|
|
|
|
* different name to register the device.
|
|
|
|
*/
|
|
|
|
if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) {
|
2019-02-19 15:46:47 +00:00
|
|
|
struct device_node *root = of_find_node_by_path("/");
|
|
|
|
|
|
|
|
sprop = of_get_property(root, "compatible", NULL);
|
|
|
|
of_node_put(root);
|
2018-02-12 22:03:24 +00:00
|
|
|
/* Strip "fsl," in the compatible name if applicable */
|
|
|
|
p = strrchr(sprop, ',');
|
|
|
|
if (p)
|
|
|
|
sprop = p + 1;
|
|
|
|
snprintf(ssi->card_name, sizeof(ssi->card_name),
|
|
|
|
"snd-soc-%s", sprop);
|
|
|
|
make_lowercase(ssi->card_name);
|
|
|
|
ssi->card_idx = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_ssi_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct regmap_config regconfig = fsl_ssi_regconfig;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct fsl_ssi *ssi;
|
|
|
|
struct resource *res;
|
|
|
|
void __iomem *iomem;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
|
|
|
|
if (!ssi)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
ssi->dev = dev;
|
2021-01-18 12:38:10 +00:00
|
|
|
ssi->soc = of_device_get_match_data(&pdev->dev);
|
2018-02-12 22:03:24 +00:00
|
|
|
|
|
|
|
/* Probe from DT */
|
|
|
|
ret = fsl_ssi_probe_from_dt(ssi);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (fsl_ssi_is_ac97(ssi)) {
|
|
|
|
memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
|
2017-12-18 02:52:04 +00:00
|
|
|
sizeof(fsl_ssi_ac97_dai));
|
2017-12-18 02:52:00 +00:00
|
|
|
fsl_ac97_data = ssi;
|
2013-08-19 15:05:58 +00:00
|
|
|
} else {
|
2017-12-18 02:52:00 +00:00
|
|
|
memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
|
2013-08-19 15:05:58 +00:00
|
|
|
sizeof(fsl_ssi_dai_template));
|
|
|
|
}
|
2017-12-18 02:52:01 +00:00
|
|
|
ssi->cpu_dai_drv.name = dev_name(dev);
|
2010-03-17 20:15:21 +00:00
|
|
|
|
2021-06-15 01:39:21 +00:00
|
|
|
iomem = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
2015-04-10 10:12:29 +00:00
|
|
|
if (IS_ERR(iomem))
|
|
|
|
return PTR_ERR(iomem);
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->ssi_phys = res->start;
|
2014-05-27 08:24:25 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (ssi->soc->imx21regs) {
|
2017-12-18 02:52:02 +00:00
|
|
|
/* No SACC{ST,EN,DIS} regs in imx21-class SSI */
|
2017-12-18 02:52:03 +00:00
|
|
|
regconfig.max_register = REG_SSI_SRMSK;
|
2016-09-29 18:22:52 +00:00
|
|
|
regconfig.num_reg_defaults_raw =
|
2017-12-18 02:52:03 +00:00
|
|
|
REG_SSI_SRMSK / sizeof(uint32_t) + 1;
|
2016-01-18 19:07:44 +00:00
|
|
|
}
|
|
|
|
|
2018-02-12 22:03:24 +00:00
|
|
|
if (ssi->has_ipg_clk_name)
|
2017-12-18 02:52:01 +00:00
|
|
|
ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem,
|
|
|
|
®config);
|
2018-02-12 22:03:24 +00:00
|
|
|
else
|
|
|
|
ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config);
|
2017-12-18 02:52:00 +00:00
|
|
|
if (IS_ERR(ssi->regs)) {
|
2017-12-18 02:52:05 +00:00
|
|
|
dev_err(dev, "failed to init register map\n");
|
2017-12-18 02:52:00 +00:00
|
|
|
return PTR_ERR(ssi->regs);
|
2014-05-27 08:24:25 +00:00
|
|
|
}
|
2011-08-16 22:47:45 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->irq = platform_get_irq(pdev, 0);
|
2019-07-30 18:15:49 +00:00
|
|
|
if (ssi->irq < 0)
|
2017-12-18 02:52:00 +00:00
|
|
|
return ssi->irq;
|
2011-08-16 22:47:45 +00:00
|
|
|
|
2018-02-12 22:03:24 +00:00
|
|
|
/* Set software limitations for synchronous mode except AC97 */
|
|
|
|
if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) {
|
2021-01-15 04:54:08 +00:00
|
|
|
ssi->cpu_dai_drv.symmetric_rate = 1;
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->cpu_dai_drv.symmetric_channels = 1;
|
2021-01-15 04:54:08 +00:00
|
|
|
ssi->cpu_dai_drv.symmetric_sample_bits = 1;
|
2013-12-03 10:38:07 +00:00
|
|
|
}
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2017-01-03 18:22:57 +00:00
|
|
|
/*
|
2017-12-18 02:52:02 +00:00
|
|
|
* Configure TX and RX DMA watermarks -- when to send a DMA request
|
2017-01-03 18:22:57 +00:00
|
|
|
*
|
2017-12-18 02:52:02 +00:00
|
|
|
* Values should be tested to avoid FIFO under/over run. Set maxburst
|
|
|
|
* to fifo_watermark to maxiumize DMA transaction to reduce overhead.
|
2017-01-03 18:22:57 +00:00
|
|
|
*/
|
2017-12-18 02:52:00 +00:00
|
|
|
switch (ssi->fifo_depth) {
|
2017-01-03 18:22:57 +00:00
|
|
|
case 15:
|
|
|
|
/*
|
2017-12-18 02:52:02 +00:00
|
|
|
* Set to 8 as a balanced configuration -- When TX FIFO has 8
|
|
|
|
* empty slots, send a DMA request to fill these 8 slots. The
|
|
|
|
* remaining 7 slots should be able to allow DMA to finish the
|
|
|
|
* transaction before TX FIFO underruns; Same applies to RX.
|
|
|
|
*
|
|
|
|
* Tested with cases running at 48kHz @ 16 bits x 16 channels
|
2017-01-03 18:22:57 +00:00
|
|
|
*/
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->fifo_watermark = 8;
|
|
|
|
ssi->dma_maxburst = 8;
|
2017-01-03 18:22:57 +00:00
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
default:
|
2017-12-18 02:52:02 +00:00
|
|
|
/* Safely use old watermark configurations for older chips */
|
2017-12-18 02:52:00 +00:00
|
|
|
ssi->fifo_watermark = ssi->fifo_depth - 2;
|
|
|
|
ssi->dma_maxburst = ssi->fifo_depth - 2;
|
2017-01-03 18:22:57 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:01 +00:00
|
|
|
dev_set_drvdata(dev, ssi);
|
2014-04-28 10:54:47 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (ssi->soc->imx) {
|
|
|
|
ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
|
2014-04-28 10:54:45 +00:00
|
|
|
if (ret)
|
2014-12-01 21:57:14 +00:00
|
|
|
return ret;
|
2013-12-20 13:11:31 +00:00
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (fsl_ssi_is_ac97(ssi)) {
|
|
|
|
mutex_init(&ssi->ac97_reg_lock);
|
2017-11-20 22:14:55 +00:00
|
|
|
ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
|
|
|
|
if (ret) {
|
2017-12-18 02:52:05 +00:00
|
|
|
dev_err(dev, "failed to set AC'97 ops\n");
|
2017-11-20 22:14:55 +00:00
|
|
|
goto error_ac97_ops;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:01 +00:00
|
|
|
ret = devm_snd_soc_register_component(dev, &fsl_ssi_component,
|
2017-12-18 02:52:00 +00:00
|
|
|
&ssi->cpu_dai_drv, 1);
|
2014-04-28 10:54:47 +00:00
|
|
|
if (ret) {
|
2017-12-18 02:52:01 +00:00
|
|
|
dev_err(dev, "failed to register DAI: %d\n", ret);
|
2014-04-28 10:54:47 +00:00
|
|
|
goto error_asoc_register;
|
|
|
|
}
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (ssi->use_dma) {
|
2017-12-18 02:52:01 +00:00
|
|
|
ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
|
|
|
|
dev_name(dev), ssi);
|
2013-08-19 15:06:01 +00:00
|
|
|
if (ret < 0) {
|
2017-12-18 02:52:05 +00:00
|
|
|
dev_err(dev, "failed to claim irq %u\n", ssi->irq);
|
2015-04-09 17:56:41 +00:00
|
|
|
goto error_asoc_register;
|
2013-08-19 15:06:01 +00:00
|
|
|
}
|
2012-03-16 08:56:43 +00:00
|
|
|
}
|
|
|
|
|
2019-06-14 09:47:55 +00:00
|
|
|
fsl_ssi_debugfs_create(&ssi->dbg_stats, dev);
|
2012-03-16 08:56:43 +00:00
|
|
|
|
2018-02-12 22:03:20 +00:00
|
|
|
/* Initially configures SSI registers */
|
|
|
|
fsl_ssi_hw_init(ssi);
|
|
|
|
|
2018-02-12 22:03:24 +00:00
|
|
|
/* Register a platform device for older bindings or AC97 */
|
|
|
|
if (ssi->card_name[0]) {
|
|
|
|
struct device *parent = dev;
|
|
|
|
/*
|
|
|
|
* Do not set SSI dev as the parent of AC97 CODEC device since
|
|
|
|
* it does not have a DT node. Otherwise ASoC core will assume
|
|
|
|
* CODEC has the same DT node as the SSI, so it may bypass the
|
|
|
|
* dai_probe() of SSI and then cause NULL DMA data pointers.
|
|
|
|
*/
|
|
|
|
if (fsl_ssi_is_ac97(ssi))
|
|
|
|
parent = NULL;
|
|
|
|
|
|
|
|
ssi->card_pdev = platform_device_register_data(parent,
|
|
|
|
ssi->card_name, ssi->card_idx, NULL, 0);
|
|
|
|
if (IS_ERR(ssi->card_pdev)) {
|
|
|
|
ret = PTR_ERR(ssi->card_pdev);
|
|
|
|
dev_err(dev, "failed to register %s: %d\n",
|
|
|
|
ssi->card_name, ret);
|
2015-08-05 15:26:44 +00:00
|
|
|
goto error_sound_card;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-03-17 20:15:21 +00:00
|
|
|
return 0;
|
2010-08-03 22:55:28 +00:00
|
|
|
|
2014-04-28 10:54:47 +00:00
|
|
|
error_sound_card:
|
2017-12-18 02:52:00 +00:00
|
|
|
fsl_ssi_debugfs_remove(&ssi->dbg_stats);
|
2014-04-28 10:54:47 +00:00
|
|
|
error_asoc_register:
|
2017-12-18 02:52:00 +00:00
|
|
|
if (fsl_ssi_is_ac97(ssi))
|
2017-11-20 22:14:55 +00:00
|
|
|
snd_soc_set_ac97_ops(NULL);
|
|
|
|
error_ac97_ops:
|
2017-12-18 02:52:00 +00:00
|
|
|
if (fsl_ssi_is_ac97(ssi))
|
|
|
|
mutex_destroy(&ssi->ac97_reg_lock);
|
2017-11-20 22:16:07 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (ssi->soc->imx)
|
|
|
|
fsl_ssi_imx_clean(pdev, ssi);
|
2011-08-16 22:47:45 +00:00
|
|
|
|
2010-08-03 22:55:28 +00:00
|
|
|
return ret;
|
2008-01-11 17:15:26 +00:00
|
|
|
}
|
|
|
|
|
2010-08-19 20:26:58 +00:00
|
|
|
static int fsl_ssi_remove(struct platform_device *pdev)
|
2008-01-11 17:15:26 +00:00
|
|
|
{
|
2017-12-18 02:52:00 +00:00
|
|
|
struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev);
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
fsl_ssi_debugfs_remove(&ssi->dbg_stats);
|
2013-12-20 13:11:29 +00:00
|
|
|
|
2018-02-12 22:03:24 +00:00
|
|
|
if (ssi->card_pdev)
|
|
|
|
platform_device_unregister(ssi->card_pdev);
|
2014-04-28 10:54:45 +00:00
|
|
|
|
2018-02-12 22:03:21 +00:00
|
|
|
/* Clean up SSI registers */
|
|
|
|
fsl_ssi_hw_clean(ssi);
|
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (ssi->soc->imx)
|
|
|
|
fsl_ssi_imx_clean(pdev, ssi);
|
2014-04-28 10:54:45 +00:00
|
|
|
|
2017-12-18 02:52:00 +00:00
|
|
|
if (fsl_ssi_is_ac97(ssi)) {
|
2015-08-05 15:25:31 +00:00
|
|
|
snd_soc_set_ac97_ops(NULL);
|
2017-12-18 02:52:00 +00:00
|
|
|
mutex_destroy(&ssi->ac97_reg_lock);
|
2017-11-20 22:16:07 +00:00
|
|
|
}
|
2015-08-05 15:25:31 +00:00
|
|
|
|
2010-03-17 20:15:21 +00:00
|
|
|
return 0;
|
2008-01-11 17:15:26 +00:00
|
|
|
}
|
2010-03-17 20:15:21 +00:00
|
|
|
|
2015-09-18 03:09:12 +00:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int fsl_ssi_suspend(struct device *dev)
|
|
|
|
{
|
2017-12-18 02:52:00 +00:00
|
|
|
struct fsl_ssi *ssi = dev_get_drvdata(dev);
|
|
|
|
struct regmap *regs = ssi->regs;
|
2015-09-18 03:09:12 +00:00
|
|
|
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
|
|
|
|
regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
|
2015-09-18 03:09:12 +00:00
|
|
|
|
|
|
|
regcache_cache_only(regs, true);
|
|
|
|
regcache_mark_dirty(regs);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_ssi_resume(struct device *dev)
|
|
|
|
{
|
2017-12-18 02:52:00 +00:00
|
|
|
struct fsl_ssi *ssi = dev_get_drvdata(dev);
|
|
|
|
struct regmap *regs = ssi->regs;
|
2015-09-18 03:09:12 +00:00
|
|
|
|
|
|
|
regcache_cache_only(regs, false);
|
|
|
|
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_update_bits(regs, REG_SSI_SFCSR,
|
2017-12-18 02:52:04 +00:00
|
|
|
SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
|
|
|
|
SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
|
|
|
|
ssi->regcache_sfcsr);
|
2017-12-18 02:52:03 +00:00
|
|
|
regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
|
2015-09-18 03:09:12 +00:00
|
|
|
|
|
|
|
return regcache_sync(regs);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
|
|
|
|
static const struct dev_pm_ops fsl_ssi_pm = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
|
|
|
|
};
|
|
|
|
|
2011-02-23 04:05:04 +00:00
|
|
|
static struct platform_driver fsl_ssi_driver = {
|
2010-03-17 20:15:21 +00:00
|
|
|
.driver = {
|
|
|
|
.name = "fsl-ssi-dai",
|
|
|
|
.of_match_table = fsl_ssi_ids,
|
2015-09-18 03:09:12 +00:00
|
|
|
.pm = &fsl_ssi_pm,
|
2010-03-17 20:15:21 +00:00
|
|
|
},
|
|
|
|
.probe = fsl_ssi_probe,
|
|
|
|
.remove = fsl_ssi_remove,
|
|
|
|
};
|
2008-01-11 17:15:26 +00:00
|
|
|
|
2011-11-25 02:10:55 +00:00
|
|
|
module_platform_driver(fsl_ssi_driver);
|
2009-03-05 23:23:37 +00:00
|
|
|
|
2013-07-20 19:16:01 +00:00
|
|
|
MODULE_ALIAS("platform:fsl-ssi-dai");
|
2008-01-11 17:15:26 +00:00
|
|
|
MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
|
|
|
|
MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
|
2010-03-17 20:15:21 +00:00
|
|
|
MODULE_LICENSE("GPL v2");
|