2021-03-12 02:38:41 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2017-2021 NXP
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*/
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#ifndef __FSL_RPMSG_H
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#define __FSL_RPMSG_H
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2021-08-27 06:00:38 +00:00
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/*
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* struct fsl_rpmsg_soc_data
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* @rates: supported rates
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* @formats: supported formats
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*/
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struct fsl_rpmsg_soc_data {
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int rates;
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u64 formats;
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};
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2021-03-12 02:38:41 +00:00
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/*
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* struct fsl_rpmsg - rpmsg private data
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*
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* @ipg: ipg clock for cpu dai (SAI)
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* @mclk: master clock for cpu dai (SAI)
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* @dma: clock for dma device
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* @pll8k: parent clock for multiple of 8kHz frequency
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* @pll11k: parent clock for multiple of 11kHz frequency
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* @card_pdev: Platform_device pointer to register a sound card
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2021-08-27 06:00:38 +00:00
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* @soc_data: soc specific data
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2021-03-12 02:38:41 +00:00
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* @mclk_streams: Active streams that are using baudclk
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* @force_lpa: force enable low power audio routine if condition satisfy
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* @enable_lpa: enable low power audio routine according to dts setting
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* @buffer_size: pre allocated dma buffer size
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*/
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struct fsl_rpmsg {
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struct clk *ipg;
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struct clk *mclk;
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struct clk *dma;
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struct clk *pll8k;
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struct clk *pll11k;
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struct platform_device *card_pdev;
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2021-08-27 06:00:38 +00:00
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const struct fsl_rpmsg_soc_data *soc_data;
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2021-03-12 02:38:41 +00:00
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unsigned int mclk_streams;
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int force_lpa;
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int enable_lpa;
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int buffer_size;
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};
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#endif /* __FSL_RPMSG_H */
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