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linux/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt

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spi/tegra114: add spi driver Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller is different than the older SoCs SPI controller in internal design as well as register interface. This driver supports the: - non DMA based transfer for smaller transfer i.e. less than FIFO depth. - APB DMA based transfer for larger transfer i.e. more than FIFO depth. - Clock gating through runtime PM callbacks. - registration through DT only. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2013-02-22 12:37:39 +00:00
NVIDIA Tegra114 SPI controller.
Required properties:
Documentation: DT bindings: add more Tegra chip compatible strings Align compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers: http://marc.info/?l=devicetree&m=142255654213019&w=2 The primary objective here is to avoid checkpatch warnings, per: http://marc.info/?l=linux-tegra&m=142201349727836&w=2 DT binding text files have been updated for the following IP blocks: - PCIe - SOR - SoC timers - AHB "gizmo" - APB_MISC - pinmux control - UART - PWM - I2C - SPI - RTC - PMC - eFuse - AHCI - HDA - XUSB_PADCTRL - SDHCI - SOC_THERM - AHUB - I2S - EHCI - USB PHY N.B. The nvidia,tegra20-timer compatible string is removed from the nvidia,tegra30-timer.txt documentation file because it's already mentioned in the nvidia,tegra20-timer.txt documentation file. This second version takes into account the following requests from Rob Herring <robherring2@gmail.com>: - Per-IP block patches have been combined into a single patch - Explicit documentation about which compatible strings are actually matched by the driver has been removed. In its place is implicit documentation that loosely follows Rob's prescribed format: "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ..." [...] "You should attempt to document known values of <chip> if you use it" Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Dylan Reid <dgreid@chromium.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Jingchang Lu <jingchang.lu@freescale.com> Cc: John Crispin <blogic@openwrt.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mikko Perttunen <mperttunen@nvidia.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Takashi Iwai <tiwai@suse.de> Cc: Tejun Heo <tj@kernel.org> Cc: "Terje Bergström" <tbergstrom@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Zhang Rui <rui.zhang@intel.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-i2c@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-pwm@vger.kernel.org Cc: linux-tegra@vger.kernel.org Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
2015-01-30 22:11:04 +00:00
- compatible : For Tegra114, must contain "nvidia,tegra114-spi".
Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
<chip> is tegra124, tegra132, or tegra210.
spi/tegra114: add spi driver Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller is different than the older SoCs SPI controller in internal design as well as register interface. This driver supports the: - non DMA based transfer for smaller transfer i.e. less than FIFO depth. - APB DMA based transfer for larger transfer i.e. more than FIFO depth. - Clock gating through runtime PM callbacks. - registration through DT only. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2013-02-22 12:37:39 +00:00
- reg: Should contain SPI registers location and length.
- interrupts: Should contain SPI interrupts.
ARM: tegra: add missing clock documentation to DT bindings Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
2013-11-06 21:00:25 +00:00
- clock-names : Must include the following entries:
- spi
ARM: tegra: document reset properties in DT bindings Update all the Tegra DT bindings to require resets/reset-names properties where the HW module has reset inputs. Remove any entries from clocks or clock-names that were only required to identify reset inputs, rather than referring to real clocks. This is a DT-ABI-incompatible change. It is the first of two changes required for me to consider the Tegra DT bindings as stable, the other being conversion to the common DMA DT bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
2013-11-07 17:11:27 +00:00
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
- spi
ARM: tegra: document use of standard DMA DT bindings Update all the Tegra DT bindings to require the standard dmas/dma-names properties rather than non-standard nvidia,dma-request-selector property. This is a DT-ABI-incompatible change. It is the second of two changes required for me to consider the Tegra DT bindings as stable, the other being the previous conversion to the common reset bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-11-11 20:04:19 +00:00
- dmas : Must contain an entry for each entry in clock-names.
See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
- rx
- tx
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
spi/tegra114: add spi driver Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller is different than the older SoCs SPI controller in internal design as well as register interface. This driver supports the: - non DMA based transfer for smaller transfer i.e. less than FIFO depth. - APB DMA based transfer for larger transfer i.e. more than FIFO depth. - Clock gating through runtime PM callbacks. - registration through DT only. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2013-02-22 12:37:39 +00:00
Recommended properties:
- spi-max-frequency: Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt
Example:
spi@7000d600 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
spi-max-frequency = <25000000>;
#address-cells = <1>;
#size-cells = <0>;
ARM: tegra: add missing clock documentation to DT bindings Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
2013-11-06 21:00:25 +00:00
clocks = <&tegra_car 44>;
clock-names = "spi";
ARM: tegra: document reset properties in DT bindings Update all the Tegra DT bindings to require resets/reset-names properties where the HW module has reset inputs. Remove any entries from clocks or clock-names that were only required to identify reset inputs, rather than referring to real clocks. This is a DT-ABI-incompatible change. It is the first of two changes required for me to consider the Tegra DT bindings as stable, the other being conversion to the common DMA DT bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
2013-11-07 17:11:27 +00:00
resets = <&tegra_car 44>;
reset-names = "spi";
ARM: tegra: document use of standard DMA DT bindings Update all the Tegra DT bindings to require the standard dmas/dma-names properties rather than non-standard nvidia,dma-request-selector property. This is a DT-ABI-incompatible change. It is the second of two changes required for me to consider the Tegra DT bindings as stable, the other being the previous conversion to the common reset bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-11-11 20:04:19 +00:00
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
spi/tegra114: add spi driver Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller is different than the older SoCs SPI controller in internal design as well as register interface. This driver supports the: - non DMA based transfer for smaller transfer i.e. less than FIFO depth. - APB DMA based transfer for larger transfer i.e. more than FIFO depth. - Clock gating through runtime PM callbacks. - registration through DT only. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2013-02-22 12:37:39 +00:00
};
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