2019-12-09 14:08:09 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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//
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// HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets
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//
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// Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
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// Author: John Garry <john.garry@huawei.com>
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#include <linux/acpi.h>
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#include <linux/bitops.h>
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2020-09-24 12:24:30 +00:00
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#include <linux/completion.h>
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2020-02-28 15:18:51 +00:00
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#include <linux/dmi.h>
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2020-09-24 12:24:30 +00:00
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#include <linux/interrupt.h>
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2019-12-09 14:08:09 +00:00
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#define HISI_SFC_V3XX_VERSION (0x1f8)
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2021-01-27 09:40:50 +00:00
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#define HISI_SFC_V3XX_GLB_CFG (0x100)
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#define HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE BIT(2)
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2020-09-24 12:24:30 +00:00
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#define HISI_SFC_V3XX_RAW_INT_STAT (0x120)
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#define HISI_SFC_V3XX_INT_STAT (0x124)
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#define HISI_SFC_V3XX_INT_MASK (0x128)
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2020-04-17 07:48:27 +00:00
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#define HISI_SFC_V3XX_INT_CLR (0x12c)
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2019-12-09 14:08:09 +00:00
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#define HISI_SFC_V3XX_CMD_CFG (0x300)
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#define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9
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#define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8)
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#define HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK BIT(7)
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#define HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF 4
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#define HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK BIT(3)
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#define HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF 1
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#define HISI_SFC_V3XX_CMD_CFG_START_MSK BIT(0)
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#define HISI_SFC_V3XX_CMD_INS (0x308)
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#define HISI_SFC_V3XX_CMD_ADDR (0x30c)
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#define HISI_SFC_V3XX_CMD_DATABUF0 (0x400)
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2020-09-24 12:24:29 +00:00
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/* Common definition of interrupt bit masks */
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#define HISI_SFC_V3XX_INT_MASK_ALL (0x1ff) /* all the masks */
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2020-09-24 12:24:30 +00:00
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#define HISI_SFC_V3XX_INT_MASK_CPLT BIT(0) /* command execution complete */
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2020-09-24 12:24:29 +00:00
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#define HISI_SFC_V3XX_INT_MASK_PP_ERR BIT(2) /* page progrom error */
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#define HISI_SFC_V3XX_INT_MASK_IACCES BIT(5) /* error visiting inaccessible/
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* protected address
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*/
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2020-09-24 12:24:27 +00:00
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/* IO Mode definition in HISI_SFC_V3XX_CMD_CFG */
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#define HISI_SFC_V3XX_STD (0 << 17)
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#define HISI_SFC_V3XX_DIDO (1 << 17)
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#define HISI_SFC_V3XX_DIO (2 << 17)
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#define HISI_SFC_V3XX_FULL_DIO (3 << 17)
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#define HISI_SFC_V3XX_QIQO (5 << 17)
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#define HISI_SFC_V3XX_QIO (6 << 17)
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#define HISI_SFC_V3XX_FULL_QIO (7 << 17)
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/*
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* The IO modes lookup table. hisi_sfc_v3xx_io_modes[(z - 1) / 2][y / 2][x / 2]
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* stands for x-y-z mode, as described in SFDP terminology. -EIO indicates
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* an invalid mode.
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*/
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static const int hisi_sfc_v3xx_io_modes[2][3][3] = {
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{
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{ HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO, HISI_SFC_V3XX_DIDO },
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{ HISI_SFC_V3XX_DIO, HISI_SFC_V3XX_FULL_DIO, -EIO },
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{ -EIO, -EIO, -EIO },
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},
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{
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{ HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO, HISI_SFC_V3XX_QIQO },
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{ -EIO, -EIO, -EIO },
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{ HISI_SFC_V3XX_QIO, -EIO, HISI_SFC_V3XX_FULL_QIO },
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},
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};
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2019-12-09 14:08:09 +00:00
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struct hisi_sfc_v3xx_host {
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struct device *dev;
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void __iomem *regbase;
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int max_cmd_dword;
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2020-09-24 12:24:30 +00:00
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struct completion *completion;
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2021-01-27 09:40:50 +00:00
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u8 address_mode;
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2020-09-24 12:24:30 +00:00
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int irq;
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2019-12-09 14:08:09 +00:00
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};
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2020-09-24 12:24:30 +00:00
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static void hisi_sfc_v3xx_disable_int(struct hisi_sfc_v3xx_host *host)
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{
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writel(0, host->regbase + HISI_SFC_V3XX_INT_MASK);
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}
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static void hisi_sfc_v3xx_enable_int(struct hisi_sfc_v3xx_host *host)
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{
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writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_MASK);
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}
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static void hisi_sfc_v3xx_clear_int(struct hisi_sfc_v3xx_host *host)
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{
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writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_CLR);
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}
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/*
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* The interrupt status register indicates whether an error occurs
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* after per operation. Check it, and clear the interrupts for
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* next time judgement.
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*/
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static int hisi_sfc_v3xx_handle_completion(struct hisi_sfc_v3xx_host *host)
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{
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u32 reg;
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reg = readl(host->regbase + HISI_SFC_V3XX_RAW_INT_STAT);
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hisi_sfc_v3xx_clear_int(host);
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if (reg & HISI_SFC_V3XX_INT_MASK_IACCES) {
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dev_err(host->dev, "fail to access protected address\n");
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return -EIO;
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}
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if (reg & HISI_SFC_V3XX_INT_MASK_PP_ERR) {
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dev_err(host->dev, "page program operation failed\n");
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return -EIO;
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}
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/*
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* The other bits of the interrupt registers is not currently
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* used and probably not be triggered in this driver. When it
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* happens, we regard it as an unsupported error here.
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*/
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if (!(reg & HISI_SFC_V3XX_INT_MASK_CPLT)) {
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2020-09-28 12:30:42 +00:00
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dev_err(host->dev, "unsupported error occurred, status=0x%x\n", reg);
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2020-09-24 12:24:30 +00:00
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return -EIO;
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}
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return 0;
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}
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2019-12-09 14:08:09 +00:00
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#define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000
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#define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10
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static int hisi_sfc_v3xx_wait_cmd_idle(struct hisi_sfc_v3xx_host *host)
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{
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u32 reg;
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return readl_poll_timeout(host->regbase + HISI_SFC_V3XX_CMD_CFG, reg,
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!(reg & HISI_SFC_V3XX_CMD_CFG_START_MSK),
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HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US,
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HISI_SFC_V3XX_WAIT_TIMEOUT_US);
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}
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static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem,
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struct spi_mem_op *op)
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{
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struct spi_device *spi = mem->spi;
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struct hisi_sfc_v3xx_host *host;
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uintptr_t addr = (uintptr_t)op->data.buf.in;
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int max_byte_count;
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host = spi_controller_get_devdata(spi->master);
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max_byte_count = host->max_cmd_dword * 4;
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if (!IS_ALIGNED(addr, 4) && op->data.nbytes >= 4)
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op->data.nbytes = 4 - (addr % 4);
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else if (op->data.nbytes > max_byte_count)
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op->data.nbytes = max_byte_count;
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return 0;
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}
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2020-09-24 12:24:27 +00:00
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/*
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* The controller only supports Standard SPI mode, Duall mode and
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* Quad mode. Double sanitize the ops here to avoid OOB access.
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*/
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static bool hisi_sfc_v3xx_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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2021-01-27 09:40:50 +00:00
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struct spi_device *spi = mem->spi;
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struct hisi_sfc_v3xx_host *host;
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host = spi_controller_get_devdata(spi->master);
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2020-09-24 12:24:27 +00:00
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if (op->data.buswidth > 4 || op->dummy.buswidth > 4 ||
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op->addr.buswidth > 4 || op->cmd.buswidth > 4)
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return false;
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2021-01-27 09:40:50 +00:00
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if (op->addr.nbytes != host->address_mode && op->addr.nbytes)
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return false;
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2020-09-24 12:24:27 +00:00
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return spi_mem_default_supports_op(mem, op);
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}
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2019-12-09 14:08:09 +00:00
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/*
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* memcpy_{to,from}io doesn't gurantee 32b accesses - which we require for the
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* DATABUF registers -so use __io{read,write}32_copy when possible. For
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* trailing bytes, copy them byte-by-byte from the DATABUF register, as we
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* can't clobber outside the source/dest buffer.
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*
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* For efficient data read/write, we try to put any start 32b unaligned data
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* into a separate transaction in hisi_sfc_v3xx_adjust_op_size().
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*/
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static void hisi_sfc_v3xx_read_databuf(struct hisi_sfc_v3xx_host *host,
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u8 *to, unsigned int len)
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{
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void __iomem *from;
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int i;
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from = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
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if (IS_ALIGNED((uintptr_t)to, 4)) {
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int words = len / 4;
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__ioread32_copy(to, from, words);
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len -= words * 4;
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if (len) {
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u32 val;
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to += words * 4;
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from += words * 4;
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val = __raw_readl(from);
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for (i = 0; i < len; i++, val >>= 8, to++)
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*to = (u8)val;
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}
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} else {
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for (i = 0; i < DIV_ROUND_UP(len, 4); i++, from += 4) {
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u32 val = __raw_readl(from);
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int j;
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for (j = 0; j < 4 && (j + (i * 4) < len);
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to++, val >>= 8, j++)
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*to = (u8)val;
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}
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}
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}
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static void hisi_sfc_v3xx_write_databuf(struct hisi_sfc_v3xx_host *host,
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const u8 *from, unsigned int len)
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{
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void __iomem *to;
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int i;
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to = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
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if (IS_ALIGNED((uintptr_t)from, 4)) {
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int words = len / 4;
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__iowrite32_copy(to, from, words);
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len -= words * 4;
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if (len) {
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u32 val = 0;
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to += words * 4;
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from += words * 4;
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for (i = 0; i < len; i++, from++)
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val |= *from << i * 8;
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__raw_writel(val, to);
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}
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} else {
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for (i = 0; i < DIV_ROUND_UP(len, 4); i++, to += 4) {
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u32 val = 0;
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int j;
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for (j = 0; j < 4 && (j + (i * 4) < len);
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from++, j++)
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val |= *from << j * 8;
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__raw_writel(val, to);
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}
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}
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}
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2020-09-24 12:24:28 +00:00
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static int hisi_sfc_v3xx_start_bus(struct hisi_sfc_v3xx_host *host,
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const struct spi_mem_op *op,
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u8 chip_select)
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2019-12-09 14:08:09 +00:00
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{
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2020-09-24 12:24:28 +00:00
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int len = op->data.nbytes, buswidth_mode;
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u32 config = 0;
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2019-12-09 14:08:09 +00:00
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if (op->addr.nbytes)
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config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK;
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2020-09-24 12:24:27 +00:00
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if (op->data.buswidth == 0 || op->data.buswidth == 1) {
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buswidth_mode = HISI_SFC_V3XX_STD;
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} else {
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int data_idx, addr_idx, cmd_idx;
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data_idx = (op->data.buswidth - 1) / 2;
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addr_idx = op->addr.buswidth / 2;
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cmd_idx = op->cmd.buswidth / 2;
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buswidth_mode = hisi_sfc_v3xx_io_modes[data_idx][addr_idx][cmd_idx];
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2020-02-28 15:18:50 +00:00
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}
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2020-09-24 12:24:27 +00:00
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if (buswidth_mode < 0)
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return buswidth_mode;
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config |= buswidth_mode;
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2020-02-28 15:18:50 +00:00
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2019-12-09 14:08:09 +00:00
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if (op->data.dir != SPI_MEM_NO_DATA) {
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config |= (len - 1) << HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF;
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config |= HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK;
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}
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2020-09-24 12:24:28 +00:00
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if (op->data.dir == SPI_MEM_DATA_IN)
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2019-12-09 14:08:09 +00:00
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config |= HISI_SFC_V3XX_CMD_CFG_RW_MSK;
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config |= op->dummy.nbytes << HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF |
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chip_select << HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF |
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HISI_SFC_V3XX_CMD_CFG_START_MSK;
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writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR);
|
|
|
|
writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS);
|
|
|
|
|
|
|
|
writel(config, host->regbase + HISI_SFC_V3XX_CMD_CFG);
|
|
|
|
|
2020-09-24 12:24:28 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host,
|
|
|
|
const struct spi_mem_op *op,
|
|
|
|
u8 chip_select)
|
|
|
|
{
|
2020-09-24 12:24:30 +00:00
|
|
|
DECLARE_COMPLETION_ONSTACK(done);
|
2020-09-24 12:24:28 +00:00
|
|
|
int ret;
|
|
|
|
|
2020-09-24 12:24:30 +00:00
|
|
|
if (host->irq) {
|
|
|
|
host->completion = &done;
|
|
|
|
hisi_sfc_v3xx_enable_int(host);
|
|
|
|
}
|
|
|
|
|
2020-09-24 12:24:28 +00:00
|
|
|
if (op->data.dir == SPI_MEM_DATA_OUT)
|
|
|
|
hisi_sfc_v3xx_write_databuf(host, op->data.buf.out, op->data.nbytes);
|
|
|
|
|
|
|
|
ret = hisi_sfc_v3xx_start_bus(host, op, chip_select);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2020-09-24 12:24:30 +00:00
|
|
|
if (host->irq) {
|
|
|
|
ret = wait_for_completion_timeout(host->completion,
|
|
|
|
usecs_to_jiffies(HISI_SFC_V3XX_WAIT_TIMEOUT_US));
|
|
|
|
if (!ret)
|
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
else
|
|
|
|
ret = 0;
|
2020-04-17 07:48:27 +00:00
|
|
|
|
2020-09-24 12:24:30 +00:00
|
|
|
hisi_sfc_v3xx_disable_int(host);
|
2021-04-12 11:58:27 +00:00
|
|
|
synchronize_irq(host->irq);
|
2020-09-24 12:24:30 +00:00
|
|
|
host->completion = NULL;
|
|
|
|
} else {
|
|
|
|
ret = hisi_sfc_v3xx_wait_cmd_idle(host);
|
2020-04-17 07:48:27 +00:00
|
|
|
}
|
2020-09-24 12:24:30 +00:00
|
|
|
if (hisi_sfc_v3xx_handle_completion(host) || ret)
|
2020-04-17 07:48:27 +00:00
|
|
|
return -EIO;
|
|
|
|
|
2019-12-09 14:08:09 +00:00
|
|
|
if (op->data.dir == SPI_MEM_DATA_IN)
|
2020-09-24 12:24:28 +00:00
|
|
|
hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, op->data.nbytes);
|
2019-12-09 14:08:09 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
|
|
|
|
const struct spi_mem_op *op)
|
|
|
|
{
|
|
|
|
struct hisi_sfc_v3xx_host *host;
|
|
|
|
struct spi_device *spi = mem->spi;
|
|
|
|
u8 chip_select = spi->chip_select;
|
|
|
|
|
|
|
|
host = spi_controller_get_devdata(spi->master);
|
|
|
|
|
|
|
|
return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
|
|
|
|
.adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
|
2020-09-24 12:24:27 +00:00
|
|
|
.supports_op = hisi_sfc_v3xx_supports_op,
|
2019-12-09 14:08:09 +00:00
|
|
|
.exec_op = hisi_sfc_v3xx_exec_op,
|
|
|
|
};
|
|
|
|
|
2020-09-24 12:24:30 +00:00
|
|
|
static irqreturn_t hisi_sfc_v3xx_isr(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct hisi_sfc_v3xx_host *host = data;
|
|
|
|
|
|
|
|
hisi_sfc_v3xx_disable_int(host);
|
|
|
|
|
|
|
|
complete(host->completion);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2020-02-28 15:18:51 +00:00
|
|
|
static int hisi_sfc_v3xx_buswidth_override_bits;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ACPI FW does not allow us to currently set the device buswidth, so quirk it
|
|
|
|
* depending on the board.
|
|
|
|
*/
|
|
|
|
static int __init hisi_sfc_v3xx_dmi_quirk(const struct dmi_system_id *d)
|
|
|
|
{
|
|
|
|
hisi_sfc_v3xx_buswidth_override_bits = SPI_RX_QUAD | SPI_TX_QUAD;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dmi_system_id hisi_sfc_v3xx_dmi_quirk_table[] = {
|
|
|
|
{
|
|
|
|
.callback = hisi_sfc_v3xx_dmi_quirk,
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "D06"),
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.callback = hisi_sfc_v3xx_dmi_quirk,
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 2280 V2"),
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.callback = hisi_sfc_v3xx_dmi_quirk,
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 200 (Model 2280)"),
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
2019-12-09 14:08:09 +00:00
|
|
|
static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct hisi_sfc_v3xx_host *host;
|
|
|
|
struct spi_controller *ctlr;
|
2021-01-27 09:40:50 +00:00
|
|
|
u32 version, glb_config;
|
2019-12-09 14:08:09 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
|
|
|
|
if (!ctlr)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
|
|
|
|
SPI_TX_DUAL | SPI_TX_QUAD;
|
|
|
|
|
2020-02-28 15:18:51 +00:00
|
|
|
ctlr->buswidth_override_bits = hisi_sfc_v3xx_buswidth_override_bits;
|
|
|
|
|
2019-12-09 14:08:09 +00:00
|
|
|
host = spi_controller_get_devdata(ctlr);
|
|
|
|
host->dev = dev;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
|
|
|
|
host->regbase = devm_platform_ioremap_resource(pdev, 0);
|
|
|
|
if (IS_ERR(host->regbase)) {
|
|
|
|
ret = PTR_ERR(host->regbase);
|
|
|
|
goto err_put_master;
|
|
|
|
}
|
|
|
|
|
2020-09-24 12:24:30 +00:00
|
|
|
host->irq = platform_get_irq_optional(pdev, 0);
|
|
|
|
if (host->irq == -EPROBE_DEFER) {
|
|
|
|
ret = -EPROBE_DEFER;
|
|
|
|
goto err_put_master;
|
|
|
|
}
|
|
|
|
|
|
|
|
hisi_sfc_v3xx_disable_int(host);
|
|
|
|
|
|
|
|
if (host->irq > 0) {
|
|
|
|
ret = devm_request_irq(dev, host->irq, hisi_sfc_v3xx_isr, 0,
|
|
|
|
"hisi-sfc-v3xx", host);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "failed to request irq%d, ret = %d\n", host->irq, ret);
|
|
|
|
host->irq = 0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
host->irq = 0;
|
|
|
|
}
|
|
|
|
|
2019-12-09 14:08:09 +00:00
|
|
|
ctlr->bus_num = -1;
|
|
|
|
ctlr->num_chipselect = 1;
|
|
|
|
ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;
|
|
|
|
|
2021-01-27 09:40:50 +00:00
|
|
|
/*
|
|
|
|
* The address mode of the controller is either 3 or 4,
|
|
|
|
* which is indicated by the address mode bit in
|
|
|
|
* the global config register. The register is read only
|
|
|
|
* for the OS driver.
|
|
|
|
*/
|
|
|
|
glb_config = readl(host->regbase + HISI_SFC_V3XX_GLB_CFG);
|
|
|
|
if (glb_config & HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE)
|
|
|
|
host->address_mode = 4;
|
|
|
|
else
|
|
|
|
host->address_mode = 3;
|
|
|
|
|
2019-12-09 14:08:09 +00:00
|
|
|
version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
|
|
|
|
|
2021-01-13 08:31:56 +00:00
|
|
|
if (version >= 0x351)
|
2019-12-09 14:08:09 +00:00
|
|
|
host->max_cmd_dword = 64;
|
2021-01-13 08:31:56 +00:00
|
|
|
else
|
2019-12-09 14:08:09 +00:00
|
|
|
host->max_cmd_dword = 16;
|
|
|
|
|
|
|
|
ret = devm_spi_register_controller(dev, ctlr);
|
|
|
|
if (ret)
|
|
|
|
goto err_put_master;
|
|
|
|
|
2020-09-24 12:24:30 +00:00
|
|
|
dev_info(&pdev->dev, "hw version 0x%x, %s mode.\n",
|
|
|
|
version, host->irq ? "irq" : "polling");
|
2019-12-09 14:08:09 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_put_master:
|
|
|
|
spi_master_put(ctlr);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_ACPI)
|
|
|
|
static const struct acpi_device_id hisi_sfc_v3xx_acpi_ids[] = {
|
|
|
|
{"HISI0341", 0},
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(acpi, hisi_sfc_v3xx_acpi_ids);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static struct platform_driver hisi_sfc_v3xx_spi_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "hisi-sfc-v3xx",
|
|
|
|
.acpi_match_table = ACPI_PTR(hisi_sfc_v3xx_acpi_ids),
|
|
|
|
},
|
|
|
|
.probe = hisi_sfc_v3xx_probe,
|
|
|
|
};
|
|
|
|
|
2020-02-28 15:18:51 +00:00
|
|
|
static int __init hisi_sfc_v3xx_spi_init(void)
|
|
|
|
{
|
|
|
|
dmi_check_system(hisi_sfc_v3xx_dmi_quirk_table);
|
|
|
|
|
|
|
|
return platform_driver_register(&hisi_sfc_v3xx_spi_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit hisi_sfc_v3xx_spi_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&hisi_sfc_v3xx_spi_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(hisi_sfc_v3xx_spi_init);
|
|
|
|
module_exit(hisi_sfc_v3xx_spi_exit);
|
2019-12-09 14:08:09 +00:00
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
|
|
|
|
MODULE_DESCRIPTION("HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets");
|