2008-10-16 09:32:24 +00:00
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/*
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* Common interrupt code for 32 and 64 bit
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*/
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/seq_file.h>
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2009-01-04 10:52:17 +00:00
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#include <linux/smp.h>
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2009-02-06 22:09:41 +00:00
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#include <linux/ftrace.h>
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2008-10-16 09:32:24 +00:00
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2009-02-17 12:58:15 +00:00
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#include <asm/apic.h>
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2008-10-16 09:32:24 +00:00
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#include <asm/io_apic.h>
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2008-12-23 14:15:17 +00:00
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#include <asm/irq.h>
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2009-02-06 22:09:41 +00:00
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#include <asm/idle.h>
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2009-05-27 19:56:52 +00:00
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#include <asm/mce.h>
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2009-04-10 18:33:10 +00:00
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#include <asm/hw_irq.h>
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2008-10-16 09:32:24 +00:00
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atomic_t irq_err_count;
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2009-03-04 18:56:05 +00:00
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/* Function pointer for generic interrupt vector handling */
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2009-10-14 14:22:57 +00:00
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void (*x86_platform_ipi_callback)(void) = NULL;
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2009-03-04 18:56:05 +00:00
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2008-10-16 10:18:50 +00:00
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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2009-04-12 16:47:39 +00:00
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if (printk_ratelimit())
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pr_err("unexpected IRQ trap at vector %02x\n", irq);
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2008-10-16 10:18:50 +00:00
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/*
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* Currently unexpected vectors happen only on SMP and APIC.
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* We _must_ ack these because every local APIC has only N
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* irq slots per priority level, and a 'hanging, unacked' IRQ
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* holds up an irq slot - in excessive cases (when multiple
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* unexpected vectors occur) that might lock up the APIC
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* completely.
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* But only ack when the APIC is enabled -AK
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*/
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2009-04-12 16:47:41 +00:00
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ack_APIC_irq();
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2008-10-16 10:18:50 +00:00
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}
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2009-01-18 15:38:57 +00:00
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#define irq_stats(x) (&per_cpu(irq_stat, x))
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2008-10-16 09:32:24 +00:00
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/*
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* /proc/interrupts printing:
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*/
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2009-03-12 12:45:15 +00:00
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static int show_other_interrupts(struct seq_file *p, int prec)
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2008-10-16 09:32:24 +00:00
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{
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int j;
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*s: ", prec, "NMI");
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2008-10-16 09:32:24 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
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seq_printf(p, " Non-maskable interrupts\n");
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#ifdef CONFIG_X86_LOCAL_APIC
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*s: ", prec, "LOC");
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2008-10-16 09:32:24 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
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seq_printf(p, " Local timer interrupts\n");
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2009-03-22 20:38:34 +00:00
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seq_printf(p, "%*s: ", prec, "SPU");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
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seq_printf(p, " Spurious interrupts\n");
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2009-03-25 01:50:34 +00:00
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seq_printf(p, "%*s: ", prec, "CNT");
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2008-12-03 09:39:53 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
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seq_printf(p, " Performance counter interrupts\n");
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2009-04-13 19:24:50 +00:00
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seq_printf(p, "%*s: ", prec, "PND");
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2009-04-06 09:45:03 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_pending_irqs);
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seq_printf(p, " Performance pending work\n");
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2008-10-16 09:32:24 +00:00
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#endif
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2009-10-14 14:22:57 +00:00
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if (x86_platform_ipi_callback) {
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2009-03-25 01:50:34 +00:00
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seq_printf(p, "%*s: ", prec, "PLT");
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2009-03-04 18:56:05 +00:00
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for_each_online_cpu(j)
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2009-10-14 14:22:57 +00:00
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seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
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2009-03-04 18:56:05 +00:00
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seq_printf(p, " Platform interrupts\n");
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}
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2008-10-16 09:32:24 +00:00
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#ifdef CONFIG_SMP
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*s: ", prec, "RES");
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2008-10-16 09:32:24 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
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seq_printf(p, " Rescheduling interrupts\n");
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*s: ", prec, "CAL");
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2008-10-16 09:32:24 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
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seq_printf(p, " Function call interrupts\n");
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*s: ", prec, "TLB");
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2008-10-16 09:32:24 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
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seq_printf(p, " TLB shootdowns\n");
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#endif
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#ifdef CONFIG_X86_MCE
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*s: ", prec, "TRM");
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2008-10-16 09:32:24 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
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seq_printf(p, " Thermal event interrupts\n");
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x86, mce: use 64bit machine check code on 32bit
The 64bit machine check code is in many ways much better than
the 32bit machine check code: it is more specification compliant,
is cleaner, only has a single code base versus one per CPU,
has better infrastructure for recovery, has a cleaner way to communicate
with user space etc. etc.
Use the 64bit code for 32bit too.
This is the second attempt to do this. There was one a couple of years
ago to unify this code for 32bit and 64bit. Back then this ran into some
trouble with K7s and was reverted.
I believe this time the K7 problems (and some others) are addressed.
I went over the old handlers and was very careful to retain
all quirks.
But of course this needs a lot of testing on old systems. On newer
64bit capable systems I don't expect much problems because they have been
already tested with the 64bit kernel.
I made this a CONFIG for now that still allows to select the old
machine check code. This is mostly to make testing easier,
if someone runs into a problem we can ask them to try
with the CONFIG switched.
The new code is default y for more coverage.
Once there is confidence the 64bit code works well on older hardware
too the CONFIG_X86_OLD_MCE and the associated code can be easily
removed.
This causes a behaviour change for 32bit installations. They now
have to install the mcelog package to be able to log
corrected machine checks.
The 64bit machine check code only handles CPUs which support the
standard Intel machine check architecture described in the IA32 SDM.
The 32bit code has special support for some older CPUs which
have non standard machine check architectures, in particular
WinChip C3 and Intel P5. I made those a separate CONFIG option
and kept them for now. The WinChip variant could be probably
removed without too much pain, it doesn't really do anything
interesting. P5 is also disabled by default (like it
was before) because many motherboards have it miswired, but
according to Alan Cox a few embedded setups use that one.
Forward ported/heavily changed version of old patch, original patch
included review/fixes from Thomas Gleixner, Bert Wesarg.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-04-28 17:07:31 +00:00
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# ifdef CONFIG_X86_MCE_THRESHOLD
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*s: ", prec, "THR");
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2008-10-16 09:32:24 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
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seq_printf(p, " Threshold APIC interrupts\n");
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# endif
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2009-05-27 19:56:52 +00:00
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#endif
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2009-07-08 22:31:41 +00:00
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#ifdef CONFIG_X86_MCE
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2009-05-27 19:56:52 +00:00
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seq_printf(p, "%*s: ", prec, "MCE");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
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seq_printf(p, " Machine check exceptions\n");
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2009-05-27 19:56:57 +00:00
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seq_printf(p, "%*s: ", prec, "MCP");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
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seq_printf(p, " Machine check polls\n");
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2008-10-16 09:32:24 +00:00
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#endif
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
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2008-10-16 09:32:24 +00:00
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#if defined(CONFIG_X86_IO_APIC)
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
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2008-10-16 09:32:24 +00:00
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#endif
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return 0;
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}
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int show_interrupts(struct seq_file *p, void *v)
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{
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unsigned long flags, any_count = 0;
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2009-03-12 12:45:15 +00:00
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int i = *(loff_t *) v, j, prec;
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2008-10-16 09:32:24 +00:00
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struct irqaction *action;
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struct irq_desc *desc;
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if (i > nr_irqs)
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return 0;
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2009-03-12 12:45:15 +00:00
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for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
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j *= 10;
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2008-10-16 09:32:24 +00:00
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if (i == nr_irqs)
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2009-03-12 12:45:15 +00:00
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return show_other_interrupts(p, prec);
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2008-10-16 09:32:24 +00:00
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/* print header */
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if (i == 0) {
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*s", prec + 8, "");
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2008-10-16 09:32:24 +00:00
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for_each_online_cpu(j)
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2008-10-21 13:49:59 +00:00
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seq_printf(p, "CPU%-8d", j);
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2008-10-16 09:32:24 +00:00
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seq_putc(p, '\n');
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}
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desc = irq_to_desc(i);
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2008-12-06 02:58:31 +00:00
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if (!desc)
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return 0;
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2008-10-16 09:32:24 +00:00
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spin_lock_irqsave(&desc->lock, flags);
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for_each_online_cpu(j)
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any_count |= kstat_irqs_cpu(i, j);
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action = desc->action;
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if (!action && !any_count)
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goto out;
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2009-03-12 12:45:15 +00:00
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seq_printf(p, "%*d: ", prec, i);
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2008-10-16 09:32:24 +00:00
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
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seq_printf(p, " %8s", desc->chip->name);
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seq_printf(p, "-%-8s", desc->name);
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if (action) {
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seq_printf(p, " %s", action->name);
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while ((action = action->next) != NULL)
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seq_printf(p, ", %s", action->name);
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}
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seq_putc(p, '\n');
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out:
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spin_unlock_irqrestore(&desc->lock, flags);
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return 0;
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}
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/*
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* /proc/stat helpers
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*/
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u64 arch_irq_stat_cpu(unsigned int cpu)
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{
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u64 sum = irq_stats(cpu)->__nmi_count;
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#ifdef CONFIG_X86_LOCAL_APIC
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sum += irq_stats(cpu)->apic_timer_irqs;
|
2009-03-22 20:38:34 +00:00
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sum += irq_stats(cpu)->irq_spurious_count;
|
2008-12-03 09:39:53 +00:00
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sum += irq_stats(cpu)->apic_perf_irqs;
|
2009-04-06 09:45:03 +00:00
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sum += irq_stats(cpu)->apic_pending_irqs;
|
2008-10-16 09:32:24 +00:00
|
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#endif
|
2009-10-14 14:22:57 +00:00
|
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if (x86_platform_ipi_callback)
|
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sum += irq_stats(cpu)->x86_platform_ipis;
|
2008-10-16 09:32:24 +00:00
|
|
|
#ifdef CONFIG_SMP
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sum += irq_stats(cpu)->irq_resched_count;
|
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sum += irq_stats(cpu)->irq_call_count;
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sum += irq_stats(cpu)->irq_tlb_count;
|
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#endif
|
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#ifdef CONFIG_X86_MCE
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sum += irq_stats(cpu)->irq_thermal_count;
|
x86, mce: use 64bit machine check code on 32bit
The 64bit machine check code is in many ways much better than
the 32bit machine check code: it is more specification compliant,
is cleaner, only has a single code base versus one per CPU,
has better infrastructure for recovery, has a cleaner way to communicate
with user space etc. etc.
Use the 64bit code for 32bit too.
This is the second attempt to do this. There was one a couple of years
ago to unify this code for 32bit and 64bit. Back then this ran into some
trouble with K7s and was reverted.
I believe this time the K7 problems (and some others) are addressed.
I went over the old handlers and was very careful to retain
all quirks.
But of course this needs a lot of testing on old systems. On newer
64bit capable systems I don't expect much problems because they have been
already tested with the 64bit kernel.
I made this a CONFIG for now that still allows to select the old
machine check code. This is mostly to make testing easier,
if someone runs into a problem we can ask them to try
with the CONFIG switched.
The new code is default y for more coverage.
Once there is confidence the 64bit code works well on older hardware
too the CONFIG_X86_OLD_MCE and the associated code can be easily
removed.
This causes a behaviour change for 32bit installations. They now
have to install the mcelog package to be able to log
corrected machine checks.
The 64bit machine check code only handles CPUs which support the
standard Intel machine check architecture described in the IA32 SDM.
The 32bit code has special support for some older CPUs which
have non standard machine check architectures, in particular
WinChip C3 and Intel P5. I made those a separate CONFIG option
and kept them for now. The WinChip variant could be probably
removed without too much pain, it doesn't really do anything
interesting. P5 is also disabled by default (like it
was before) because many motherboards have it miswired, but
according to Alan Cox a few embedded setups use that one.
Forward ported/heavily changed version of old patch, original patch
included review/fixes from Thomas Gleixner, Bert Wesarg.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2009-04-28 17:07:31 +00:00
|
|
|
# ifdef CONFIG_X86_MCE_THRESHOLD
|
2008-10-16 09:32:24 +00:00
|
|
|
sum += irq_stats(cpu)->irq_threshold_count;
|
2009-04-12 16:47:39 +00:00
|
|
|
# endif
|
2009-06-02 07:53:23 +00:00
|
|
|
#endif
|
2009-07-08 22:31:41 +00:00
|
|
|
#ifdef CONFIG_X86_MCE
|
2009-06-02 07:53:23 +00:00
|
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|
sum += per_cpu(mce_exception_count, cpu);
|
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|
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sum += per_cpu(mce_poll_count, cpu);
|
2008-10-16 09:32:24 +00:00
|
|
|
#endif
|
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|
|
return sum;
|
|
|
|
}
|
|
|
|
|
|
|
|
u64 arch_irq_stat(void)
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|
|
{
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|
|
u64 sum = atomic_read(&irq_err_count);
|
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|
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|
|
#ifdef CONFIG_X86_IO_APIC
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|
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sum += atomic_read(&irq_mis_count);
|
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|
|
#endif
|
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|
|
return sum;
|
|
|
|
}
|
2008-12-23 14:15:17 +00:00
|
|
|
|
2009-02-06 22:09:41 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* do_IRQ handles all normal device IRQ's (the special
|
|
|
|
* SMP cross-CPU interrupts have their own specific
|
|
|
|
* handlers).
|
|
|
|
*/
|
|
|
|
unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
struct pt_regs *old_regs = set_irq_regs(regs);
|
|
|
|
|
|
|
|
/* high bit used in ret_from_ code */
|
|
|
|
unsigned vector = ~regs->orig_ax;
|
|
|
|
unsigned irq;
|
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|
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|
|
exit_idle();
|
|
|
|
irq_enter();
|
|
|
|
|
|
|
|
irq = __get_cpu_var(vector_irq)[vector];
|
|
|
|
|
|
|
|
if (!handle_irq(irq, regs)) {
|
2009-04-12 16:47:41 +00:00
|
|
|
ack_APIC_irq();
|
2009-02-06 22:09:41 +00:00
|
|
|
|
|
|
|
if (printk_ratelimit())
|
2009-04-12 16:47:39 +00:00
|
|
|
pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
|
|
|
|
__func__, smp_processor_id(), vector, irq);
|
2009-02-06 22:09:41 +00:00
|
|
|
}
|
|
|
|
|
2009-10-08 13:40:41 +00:00
|
|
|
run_local_timers();
|
2009-02-06 22:09:41 +00:00
|
|
|
irq_exit();
|
|
|
|
|
|
|
|
set_irq_regs(old_regs);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2009-03-04 18:56:05 +00:00
|
|
|
/*
|
2009-10-14 14:22:57 +00:00
|
|
|
* Handler for X86_PLATFORM_IPI_VECTOR.
|
2009-03-04 18:56:05 +00:00
|
|
|
*/
|
2009-10-14 14:22:57 +00:00
|
|
|
void smp_x86_platform_ipi(struct pt_regs *regs)
|
2009-03-04 18:56:05 +00:00
|
|
|
{
|
|
|
|
struct pt_regs *old_regs = set_irq_regs(regs);
|
|
|
|
|
|
|
|
ack_APIC_irq();
|
|
|
|
|
|
|
|
exit_idle();
|
|
|
|
|
|
|
|
irq_enter();
|
|
|
|
|
2009-10-14 14:22:57 +00:00
|
|
|
inc_irq_stat(x86_platform_ipis);
|
2009-03-04 18:56:05 +00:00
|
|
|
|
2009-10-14 14:22:57 +00:00
|
|
|
if (x86_platform_ipi_callback)
|
|
|
|
x86_platform_ipi_callback();
|
2009-03-04 18:56:05 +00:00
|
|
|
|
2009-10-08 13:40:41 +00:00
|
|
|
run_local_timers();
|
2009-03-04 18:56:05 +00:00
|
|
|
irq_exit();
|
|
|
|
|
|
|
|
set_irq_regs(old_regs);
|
|
|
|
}
|
|
|
|
|
2008-12-23 14:15:17 +00:00
|
|
|
EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
|