2019-05-19 12:08:55 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2015-03-02 22:22:59 +00:00
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/*
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* HD-audio core bus driver
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*/
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#include <linux/init.h>
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2019-08-09 02:54:58 +00:00
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#include <linux/io.h>
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2015-03-02 22:22:59 +00:00
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/export.h>
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#include <sound/hdaudio.h>
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2019-08-14 16:27:08 +00:00
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#include "local.h"
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2015-03-10 14:16:28 +00:00
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#include "trace.h"
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2015-03-02 22:22:59 +00:00
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2019-08-14 17:59:44 +00:00
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static void snd_hdac_bus_process_unsol_events(struct work_struct *work);
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2015-04-14 10:15:47 +00:00
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static const struct hdac_bus_ops default_ops = {
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.command = snd_hdac_bus_send_cmd,
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.get_response = snd_hdac_bus_get_response,
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2021-02-05 18:46:28 +00:00
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.link_power = snd_hdac_bus_link_power,
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2015-04-14 10:15:47 +00:00
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};
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2015-03-02 22:22:59 +00:00
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/**
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* snd_hdac_bus_init - initialize a HD-audio bas bus
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* @bus: the pointer to bus object
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2020-01-13 20:56:38 +00:00
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* @dev: device pointer
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2015-04-14 10:15:47 +00:00
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* @ops: bus verb operators
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2015-03-02 22:22:59 +00:00
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*
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* Returns 0 if successful, or a negative error code.
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*/
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int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
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2019-08-07 18:32:08 +00:00
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const struct hdac_bus_ops *ops)
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2015-03-02 22:22:59 +00:00
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{
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memset(bus, 0, sizeof(*bus));
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bus->dev = dev;
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2015-04-14 10:15:47 +00:00
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if (ops)
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bus->ops = ops;
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else
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bus->ops = &default_ops;
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2019-08-07 18:02:31 +00:00
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bus->dma_type = SNDRV_DMA_TYPE_DEV;
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2015-04-14 10:15:47 +00:00
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INIT_LIST_HEAD(&bus->stream_list);
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2015-03-02 22:22:59 +00:00
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INIT_LIST_HEAD(&bus->codec_list);
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2018-12-11 21:30:27 +00:00
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INIT_WORK(&bus->unsol_work, snd_hdac_bus_process_unsol_events);
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2015-04-14 10:15:47 +00:00
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spin_lock_init(&bus->reg_lock);
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2015-03-02 22:22:59 +00:00
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mutex_init(&bus->cmd_mutex);
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2019-04-10 10:49:55 +00:00
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mutex_init(&bus->lock);
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2019-04-10 14:00:54 +00:00
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INIT_LIST_HEAD(&bus->hlink_list);
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2019-12-10 14:57:27 +00:00
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init_waitqueue_head(&bus->rirb_wq);
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2015-04-14 10:15:47 +00:00
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bus->irq = -1;
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2020-08-19 15:32:10 +00:00
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/*
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* Default value of '8' is as per the HD audio specification (Rev 1.0a).
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* Following relation is used to derive STRIPE control value.
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* For sample rate <= 48K:
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* { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
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* For sample rate > 48K:
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* { ((num_channels * bits_per_sample * rate/48000) /
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* number of SDOs) >= 8 }
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*/
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bus->sdo_limit = 8;
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2015-03-02 22:22:59 +00:00
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return 0;
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}
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EXPORT_SYMBOL_GPL(snd_hdac_bus_init);
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/**
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* snd_hdac_bus_exit - clean up a HD-audio bas bus
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* @bus: the pointer to bus object
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*/
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void snd_hdac_bus_exit(struct hdac_bus *bus)
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{
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2015-04-14 10:15:47 +00:00
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WARN_ON(!list_empty(&bus->stream_list));
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2015-03-02 22:22:59 +00:00
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WARN_ON(!list_empty(&bus->codec_list));
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cancel_work_sync(&bus->unsol_work);
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}
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EXPORT_SYMBOL_GPL(snd_hdac_bus_exit);
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/**
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* snd_hdac_bus_exec_verb - execute a HD-audio verb on the given bus
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* @bus: bus object
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2020-01-13 20:56:38 +00:00
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* @addr: the HDAC device address
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2015-03-02 22:22:59 +00:00
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* @cmd: HD-audio encoded verb
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* @res: pointer to store the response, NULL if performing asynchronously
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*
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* Returns 0 if successful, or a negative error code.
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*/
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int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr,
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unsigned int cmd, unsigned int *res)
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{
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int err;
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mutex_lock(&bus->cmd_mutex);
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err = snd_hdac_bus_exec_verb_unlocked(bus, addr, cmd, res);
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mutex_unlock(&bus->cmd_mutex);
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return err;
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}
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/**
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* snd_hdac_bus_exec_verb_unlocked - unlocked version
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* @bus: bus object
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2020-01-13 20:56:38 +00:00
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* @addr: the HDAC device address
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2015-03-02 22:22:59 +00:00
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* @cmd: HD-audio encoded verb
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* @res: pointer to store the response, NULL if performing asynchronously
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*
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* Returns 0 if successful, or a negative error code.
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*/
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int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
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unsigned int cmd, unsigned int *res)
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{
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unsigned int tmp;
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int err;
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if (cmd == ~0)
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return -EINVAL;
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if (res)
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*res = -1;
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else if (bus->sync_write)
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res = &tmp;
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for (;;) {
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2015-03-10 14:16:28 +00:00
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trace_hda_send_cmd(bus, cmd);
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2015-03-02 22:22:59 +00:00
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err = bus->ops->command(bus, cmd);
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if (err != -EAGAIN)
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break;
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/* process pending verbs */
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err = bus->ops->get_response(bus, addr, &tmp);
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if (err)
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break;
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}
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2015-03-10 14:16:28 +00:00
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if (!err && res) {
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2015-03-02 22:22:59 +00:00
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err = bus->ops->get_response(bus, addr, res);
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2015-03-10 14:16:28 +00:00
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trace_hda_get_response(bus, addr, *res);
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}
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2015-03-02 22:22:59 +00:00
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return err;
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}
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EXPORT_SYMBOL_GPL(snd_hdac_bus_exec_verb_unlocked);
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/**
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* snd_hdac_bus_queue_event - add an unsolicited event to queue
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* @bus: the BUS
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* @res: unsolicited event (lower 32bit of RIRB entry)
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* @res_ex: codec addr and flags (upper 32bit or RIRB entry)
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*
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* Adds the given event to the queue. The events are processed in
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* the workqueue asynchronously. Call this function in the interrupt
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* hanlder when RIRB receives an unsolicited event.
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*/
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void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex)
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{
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unsigned int wp;
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if (!bus)
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return;
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2015-03-10 14:16:28 +00:00
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trace_hda_unsol_event(bus, res, res_ex);
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2015-03-02 22:22:59 +00:00
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wp = (bus->unsol_wp + 1) % HDA_UNSOL_QUEUE_SIZE;
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bus->unsol_wp = wp;
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wp <<= 1;
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bus->unsol_queue[wp] = res;
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bus->unsol_queue[wp + 1] = res_ex;
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schedule_work(&bus->unsol_work);
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}
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/*
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* process queued unsolicited events
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*/
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2019-08-14 17:59:44 +00:00
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static void snd_hdac_bus_process_unsol_events(struct work_struct *work)
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2015-03-02 22:22:59 +00:00
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{
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struct hdac_bus *bus = container_of(work, struct hdac_bus, unsol_work);
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struct hdac_device *codec;
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struct hdac_driver *drv;
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unsigned int rp, caddr, res;
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2020-05-16 06:25:56 +00:00
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spin_lock_irq(&bus->reg_lock);
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2015-03-02 22:22:59 +00:00
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while (bus->unsol_rp != bus->unsol_wp) {
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rp = (bus->unsol_rp + 1) % HDA_UNSOL_QUEUE_SIZE;
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bus->unsol_rp = rp;
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rp <<= 1;
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res = bus->unsol_queue[rp];
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caddr = bus->unsol_queue[rp + 1];
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if (!(caddr & (1 << 4))) /* no unsolicited event? */
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continue;
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codec = bus->caddr_tbl[caddr & 0x0f];
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if (!codec || !codec->dev.driver)
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continue;
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2020-05-16 06:25:56 +00:00
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spin_unlock_irq(&bus->reg_lock);
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2015-03-02 22:22:59 +00:00
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drv = drv_to_hdac_driver(codec->dev.driver);
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if (drv->unsol_event)
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drv->unsol_event(codec, res);
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2020-05-16 06:25:56 +00:00
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spin_lock_irq(&bus->reg_lock);
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2015-03-02 22:22:59 +00:00
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}
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2020-05-16 06:25:56 +00:00
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spin_unlock_irq(&bus->reg_lock);
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2015-03-02 22:22:59 +00:00
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}
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2015-10-28 11:26:48 +00:00
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/**
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* snd_hdac_bus_add_device - Add a codec to bus
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* @bus: HDA core bus
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* @codec: HDA core device to add
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*
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* Adds the given codec to the list in the bus. The caddr_tbl array
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* and codec_powered bits are updated, as well.
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* Returns zero if success, or a negative error code.
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*/
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2015-03-02 22:22:59 +00:00
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int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec)
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{
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if (bus->caddr_tbl[codec->addr]) {
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dev_err(bus->dev, "address 0x%x is already occupied\n",
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codec->addr);
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return -EBUSY;
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}
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list_add_tail(&codec->list, &bus->codec_list);
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bus->caddr_tbl[codec->addr] = codec;
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set_bit(codec->addr, &bus->codec_powered);
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bus->num_codecs++;
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return 0;
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}
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2015-10-28 11:26:48 +00:00
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/**
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* snd_hdac_bus_remove_device - Remove a codec from bus
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* @bus: HDA core bus
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* @codec: HDA core device to remove
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*/
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2015-03-02 22:22:59 +00:00
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void snd_hdac_bus_remove_device(struct hdac_bus *bus,
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struct hdac_device *codec)
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{
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WARN_ON(bus != codec->bus);
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if (list_empty(&codec->list))
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return;
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list_del_init(&codec->list);
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bus->caddr_tbl[codec->addr] = NULL;
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clear_bit(codec->addr, &bus->codec_powered);
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bus->num_codecs--;
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2017-06-19 15:49:48 +00:00
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flush_work(&bus->unsol_work);
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2015-03-02 22:22:59 +00:00
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}
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2019-08-07 18:32:08 +00:00
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#ifdef CONFIG_SND_HDA_ALIGNED_MMIO
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/* Helpers for aligned read/write of mmio space, for Tegra */
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unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask)
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{
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void __iomem *aligned_addr =
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(void __iomem *)((unsigned long)(addr) & ~0x3);
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unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
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unsigned int v;
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v = readl(aligned_addr);
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return (v >> shift) & mask;
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}
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EXPORT_SYMBOL_GPL(snd_hdac_aligned_read);
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void snd_hdac_aligned_write(unsigned int val, void __iomem *addr,
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unsigned int mask)
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{
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void __iomem *aligned_addr =
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(void __iomem *)((unsigned long)(addr) & ~0x3);
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unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
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unsigned int v;
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v = readl(aligned_addr);
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v &= ~(mask << shift);
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v |= val << shift;
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writel(v, aligned_addr);
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}
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EXPORT_SYMBOL_GPL(snd_hdac_aligned_write);
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#endif /* CONFIG_SND_HDA_ALIGNED_MMIO */
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2021-02-05 18:46:28 +00:00
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void snd_hdac_codec_link_up(struct hdac_device *codec)
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{
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struct hdac_bus *bus = codec->bus;
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if (bus->ops->link_power)
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bus->ops->link_power(codec, true);
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else
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snd_hdac_bus_link_power(codec, true);
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}
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EXPORT_SYMBOL_GPL(snd_hdac_codec_link_up);
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void snd_hdac_codec_link_down(struct hdac_device *codec)
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{
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struct hdac_bus *bus = codec->bus;
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if (bus->ops->link_power)
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bus->ops->link_power(codec, false);
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else
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snd_hdac_bus_link_power(codec, false);
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}
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EXPORT_SYMBOL_GPL(snd_hdac_codec_link_down);
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