2016-01-25 18:47:07 +00:00
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/*
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* Copyright (c) 2016 Linaro Ltd.
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* Copyright (c) 2016 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include "hisi_sas.h"
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#define DRV_NAME "hisi_sas_v2_hw"
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2016-01-25 18:47:08 +00:00
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/* global registers need init*/
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#define DLVRY_QUEUE_ENABLE 0x0
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#define IOST_BASE_ADDR_LO 0x8
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#define IOST_BASE_ADDR_HI 0xc
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#define ITCT_BASE_ADDR_LO 0x10
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#define ITCT_BASE_ADDR_HI 0x14
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#define IO_BROKEN_MSG_ADDR_LO 0x18
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#define IO_BROKEN_MSG_ADDR_HI 0x1c
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#define PHY_CONTEXT 0x20
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#define PHY_STATE 0x24
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#define PHY_PORT_NUM_MA 0x28
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#define PORT_STATE 0x2c
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#define PORT_STATE_PHY8_PORT_NUM_OFF 16
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#define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
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#define PORT_STATE_PHY8_CONN_RATE_OFF 20
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#define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
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#define PHY_CONN_RATE 0x30
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#define HGC_TRANS_TASK_CNT_LIMIT 0x38
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#define AXI_AHB_CLK_CFG 0x3c
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#define ITCT_CLR 0x44
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#define ITCT_CLR_EN_OFF 16
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#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
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#define ITCT_DEV_OFF 0
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#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
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#define AXI_USER1 0x48
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#define AXI_USER2 0x4c
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#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
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#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
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#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
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#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
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#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
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#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
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#define HGC_GET_ITV_TIME 0x90
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#define DEVICE_MSG_WORK_MODE 0x94
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#define OPENA_WT_CONTI_TIME 0x9c
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#define I_T_NEXUS_LOSS_TIME 0xa0
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#define MAX_CON_TIME_LIMIT_TIME 0xa4
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#define BUS_INACTIVE_LIMIT_TIME 0xa8
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#define REJECT_TO_OPEN_LIMIT_TIME 0xac
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#define CFG_AGING_TIME 0xbc
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#define HGC_DFX_CFG2 0xc0
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#define HGC_IOMB_PROC1_STATUS 0x104
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#define CFG_1US_TIMER_TRSH 0xcc
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#define HGC_INVLD_DQE_INFO 0x148
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#define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
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#define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
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#define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
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#define INT_COAL_EN 0x19c
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#define OQ_INT_COAL_TIME 0x1a0
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#define OQ_INT_COAL_CNT 0x1a4
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#define ENT_INT_COAL_TIME 0x1a8
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#define ENT_INT_COAL_CNT 0x1ac
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#define OQ_INT_SRC 0x1b0
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#define OQ_INT_SRC_MSK 0x1b4
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#define ENT_INT_SRC1 0x1b8
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#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
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#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
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#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
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#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
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#define ENT_INT_SRC2 0x1bc
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#define ENT_INT_SRC3 0x1c0
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#define ENT_INT_SRC3_ITC_INT_OFF 15
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#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
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#define ENT_INT_SRC_MSK1 0x1c4
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#define ENT_INT_SRC_MSK2 0x1c8
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#define ENT_INT_SRC_MSK3 0x1cc
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#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
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#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
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#define SAS_ECC_INTR_MSK 0x1ec
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#define HGC_ERR_STAT_EN 0x238
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#define DLVRY_Q_0_BASE_ADDR_LO 0x260
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#define DLVRY_Q_0_BASE_ADDR_HI 0x264
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#define DLVRY_Q_0_DEPTH 0x268
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#define DLVRY_Q_0_WR_PTR 0x26c
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#define DLVRY_Q_0_RD_PTR 0x270
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#define HYPER_STREAM_ID_EN_CFG 0xc80
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#define OQ0_INT_SRC_MSK 0xc90
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#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
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#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
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#define COMPL_Q_0_DEPTH 0x4e8
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#define COMPL_Q_0_WR_PTR 0x4ec
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#define COMPL_Q_0_RD_PTR 0x4f0
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/* phy registers need init */
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#define PORT_BASE (0x2000)
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#define PHY_CFG (PORT_BASE + 0x0)
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#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
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#define PHY_CFG_ENA_OFF 0
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#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
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#define PHY_CFG_DC_OPT_OFF 2
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#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
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#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
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#define PROG_PHY_LINK_RATE_MAX_OFF 0
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#define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
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#define PHY_CTRL (PORT_BASE + 0x14)
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#define PHY_CTRL_RESET_OFF 0
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#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
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#define SAS_PHY_CTRL (PORT_BASE + 0x20)
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#define SL_CFG (PORT_BASE + 0x84)
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#define PHY_PCN (PORT_BASE + 0x44)
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#define SL_TOUT_CFG (PORT_BASE + 0x8c)
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#define SL_CONTROL (PORT_BASE + 0x94)
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#define SL_CONTROL_NOTIFY_EN_OFF 0
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#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
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#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
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#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
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#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
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#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
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#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
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#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
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#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
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#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
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#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
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#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
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#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
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#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
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#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
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#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
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#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
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#define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
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#define CHL_INT0 (PORT_BASE + 0x1b4)
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#define CHL_INT0_HOTPLUG_TOUT_OFF 0
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#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
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#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
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#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
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#define CHL_INT0_SL_PHY_ENABLE_OFF 2
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#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
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#define CHL_INT0_NOT_RDY_OFF 4
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#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
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#define CHL_INT0_PHY_RDY_OFF 5
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#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
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#define CHL_INT1 (PORT_BASE + 0x1b8)
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#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
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#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
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#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
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#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
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#define CHL_INT2 (PORT_BASE + 0x1bc)
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#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
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#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
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#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
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#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
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#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
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#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
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#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
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#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
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#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
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#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
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#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
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#define DMA_TX_STATUS_BUSY_OFF 0
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#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
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#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
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#define DMA_RX_STATUS_BUSY_OFF 0
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#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
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#define AXI_CFG (0x5100)
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#define AM_CFG_MAX_TRANS (0x5010)
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#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
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/* HW dma structures */
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/* Delivery queue header */
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/* dw0 */
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#define CMD_HDR_RESP_REPORT_OFF 5
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#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
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#define CMD_HDR_TLR_CTRL_OFF 6
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#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
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#define CMD_HDR_PORT_OFF 18
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#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
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#define CMD_HDR_PRIORITY_OFF 27
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#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
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#define CMD_HDR_CMD_OFF 29
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#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
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/* dw1 */
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#define CMD_HDR_DIR_OFF 5
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#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
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#define CMD_HDR_RESET_OFF 7
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#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
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#define CMD_HDR_VDTL_OFF 10
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#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
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#define CMD_HDR_FRAME_TYPE_OFF 11
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#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
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#define CMD_HDR_DEV_ID_OFF 16
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#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
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/* dw2 */
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#define CMD_HDR_CFL_OFF 0
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#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
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#define CMD_HDR_NCQ_TAG_OFF 10
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#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
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#define CMD_HDR_MRFL_OFF 15
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#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
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#define CMD_HDR_SG_MOD_OFF 24
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#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
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#define CMD_HDR_FIRST_BURST_OFF 26
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#define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
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/* dw3 */
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#define CMD_HDR_IPTT_OFF 0
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#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
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/* dw6 */
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#define CMD_HDR_DIF_SGL_LEN_OFF 0
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#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
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#define CMD_HDR_DATA_SGL_LEN_OFF 16
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#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
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/* Completion header */
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/* dw0 */
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#define CMPLT_HDR_RSPNS_XFRD_OFF 10
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#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
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#define CMPLT_HDR_ERX_OFF 12
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#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
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/* dw1 */
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#define CMPLT_HDR_IPTT_OFF 0
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#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
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#define CMPLT_HDR_DEV_ID_OFF 16
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#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
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/* ITCT header */
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/* qw0 */
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#define ITCT_HDR_DEV_TYPE_OFF 0
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#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
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#define ITCT_HDR_VALID_OFF 2
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#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
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#define ITCT_HDR_MCR_OFF 5
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#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
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#define ITCT_HDR_VLN_OFF 9
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#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
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#define ITCT_HDR_PORT_ID_OFF 28
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#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
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/* qw2 */
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#define ITCT_HDR_INLT_OFF 0
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#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
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#define ITCT_HDR_BITLT_OFF 16
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#define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
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#define ITCT_HDR_MCTLT_OFF 32
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#define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
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#define ITCT_HDR_RTOLT_OFF 48
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#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
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2016-01-25 18:47:07 +00:00
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static const struct hisi_sas_hw hisi_sas_v2_hw = {
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};
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static int hisi_sas_v2_probe(struct platform_device *pdev)
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{
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return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
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}
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static int hisi_sas_v2_remove(struct platform_device *pdev)
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{
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return hisi_sas_remove(pdev);
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}
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static const struct of_device_id sas_v2_of_match[] = {
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{ .compatible = "hisilicon,hip06-sas-v2",},
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{},
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};
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MODULE_DEVICE_TABLE(of, sas_v2_of_match);
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static struct platform_driver hisi_sas_v2_driver = {
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.probe = hisi_sas_v2_probe,
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.remove = hisi_sas_v2_remove,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = sas_v2_of_match,
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},
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};
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module_platform_driver(hisi_sas_v2_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
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MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
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MODULE_ALIAS("platform:" DRV_NAME);
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