2007-07-12 14:41:45 +00:00
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/*
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2009-09-24 14:11:24 +00:00
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* simple DMA Implementation for Blackfin
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2007-07-12 14:41:45 +00:00
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*
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2009-09-24 14:11:24 +00:00
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* Copyright 2007-2009 Analog Devices Inc.
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2007-07-12 14:41:45 +00:00
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*
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2009-09-24 14:11:24 +00:00
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* Licensed under the GPL-2 or later.
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2007-07-12 14:41:45 +00:00
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*/
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2009-09-24 14:11:24 +00:00
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2008-04-23 21:23:31 +00:00
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#include <linux/module.h>
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2007-07-12 14:41:45 +00:00
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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2010-10-25 18:11:09 +00:00
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struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
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2007-07-12 14:41:45 +00:00
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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(struct dma_register *) DMA3_NEXT_DESC_PTR,
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(struct dma_register *) DMA4_NEXT_DESC_PTR,
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(struct dma_register *) DMA5_NEXT_DESC_PTR,
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(struct dma_register *) DMA6_NEXT_DESC_PTR,
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(struct dma_register *) DMA7_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
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(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
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};
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2008-04-23 21:31:18 +00:00
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EXPORT_SYMBOL(dma_io_base_addr);
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2007-07-12 14:41:45 +00:00
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2007-06-21 03:34:16 +00:00
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int channel2irq(unsigned int channel)
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2007-07-12 14:41:45 +00:00
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{
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int ret_irq = -1;
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switch (channel) {
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case CH_PPI:
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ret_irq = IRQ_PPI;
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break;
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case CH_SPORT0_RX:
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ret_irq = IRQ_SPORT0_RX;
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break;
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case CH_SPORT0_TX:
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ret_irq = IRQ_SPORT0_TX;
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break;
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case CH_SPORT1_RX:
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ret_irq = IRQ_SPORT1_RX;
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break;
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case CH_SPORT1_TX:
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ret_irq = IRQ_SPORT1_TX;
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break;
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case CH_SPI:
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ret_irq = IRQ_SPI;
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break;
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2009-07-27 00:44:25 +00:00
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case CH_UART0_RX:
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ret_irq = IRQ_UART0_RX;
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2007-07-12 14:41:45 +00:00
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break;
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2009-07-27 00:44:25 +00:00
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case CH_UART0_TX:
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ret_irq = IRQ_UART0_TX;
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2007-07-12 14:41:45 +00:00
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break;
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case CH_MEM_STREAM0_SRC:
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case CH_MEM_STREAM0_DEST:
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ret_irq = IRQ_MEM_DMA0;
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break;
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case CH_MEM_STREAM1_SRC:
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case CH_MEM_STREAM1_DEST:
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ret_irq = IRQ_MEM_DMA1;
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break;
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}
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return ret_irq;
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}
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