2018-04-11 09:56:55 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2018-10-09 10:23:43 +00:00
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#include <linux/errno.h>
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2018-04-11 09:56:55 +00:00
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#include <linux/init.h>
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2021-06-15 07:20:26 +00:00
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#include <asm/setup.h>
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#include <asm/processor.h>
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2018-04-11 09:56:55 +00:00
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#include <asm/sclp.h>
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#include <asm/sections.h>
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#include <asm/mem_detect.h>
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2018-04-11 17:15:24 +00:00
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#include <asm/sparsemem.h>
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2022-04-23 19:31:22 +00:00
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#include "decompressor.h"
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2018-04-11 09:56:55 +00:00
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#include "boot.h"
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struct mem_detect_info __bootdata(mem_detect);
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/* up to 256 storage elements, 1020 subincrements each */
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#define ENTRIES_EXTENDED_MAX \
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(256 * (1020 / 2) * sizeof(struct mem_detect_block))
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/*
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* To avoid corrupting old kernel memory during dump, find lowest memory
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* chunk possible either right after the kernel end (decompressed kernel) or
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* after initrd (if it is present and there is no hole between the kernel end
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* and initrd)
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*/
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static void *mem_detect_alloc_extended(void)
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{
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unsigned long offset = ALIGN(mem_safe_offset(), sizeof(u64));
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2021-06-15 12:15:07 +00:00
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if (IS_ENABLED(CONFIG_BLK_DEV_INITRD) && initrd_data.start && initrd_data.size &&
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initrd_data.start < offset + ENTRIES_EXTENDED_MAX)
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offset = ALIGN(initrd_data.start + initrd_data.size, sizeof(u64));
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2018-04-11 09:56:55 +00:00
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return (void *)offset;
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}
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static struct mem_detect_block *__get_mem_detect_block_ptr(u32 n)
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{
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if (n < MEM_INLINED_ENTRIES)
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return &mem_detect.entries[n];
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if (unlikely(!mem_detect.entries_extended))
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mem_detect.entries_extended = mem_detect_alloc_extended();
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return &mem_detect.entries_extended[n - MEM_INLINED_ENTRIES];
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}
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/*
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* sequential calls to add_mem_detect_block with adjacent memory areas
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* are merged together into single memory block.
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*/
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void add_mem_detect_block(u64 start, u64 end)
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{
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struct mem_detect_block *block;
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if (mem_detect.count) {
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block = __get_mem_detect_block_ptr(mem_detect.count - 1);
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if (block->end == start) {
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block->end = end;
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return;
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}
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}
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block = __get_mem_detect_block_ptr(mem_detect.count);
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block->start = start;
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block->end = end;
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mem_detect.count++;
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}
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2018-04-11 16:48:20 +00:00
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static int __diag260(unsigned long rx1, unsigned long rx2)
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{
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2021-06-14 19:57:58 +00:00
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unsigned long reg1, reg2, ry;
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union register_pair rx;
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2021-06-14 19:40:43 +00:00
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psw_t old;
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2021-06-14 19:57:58 +00:00
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int rc;
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2018-04-11 16:48:20 +00:00
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2021-06-14 19:57:58 +00:00
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rx.even = rx1;
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rx.odd = rx2;
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ry = 0x10; /* storage configuration */
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rc = -1; /* fail */
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2018-04-11 16:48:20 +00:00
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asm volatile(
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2021-06-14 19:40:43 +00:00
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" mvc 0(16,%[psw_old]),0(%[psw_pgm])\n"
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2021-06-14 19:57:58 +00:00
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" epsw %[reg1],%[reg2]\n"
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" st %[reg1],0(%[psw_pgm])\n"
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" st %[reg2],4(%[psw_pgm])\n"
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" larl %[reg1],1f\n"
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" stg %[reg1],8(%[psw_pgm])\n"
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2018-04-11 16:48:20 +00:00
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" diag %[rx],%[ry],0x260\n"
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" ipm %[rc]\n"
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" srl %[rc],28\n"
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2021-06-14 19:40:43 +00:00
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"1: mvc 0(16,%[psw_pgm]),0(%[psw_old])\n"
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2021-06-14 19:57:58 +00:00
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: [reg1] "=&d" (reg1),
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[reg2] "=&a" (reg2),
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[rc] "+&d" (rc),
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[ry] "+&d" (ry),
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2021-06-14 19:40:43 +00:00
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"+Q" (S390_lowcore.program_new_psw),
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2021-06-14 19:57:58 +00:00
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"=Q" (old)
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: [rx] "d" (rx.pair),
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2021-06-14 19:40:43 +00:00
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[psw_old] "a" (&old),
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[psw_pgm] "a" (&S390_lowcore.program_new_psw)
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2018-04-11 16:48:20 +00:00
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: "cc", "memory");
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2021-06-14 19:57:58 +00:00
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return rc == 0 ? ry : -1;
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2018-04-11 16:48:20 +00:00
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}
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static int diag260(void)
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{
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int rc, i;
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struct {
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unsigned long start;
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unsigned long end;
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} storage_extents[8] __aligned(16); /* VM supports up to 8 extends */
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memset(storage_extents, 0, sizeof(storage_extents));
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rc = __diag260((unsigned long)storage_extents, sizeof(storage_extents));
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if (rc == -1)
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return -1;
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for (i = 0; i < min_t(int, rc, ARRAY_SIZE(storage_extents)); i++)
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add_mem_detect_block(storage_extents[i].start, storage_extents[i].end + 1);
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return 0;
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}
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2018-04-11 09:56:55 +00:00
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static int tprot(unsigned long addr)
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{
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2021-06-14 20:09:20 +00:00
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unsigned long reg1, reg2;
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2018-04-11 09:56:55 +00:00
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int rc = -EFAULT;
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2021-06-14 20:09:20 +00:00
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psw_t old;
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2018-04-11 09:56:55 +00:00
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asm volatile(
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2021-06-14 20:09:20 +00:00
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" mvc 0(16,%[psw_old]),0(%[psw_pgm])\n"
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" epsw %[reg1],%[reg2]\n"
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" st %[reg1],0(%[psw_pgm])\n"
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" st %[reg2],4(%[psw_pgm])\n"
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" larl %[reg1],1f\n"
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" stg %[reg1],8(%[psw_pgm])\n"
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2018-04-11 09:56:55 +00:00
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" tprot 0(%[addr]),0\n"
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" ipm %[rc]\n"
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" srl %[rc],28\n"
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2021-06-14 20:09:20 +00:00
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"1: mvc 0(16,%[psw_pgm]),0(%[psw_old])\n"
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: [reg1] "=&d" (reg1),
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[reg2] "=&a" (reg2),
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[rc] "+&d" (rc),
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"=Q" (S390_lowcore.program_new_psw.addr),
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"=Q" (old)
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: [psw_old] "a" (&old),
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[psw_pgm] "a" (&S390_lowcore.program_new_psw),
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[addr] "a" (addr)
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2018-04-11 09:56:55 +00:00
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: "cc", "memory");
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return rc;
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}
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2018-04-11 17:15:24 +00:00
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static void search_mem_end(void)
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2018-04-11 09:56:55 +00:00
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{
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2018-04-11 17:15:24 +00:00
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unsigned long range = 1 << (MAX_PHYSMEM_BITS - 20); /* in 1MB blocks */
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unsigned long offset = 0;
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unsigned long pivot;
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while (range > 1) {
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range >>= 1;
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pivot = offset + range;
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if (!tprot(pivot << 20))
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offset = pivot;
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}
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add_mem_detect_block(0, (offset + 1) << 20);
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2018-04-11 09:56:55 +00:00
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}
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2020-10-19 09:01:33 +00:00
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unsigned long detect_memory(void)
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2018-04-11 09:56:55 +00:00
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{
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2020-10-19 09:01:33 +00:00
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unsigned long max_physmem_end;
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2018-04-11 17:15:24 +00:00
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sclp_early_get_memsize(&max_physmem_end);
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2018-04-11 16:42:37 +00:00
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if (!sclp_early_read_storage_info()) {
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mem_detect.info_source = MEM_DETECT_SCLP_STOR_INFO;
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2020-10-19 09:01:33 +00:00
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return max_physmem_end;
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2018-04-11 16:42:37 +00:00
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}
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2018-04-11 16:48:20 +00:00
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if (!diag260()) {
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mem_detect.info_source = MEM_DETECT_DIAG260;
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2020-10-19 09:01:33 +00:00
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return max_physmem_end;
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2018-04-11 16:48:20 +00:00
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}
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2018-04-11 16:54:40 +00:00
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if (max_physmem_end) {
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add_mem_detect_block(0, max_physmem_end);
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mem_detect.info_source = MEM_DETECT_SCLP_READ_INFO;
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2020-10-19 09:01:33 +00:00
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return max_physmem_end;
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2018-04-11 16:54:40 +00:00
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}
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2018-04-11 17:15:24 +00:00
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search_mem_end();
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mem_detect.info_source = MEM_DETECT_BIN_SEARCH;
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2020-10-19 09:01:33 +00:00
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return get_mem_detect_end();
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2018-04-11 09:56:55 +00:00
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}
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