2019-05-27 06:55:06 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2017-03-13 19:07:26 +00:00
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/*
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2005-04-16 22:20:36 +00:00
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* Copyright (c) 2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 Watchdog Timer Support
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*
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* Based on, softdog.c by Alan Cox,
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2008-10-27 15:17:56 +00:00
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* (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
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2017-03-13 19:07:26 +00:00
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*/
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2005-04-16 22:20:36 +00:00
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/timer.h>
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#include <linux/watchdog.h>
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2005-10-29 18:07:23 +00:00
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#include <linux/platform_device.h>
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2005-04-16 22:20:36 +00:00
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#include <linux/interrupt.h>
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2006-01-07 16:15:52 +00:00
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#include <linux/clk.h>
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2008-08-04 16:54:46 +00:00
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#include <linux/uaccess.h>
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#include <linux/io.h>
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2009-10-30 00:30:25 +00:00
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#include <linux/cpufreq.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2011-09-26 13:40:14 +00:00
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#include <linux/err.h>
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2012-05-03 05:24:17 +00:00
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#include <linux/of.h>
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2017-03-13 19:07:25 +00:00
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#include <linux/of_device.h>
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2013-12-06 05:47:47 +00:00
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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2014-08-20 00:45:36 +00:00
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#include <linux/delay.h>
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2005-04-16 22:20:36 +00:00
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2013-06-17 14:45:24 +00:00
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#define S3C2410_WTCON 0x00
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#define S3C2410_WTDAT 0x04
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#define S3C2410_WTCNT 0x08
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2017-02-24 15:11:16 +00:00
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#define S3C2410_WTCLRINT 0x0c
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2005-04-16 22:20:36 +00:00
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2016-03-01 16:45:17 +00:00
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#define S3C2410_WTCNT_MAXCNT 0xffff
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2013-06-17 14:45:24 +00:00
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#define S3C2410_WTCON_RSTEN (1 << 0)
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#define S3C2410_WTCON_INTEN (1 << 2)
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#define S3C2410_WTCON_ENABLE (1 << 5)
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2005-04-16 22:20:36 +00:00
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2013-06-17 14:45:24 +00:00
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#define S3C2410_WTCON_DIV16 (0 << 3)
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#define S3C2410_WTCON_DIV32 (1 << 3)
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#define S3C2410_WTCON_DIV64 (2 << 3)
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#define S3C2410_WTCON_DIV128 (3 << 3)
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2016-03-01 16:45:17 +00:00
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#define S3C2410_WTCON_MAXDIV 0x80
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2013-06-17 14:45:24 +00:00
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#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
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#define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
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2016-03-01 16:45:17 +00:00
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#define S3C2410_WTCON_PRESCALE_MAX 0xff
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2005-04-16 22:20:36 +00:00
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2017-02-24 15:11:15 +00:00
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#define S3C2410_WATCHDOG_ATBOOT (0)
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#define S3C2410_WATCHDOG_DEFAULT_TIME (15)
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2005-04-16 22:20:36 +00:00
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2013-12-06 21:08:07 +00:00
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#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
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2013-12-06 05:47:47 +00:00
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#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
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#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
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#define QUIRK_HAS_PMU_CONFIG (1 << 0)
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2013-12-06 21:08:07 +00:00
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#define QUIRK_HAS_RST_STAT (1 << 1)
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2017-02-24 15:11:16 +00:00
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#define QUIRK_HAS_WTCLRINT_REG (1 << 2)
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2013-12-06 21:08:07 +00:00
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/* These quirks require that we have a PMU register map */
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#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
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QUIRK_HAS_RST_STAT)
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2013-12-06 05:47:47 +00:00
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2012-03-05 15:51:11 +00:00
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static bool nowayout = WATCHDOG_NOWAYOUT;
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2013-02-14 08:14:25 +00:00
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static int tmr_margin;
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2017-02-24 15:11:15 +00:00
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static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT;
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2008-08-04 16:54:46 +00:00
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static int soft_noboot;
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2005-04-16 22:20:36 +00:00
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module_param(tmr_margin, int, 0);
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module_param(tmr_atboot, int, 0);
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2012-03-05 15:51:11 +00:00
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module_param(nowayout, bool, 0);
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2005-04-16 22:20:36 +00:00
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module_param(soft_noboot, int, 0);
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2010-05-01 16:46:15 +00:00
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MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
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2017-02-24 15:11:15 +00:00
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__MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")");
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2008-08-04 16:54:46 +00:00
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MODULE_PARM_DESC(tmr_atboot,
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"Watchdog is started at boot time if set to 1, default="
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2017-02-24 15:11:15 +00:00
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__MODULE_STRING(S3C2410_WATCHDOG_ATBOOT));
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2008-08-04 16:54:46 +00:00
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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2017-03-13 19:07:26 +00:00
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MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
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2005-04-16 22:20:36 +00:00
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2013-12-06 05:47:47 +00:00
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/**
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* struct s3c2410_wdt_variant - Per-variant config data
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*
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* @disable_reg: Offset in pmureg for the register that disables the watchdog
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* timer reset functionality.
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* @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
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* timer reset functionality.
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* @mask_bit: Bit number for the watchdog timer in the disable register and the
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* mask reset register.
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2013-12-06 21:08:07 +00:00
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* @rst_stat_reg: Offset in pmureg for the register that has the reset status.
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* @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
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* reset.
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2013-12-06 05:47:47 +00:00
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* @quirks: A bitfield of quirks.
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*/
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struct s3c2410_wdt_variant {
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int disable_reg;
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int mask_reset_reg;
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int mask_bit;
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2013-12-06 21:08:07 +00:00
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int rst_stat_reg;
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int rst_stat_bit;
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2013-12-06 05:47:47 +00:00
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u32 quirks;
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};
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2013-08-27 10:06:03 +00:00
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struct s3c2410_wdt {
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struct device *dev;
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struct clk *clock;
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void __iomem *reg_base;
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unsigned int count;
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spinlock_t lock;
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unsigned long wtcon_save;
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unsigned long wtdat_save;
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struct watchdog_device wdt_device;
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struct notifier_block freq_transition;
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2017-03-13 19:07:24 +00:00
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const struct s3c2410_wdt_variant *drv_data;
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2013-12-06 05:47:47 +00:00
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struct regmap *pmureg;
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};
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static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
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.quirks = 0
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};
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#ifdef CONFIG_OF
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2017-02-24 15:11:16 +00:00
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static const struct s3c2410_wdt_variant drv_data_s3c6410 = {
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.quirks = QUIRK_HAS_WTCLRINT_REG,
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};
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2013-12-06 05:47:47 +00:00
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static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
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.mask_bit = 20,
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2013-12-06 21:08:07 +00:00
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
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.rst_stat_bit = 20,
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2017-02-24 15:11:16 +00:00
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.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
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| QUIRK_HAS_WTCLRINT_REG,
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2013-12-06 05:47:47 +00:00
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};
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static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
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.mask_bit = 0,
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2013-12-06 21:08:07 +00:00
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
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.rst_stat_bit = 9,
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2017-02-24 15:11:16 +00:00
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.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
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| QUIRK_HAS_WTCLRINT_REG,
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2013-12-06 05:47:47 +00:00
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};
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2014-08-27 09:47:11 +00:00
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static const struct s3c2410_wdt_variant drv_data_exynos7 = {
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
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2014-10-17 16:12:53 +00:00
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.mask_bit = 23,
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2014-08-27 09:47:11 +00:00
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
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.rst_stat_bit = 23, /* A57 WDTRESET */
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2017-02-24 15:11:16 +00:00
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.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
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| QUIRK_HAS_WTCLRINT_REG,
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2014-08-27 09:47:11 +00:00
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};
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2013-12-06 05:47:47 +00:00
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static const struct of_device_id s3c2410_wdt_match[] = {
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{ .compatible = "samsung,s3c2410-wdt",
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.data = &drv_data_s3c2410 },
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2017-02-24 15:11:16 +00:00
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{ .compatible = "samsung,s3c6410-wdt",
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.data = &drv_data_s3c6410 },
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2013-12-06 05:47:47 +00:00
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{ .compatible = "samsung,exynos5250-wdt",
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.data = &drv_data_exynos5250 },
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{ .compatible = "samsung,exynos5420-wdt",
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.data = &drv_data_exynos5420 },
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2014-08-27 09:47:11 +00:00
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{ .compatible = "samsung,exynos7-wdt",
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.data = &drv_data_exynos7 },
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2013-12-06 05:47:47 +00:00
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{},
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2013-08-27 10:06:03 +00:00
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};
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2013-12-06 05:47:47 +00:00
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MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
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#endif
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static const struct platform_device_id s3c2410_wdt_ids[] = {
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{
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.name = "s3c2410-wdt",
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.driver_data = (unsigned long)&drv_data_s3c2410,
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},
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{}
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};
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MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
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2005-04-16 22:20:36 +00:00
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/* functions */
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2016-03-01 16:45:17 +00:00
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static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock)
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{
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unsigned long freq = clk_get_rate(clock);
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return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1)
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/ S3C2410_WTCON_MAXDIV);
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}
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2013-08-27 10:06:03 +00:00
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static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
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{
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return container_of(nb, struct s3c2410_wdt, freq_transition);
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}
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2013-12-06 05:47:47 +00:00
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static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
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{
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int ret;
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u32 mask_val = 1 << wdt->drv_data->mask_bit;
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u32 val = 0;
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/* No need to do anything if no PMU CONFIG needed */
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if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
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return 0;
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if (mask)
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val = mask_val;
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ret = regmap_update_bits(wdt->pmureg,
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wdt->drv_data->disable_reg,
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mask_val, val);
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if (ret < 0)
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goto error;
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ret = regmap_update_bits(wdt->pmureg,
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wdt->drv_data->mask_reset_reg,
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mask_val, val);
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error:
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if (ret < 0)
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dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
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return ret;
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}
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2011-09-26 13:40:14 +00:00
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static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
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2005-04-16 22:20:36 +00:00
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{
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2013-08-27 10:06:03 +00:00
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|
|
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
|
|
|
|
|
|
|
spin_lock(&wdt->lock);
|
|
|
|
writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
|
|
|
|
spin_unlock(&wdt->lock);
|
2011-09-26 13:40:14 +00:00
|
|
|
|
|
|
|
return 0;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
|
2008-08-04 16:54:46 +00:00
|
|
|
{
|
|
|
|
unsigned long wtcon;
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
2008-08-04 16:54:46 +00:00
|
|
|
wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
|
2013-08-27 10:06:03 +00:00
|
|
|
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
|
2008-08-04 16:54:46 +00:00
|
|
|
}
|
|
|
|
|
2011-09-26 13:40:14 +00:00
|
|
|
static int s3c2410wdt_stop(struct watchdog_device *wdd)
|
2008-08-04 16:54:46 +00:00
|
|
|
{
|
2013-08-27 10:06:03 +00:00
|
|
|
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
|
|
|
|
|
|
|
spin_lock(&wdt->lock);
|
|
|
|
__s3c2410wdt_stop(wdt);
|
|
|
|
spin_unlock(&wdt->lock);
|
2011-09-26 13:40:14 +00:00
|
|
|
|
|
|
|
return 0;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2011-09-26 13:40:14 +00:00
|
|
|
static int s3c2410wdt_start(struct watchdog_device *wdd)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
unsigned long wtcon;
|
2013-08-27 10:06:03 +00:00
|
|
|
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
spin_lock(&wdt->lock);
|
2008-08-04 16:54:46 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
__s3c2410wdt_stop(wdt);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
2005-04-16 22:20:36 +00:00
|
|
|
wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
|
|
|
|
|
|
|
|
if (soft_noboot) {
|
|
|
|
wtcon |= S3C2410_WTCON_INTEN;
|
|
|
|
wtcon &= ~S3C2410_WTCON_RSTEN;
|
|
|
|
} else {
|
|
|
|
wtcon &= ~S3C2410_WTCON_INTEN;
|
|
|
|
wtcon |= S3C2410_WTCON_RSTEN;
|
|
|
|
}
|
|
|
|
|
2017-02-24 21:07:40 +00:00
|
|
|
dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
|
|
|
|
wdt->count, wtcon);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
|
|
|
|
writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
|
|
|
|
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
|
|
|
|
spin_unlock(&wdt->lock);
|
2011-09-26 13:40:14 +00:00
|
|
|
|
|
|
|
return 0;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
|
2009-10-30 00:30:25 +00:00
|
|
|
{
|
2013-08-27 10:06:03 +00:00
|
|
|
return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
|
2009-10-30 00:30:25 +00:00
|
|
|
}
|
|
|
|
|
2017-03-13 19:07:26 +00:00
|
|
|
static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd,
|
|
|
|
unsigned int timeout)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2013-08-27 10:06:03 +00:00
|
|
|
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
|
|
|
unsigned long freq = clk_get_rate(wdt->clock);
|
2005-04-16 22:20:36 +00:00
|
|
|
unsigned int count;
|
|
|
|
unsigned int divisor = 1;
|
|
|
|
unsigned long wtcon;
|
|
|
|
|
|
|
|
if (timeout < 1)
|
|
|
|
return -EINVAL;
|
|
|
|
|
watchdog: s3c2410_wdt: Handle rounding a little better for timeout
The existing watchdog timeout worked OK but didn't deal with
rounding in an ideal way when dividing out all of its clocks.
Specifically if you had a timeout of 32 seconds and an input clock of
66666666, you'd end up setting a timeout of 31.9998 seconds and
reporting a timeout of 31 seconds.
Specifically DBG printouts showed:
s3c2410wdt_set_heartbeat: count=16666656, timeout=32, freq=520833
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666656 (0000ff4f)
and the final timeout reported to the user was:
((count / divisor) * divisor) / freq
(0xff4f * 255) / 520833 = 31 (truncated from 31.9998)
the technically "correct" value is:
(0xff4f * 255) / (66666666.0 / 128) = 31.9998
By using "DIV_ROUND_UP" we can be a little more correct.
s3c2410wdt_set_heartbeat: count=16666688, timeout=32, freq=520834
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666688 (0000ff50)
and the final timeout reported to the user:
(0xff50 * 255) / 520834 = 32
the technically "correct" value is:
(0xff50 * 255) / (66666666.0 / 128) = 32.0003
We'll use a DIV_ROUND_UP to solve this, generally erroring on the side
of reporting shorter values to the user and setting the watchdog to
slightly longer than requested:
* Round input frequency up to assume watchdog is counting faster.
* Round divisions by divisor up to give us extra time.
At the same time we can avoid a for loop by just doing the right math.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2013-11-27 00:57:19 +00:00
|
|
|
freq = DIV_ROUND_UP(freq, 128);
|
2005-04-16 22:20:36 +00:00
|
|
|
count = timeout * freq;
|
|
|
|
|
2017-02-24 21:07:40 +00:00
|
|
|
dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
|
|
|
|
count, timeout, freq);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/* if the count is bigger than the watchdog register,
|
|
|
|
then work out what we need to do (and if) we can
|
|
|
|
actually make this value
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (count >= 0x10000) {
|
watchdog: s3c2410_wdt: Handle rounding a little better for timeout
The existing watchdog timeout worked OK but didn't deal with
rounding in an ideal way when dividing out all of its clocks.
Specifically if you had a timeout of 32 seconds and an input clock of
66666666, you'd end up setting a timeout of 31.9998 seconds and
reporting a timeout of 31 seconds.
Specifically DBG printouts showed:
s3c2410wdt_set_heartbeat: count=16666656, timeout=32, freq=520833
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666656 (0000ff4f)
and the final timeout reported to the user was:
((count / divisor) * divisor) / freq
(0xff4f * 255) / 520833 = 31 (truncated from 31.9998)
the technically "correct" value is:
(0xff4f * 255) / (66666666.0 / 128) = 31.9998
By using "DIV_ROUND_UP" we can be a little more correct.
s3c2410wdt_set_heartbeat: count=16666688, timeout=32, freq=520834
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666688 (0000ff50)
and the final timeout reported to the user:
(0xff50 * 255) / 520834 = 32
the technically "correct" value is:
(0xff50 * 255) / (66666666.0 / 128) = 32.0003
We'll use a DIV_ROUND_UP to solve this, generally erroring on the side
of reporting shorter values to the user and setting the watchdog to
slightly longer than requested:
* Round input frequency up to assume watchdog is counting faster.
* Round divisions by divisor up to give us extra time.
At the same time we can avoid a for loop by just doing the right math.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2013-11-27 00:57:19 +00:00
|
|
|
divisor = DIV_ROUND_UP(count, 0xffff);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
watchdog: s3c2410_wdt: Handle rounding a little better for timeout
The existing watchdog timeout worked OK but didn't deal with
rounding in an ideal way when dividing out all of its clocks.
Specifically if you had a timeout of 32 seconds and an input clock of
66666666, you'd end up setting a timeout of 31.9998 seconds and
reporting a timeout of 31 seconds.
Specifically DBG printouts showed:
s3c2410wdt_set_heartbeat: count=16666656, timeout=32, freq=520833
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666656 (0000ff4f)
and the final timeout reported to the user was:
((count / divisor) * divisor) / freq
(0xff4f * 255) / 520833 = 31 (truncated from 31.9998)
the technically "correct" value is:
(0xff4f * 255) / (66666666.0 / 128) = 31.9998
By using "DIV_ROUND_UP" we can be a little more correct.
s3c2410wdt_set_heartbeat: count=16666688, timeout=32, freq=520834
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666688 (0000ff50)
and the final timeout reported to the user:
(0xff50 * 255) / 520834 = 32
the technically "correct" value is:
(0xff50 * 255) / (66666666.0 / 128) = 32.0003
We'll use a DIV_ROUND_UP to solve this, generally erroring on the side
of reporting shorter values to the user and setting the watchdog to
slightly longer than requested:
* Round input frequency up to assume watchdog is counting faster.
* Round divisions by divisor up to give us extra time.
At the same time we can avoid a for loop by just doing the right math.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2013-11-27 00:57:19 +00:00
|
|
|
if (divisor > 0x100) {
|
2013-08-27 10:06:03 +00:00
|
|
|
dev_err(wdt->dev, "timeout %d too big\n", timeout);
|
2005-04-16 22:20:36 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-02-24 21:07:40 +00:00
|
|
|
dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
|
|
|
|
timeout, divisor, count, DIV_ROUND_UP(count, divisor));
|
2005-04-16 22:20:36 +00:00
|
|
|
|
watchdog: s3c2410_wdt: Handle rounding a little better for timeout
The existing watchdog timeout worked OK but didn't deal with
rounding in an ideal way when dividing out all of its clocks.
Specifically if you had a timeout of 32 seconds and an input clock of
66666666, you'd end up setting a timeout of 31.9998 seconds and
reporting a timeout of 31 seconds.
Specifically DBG printouts showed:
s3c2410wdt_set_heartbeat: count=16666656, timeout=32, freq=520833
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666656 (0000ff4f)
and the final timeout reported to the user was:
((count / divisor) * divisor) / freq
(0xff4f * 255) / 520833 = 31 (truncated from 31.9998)
the technically "correct" value is:
(0xff4f * 255) / (66666666.0 / 128) = 31.9998
By using "DIV_ROUND_UP" we can be a little more correct.
s3c2410wdt_set_heartbeat: count=16666688, timeout=32, freq=520834
s3c2410wdt_set_heartbeat: timeout=32, divisor=255, count=16666688 (0000ff50)
and the final timeout reported to the user:
(0xff50 * 255) / 520834 = 32
the technically "correct" value is:
(0xff50 * 255) / (66666666.0 / 128) = 32.0003
We'll use a DIV_ROUND_UP to solve this, generally erroring on the side
of reporting shorter values to the user and setting the watchdog to
slightly longer than requested:
* Round input frequency up to assume watchdog is counting faster.
* Round divisions by divisor up to give us extra time.
At the same time we can avoid a for loop by just doing the right math.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2013-11-27 00:57:19 +00:00
|
|
|
count = DIV_ROUND_UP(count, divisor);
|
2013-08-27 10:06:03 +00:00
|
|
|
wdt->count = count;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
/* update the pre-scaler */
|
2013-08-27 10:06:03 +00:00
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
2005-04-16 22:20:36 +00:00
|
|
|
wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
|
|
|
|
wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
writel(count, wdt->reg_base + S3C2410_WTDAT);
|
|
|
|
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2012-05-11 10:00:27 +00:00
|
|
|
wdd->timeout = (count * divisor) / freq;
|
2012-02-29 19:20:58 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-02-27 01:32:49 +00:00
|
|
|
static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
|
|
|
|
void *data)
|
2015-11-16 17:28:10 +00:00
|
|
|
{
|
|
|
|
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
|
|
|
|
void __iomem *wdt_base = wdt->reg_base;
|
|
|
|
|
|
|
|
/* disable watchdog, to be safe */
|
|
|
|
writel(0, wdt_base + S3C2410_WTCON);
|
|
|
|
|
|
|
|
/* put initial values into count and data */
|
|
|
|
writel(0x80, wdt_base + S3C2410_WTCNT);
|
|
|
|
writel(0x80, wdt_base + S3C2410_WTDAT);
|
|
|
|
|
|
|
|
/* set the watchdog to go and reset... */
|
|
|
|
writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
|
|
|
|
S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
|
|
|
|
wdt_base + S3C2410_WTCON);
|
|
|
|
|
|
|
|
/* wait for reset to assert... */
|
|
|
|
mdelay(500);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-04-14 20:20:07 +00:00
|
|
|
#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2008-08-04 16:54:46 +00:00
|
|
|
static const struct watchdog_info s3c2410_wdt_ident = {
|
2005-04-16 22:20:36 +00:00
|
|
|
.options = OPTIONS,
|
|
|
|
.firmware_version = 0,
|
|
|
|
.identity = "S3C2410 Watchdog",
|
|
|
|
};
|
|
|
|
|
2017-01-28 07:41:17 +00:00
|
|
|
static const struct watchdog_ops s3c2410wdt_ops = {
|
2011-09-26 13:40:14 +00:00
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.start = s3c2410wdt_start,
|
|
|
|
.stop = s3c2410wdt_stop,
|
|
|
|
.ping = s3c2410wdt_keepalive,
|
|
|
|
.set_timeout = s3c2410wdt_set_heartbeat,
|
2015-11-16 17:28:10 +00:00
|
|
|
.restart = s3c2410wdt_restart,
|
2005-04-16 22:20:36 +00:00
|
|
|
};
|
|
|
|
|
2017-03-13 19:07:24 +00:00
|
|
|
static const struct watchdog_device s3c2410_wdd = {
|
2011-09-26 13:40:14 +00:00
|
|
|
.info = &s3c2410_wdt_ident,
|
|
|
|
.ops = &s3c2410wdt_ops,
|
2017-02-24 15:11:15 +00:00
|
|
|
.timeout = S3C2410_WATCHDOG_DEFAULT_TIME,
|
2005-04-16 22:20:36 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/* interrupt handler code */
|
|
|
|
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 13:55:46 +00:00
|
|
|
static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2013-08-27 10:06:03 +00:00
|
|
|
struct s3c2410_wdt *wdt = platform_get_drvdata(param);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
dev_info(wdt->dev, "watchdog timer expired (irq)\n");
|
|
|
|
|
|
|
|
s3c2410wdt_keepalive(&wdt->wdt_device);
|
2017-02-24 15:11:16 +00:00
|
|
|
|
|
|
|
if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
|
|
|
|
writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2009-10-30 00:30:25 +00:00
|
|
|
|
2013-11-25 23:36:43 +00:00
|
|
|
#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
|
2009-10-30 00:30:25 +00:00
|
|
|
|
|
|
|
static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
|
|
|
|
unsigned long val, void *data)
|
|
|
|
{
|
|
|
|
int ret;
|
2013-08-27 10:06:03 +00:00
|
|
|
struct s3c2410_wdt *wdt = freq_to_wdt(nb);
|
2009-10-30 00:30:25 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
if (!s3c2410wdt_is_running(wdt))
|
2009-10-30 00:30:25 +00:00
|
|
|
goto done;
|
|
|
|
|
|
|
|
if (val == CPUFREQ_PRECHANGE) {
|
|
|
|
/* To ensure that over the change we don't cause the
|
|
|
|
* watchdog to trigger, we perform an keep-alive if
|
|
|
|
* the watchdog is running.
|
|
|
|
*/
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
s3c2410wdt_keepalive(&wdt->wdt_device);
|
2009-10-30 00:30:25 +00:00
|
|
|
} else if (val == CPUFREQ_POSTCHANGE) {
|
2013-08-27 10:06:03 +00:00
|
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
2009-10-30 00:30:25 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
|
|
|
|
wdt->wdt_device.timeout);
|
2009-10-30 00:30:25 +00:00
|
|
|
|
|
|
|
if (ret >= 0)
|
2013-08-27 10:06:03 +00:00
|
|
|
s3c2410wdt_start(&wdt->wdt_device);
|
2009-10-30 00:30:25 +00:00
|
|
|
else
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
done:
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err:
|
2013-08-27 10:06:03 +00:00
|
|
|
dev_err(wdt->dev, "cannot set new value for timeout %d\n",
|
|
|
|
wdt->wdt_device.timeout);
|
2009-10-30 00:30:25 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
|
2009-10-30 00:30:25 +00:00
|
|
|
{
|
2013-08-27 10:06:03 +00:00
|
|
|
wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
|
|
|
|
|
|
|
|
return cpufreq_register_notifier(&wdt->freq_transition,
|
2009-10-30 00:30:25 +00:00
|
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
|
|
}
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
|
2009-10-30 00:30:25 +00:00
|
|
|
{
|
2013-08-27 10:06:03 +00:00
|
|
|
wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
|
|
|
|
|
|
|
|
cpufreq_unregister_notifier(&wdt->freq_transition,
|
2009-10-30 00:30:25 +00:00
|
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
2013-08-27 10:06:03 +00:00
|
|
|
|
|
|
|
static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
|
2009-10-30 00:30:25 +00:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
|
2009-10-30 00:30:25 +00:00
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2013-12-06 21:08:07 +00:00
|
|
|
static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
|
|
|
|
{
|
|
|
|
unsigned int rst_stat;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
|
|
|
|
if (ret)
|
|
|
|
dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
|
|
|
|
else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
|
|
|
|
return WDIOF_CARDRESET;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-03-13 19:07:24 +00:00
|
|
|
static inline const struct s3c2410_wdt_variant *
|
2017-02-24 21:07:43 +00:00
|
|
|
s3c2410_get_wdt_drv_data(struct platform_device *pdev)
|
2013-12-06 05:47:47 +00:00
|
|
|
{
|
2017-03-13 19:07:25 +00:00
|
|
|
const struct s3c2410_wdt_variant *variant;
|
|
|
|
|
|
|
|
variant = of_device_get_match_data(&pdev->dev);
|
|
|
|
if (!variant) {
|
|
|
|
/* Device matched by platform_device_id */
|
|
|
|
variant = (struct s3c2410_wdt_variant *)
|
|
|
|
platform_get_device_id(pdev)->driver_data;
|
2013-12-06 05:47:47 +00:00
|
|
|
}
|
2017-03-13 19:07:25 +00:00
|
|
|
|
|
|
|
return variant;
|
2013-12-06 05:47:47 +00:00
|
|
|
}
|
|
|
|
|
2012-11-19 18:21:41 +00:00
|
|
|
static int s3c2410wdt_probe(struct platform_device *pdev)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2017-03-13 19:07:26 +00:00
|
|
|
struct device *dev = &pdev->dev;
|
2013-08-27 10:06:03 +00:00
|
|
|
struct s3c2410_wdt *wdt;
|
|
|
|
struct resource *wdt_irq;
|
2007-06-14 11:08:54 +00:00
|
|
|
unsigned int wtcon;
|
2005-04-16 22:20:36 +00:00
|
|
|
int started = 0;
|
|
|
|
int ret;
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
|
|
|
|
if (!wdt)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2017-03-13 19:07:26 +00:00
|
|
|
wdt->dev = dev;
|
2013-08-27 10:06:03 +00:00
|
|
|
spin_lock_init(&wdt->lock);
|
|
|
|
wdt->wdt_device = s3c2410_wdd;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2017-02-24 21:07:43 +00:00
|
|
|
wdt->drv_data = s3c2410_get_wdt_drv_data(pdev);
|
2013-12-06 21:08:07 +00:00
|
|
|
if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
|
2013-12-06 05:47:47 +00:00
|
|
|
wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
|
|
|
|
"samsung,syscon-phandle");
|
|
|
|
if (IS_ERR(wdt->pmureg)) {
|
|
|
|
dev_err(dev, "syscon regmap lookup failed.\n");
|
|
|
|
return PTR_ERR(wdt->pmureg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-01-13 05:14:23 +00:00
|
|
|
wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
|
|
if (wdt_irq == NULL) {
|
|
|
|
dev_err(dev, "no irq resource specified\n");
|
|
|
|
ret = -ENOENT;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* get the memory region for the watchdog timer */
|
watchdog: Convert to use devm_platform_ioremap_resource
Use devm_platform_ioremap_resource to reduce source code size,
improve readability, and reduce the likelyhood of bugs.
The conversion was done automatically with coccinelle using the
following semantic patch.
@r@
identifier res, pdev;
expression a;
expression index;
expression e;
@@
<+...
- res = platform_get_resource(pdev, IORESOURCE_MEM, index);
- a = devm_ioremap_resource(e, res);
+ a = devm_platform_ioremap_resource(pdev, index);
...+>
@depends on r@
identifier r.res;
@@
- struct resource *res;
... when != res
@@
identifier res, pdev;
expression index;
expression a;
@@
- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, index);
- a = devm_ioremap_resource(&pdev->dev, res);
+ a = devm_platform_ioremap_resource(pdev, index);
Cc: Joel Stanley <joel@jms.id.au>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Keguang Zhang <keguang.zhang@gmail.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Avi Fishman <avifishman70@gmail.com>
Cc: Nancy Yuen <yuenn@google.com>
Cc: Brendan Higgins <brendanhiggins@google.com>
Cc: Wan ZongShun <mcuos.com@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Barry Song <baohua@kernel.org>
Cc: Orson Zhai <orsonzhai@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tested-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Michal Simek <michal.simek@xilinx.com> (cadence/xilinx wdts)
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
2019-04-02 19:01:53 +00:00
|
|
|
wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
|
2013-08-27 10:06:03 +00:00
|
|
|
if (IS_ERR(wdt->reg_base)) {
|
|
|
|
ret = PTR_ERR(wdt->reg_base);
|
2013-01-10 02:06:33 +00:00
|
|
|
goto err;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
wdt->clock = devm_clk_get(dev, "watchdog");
|
|
|
|
if (IS_ERR(wdt->clock)) {
|
2007-06-14 11:08:55 +00:00
|
|
|
dev_err(dev, "failed to find watchdog clock source\n");
|
2013-08-27 10:06:03 +00:00
|
|
|
ret = PTR_ERR(wdt->clock);
|
2013-01-10 02:06:33 +00:00
|
|
|
goto err;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2014-03-04 09:34:35 +00:00
|
|
|
ret = clk_prepare_enable(wdt->clock);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev, "failed to enable clock\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2016-03-01 16:45:17 +00:00
|
|
|
wdt->wdt_device.min_timeout = 1;
|
|
|
|
wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock);
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
ret = s3c2410wdt_cpufreq_register(wdt);
|
2012-01-13 05:14:23 +00:00
|
|
|
if (ret < 0) {
|
2013-03-14 01:30:21 +00:00
|
|
|
dev_err(dev, "failed to register cpufreq\n");
|
2009-10-30 00:30:25 +00:00
|
|
|
goto err_clk;
|
|
|
|
}
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
watchdog_set_drvdata(&wdt->wdt_device, wdt);
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/* see if we can actually set the requested timer margin, and if
|
|
|
|
* not, try the default value */
|
|
|
|
|
2017-03-13 19:07:26 +00:00
|
|
|
watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
|
2013-08-27 10:06:03 +00:00
|
|
|
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
|
|
|
|
wdt->wdt_device.timeout);
|
|
|
|
if (ret) {
|
|
|
|
started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
|
2017-02-24 15:11:15 +00:00
|
|
|
S3C2410_WATCHDOG_DEFAULT_TIME);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2008-08-04 16:54:46 +00:00
|
|
|
if (started == 0)
|
|
|
|
dev_info(dev,
|
2017-03-13 19:07:26 +00:00
|
|
|
"tmr_margin value out of range, default %d used\n",
|
|
|
|
S3C2410_WATCHDOG_DEFAULT_TIME);
|
2008-08-04 16:54:46 +00:00
|
|
|
else
|
2017-03-13 19:07:26 +00:00
|
|
|
dev_info(dev, "default timer value is out of range, cannot start\n");
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2013-01-10 02:06:33 +00:00
|
|
|
ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
|
|
|
|
pdev->name, pdev);
|
2012-01-13 05:14:23 +00:00
|
|
|
if (ret != 0) {
|
|
|
|
dev_err(dev, "failed to install irq (%d)\n", ret);
|
|
|
|
goto err_cpufreq;
|
|
|
|
}
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
watchdog_set_nowayout(&wdt->wdt_device, nowayout);
|
2015-11-16 17:28:10 +00:00
|
|
|
watchdog_set_restart_priority(&wdt->wdt_device, 128);
|
2011-11-29 15:24:16 +00:00
|
|
|
|
2013-12-06 21:08:07 +00:00
|
|
|
wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
|
2017-03-13 19:07:26 +00:00
|
|
|
wdt->wdt_device.parent = dev;
|
2013-12-06 21:08:07 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
ret = watchdog_register_device(&wdt->wdt_device);
|
2019-05-18 21:27:50 +00:00
|
|
|
if (ret)
|
2013-01-10 02:06:33 +00:00
|
|
|
goto err_cpufreq;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2013-12-06 05:47:47 +00:00
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err_unregister;
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
if (tmr_atboot && started == 0) {
|
2007-06-14 11:08:55 +00:00
|
|
|
dev_info(dev, "starting watchdog timer\n");
|
2013-08-27 10:06:03 +00:00
|
|
|
s3c2410wdt_start(&wdt->wdt_device);
|
2006-04-19 22:02:56 +00:00
|
|
|
} else if (!tmr_atboot) {
|
|
|
|
/* if we're not enabling the watchdog, then ensure it is
|
|
|
|
* disabled if it has been left running from the bootloader
|
|
|
|
* or other source */
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
platform_set_drvdata(pdev, wdt);
|
|
|
|
|
2007-06-14 11:08:54 +00:00
|
|
|
/* print out a statement of readiness */
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
2007-06-14 11:08:54 +00:00
|
|
|
|
2007-06-14 11:08:55 +00:00
|
|
|
dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
|
2007-06-14 11:08:54 +00:00
|
|
|
(wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
|
2011-11-16 08:46:13 +00:00
|
|
|
(wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
|
|
|
|
(wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
|
2008-08-04 16:54:46 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
return 0;
|
2006-12-18 10:31:32 +00:00
|
|
|
|
2013-12-06 05:47:47 +00:00
|
|
|
err_unregister:
|
|
|
|
watchdog_unregister_device(&wdt->wdt_device);
|
|
|
|
|
2009-10-30 00:30:25 +00:00
|
|
|
err_cpufreq:
|
2013-08-27 10:06:03 +00:00
|
|
|
s3c2410wdt_cpufreq_deregister(wdt);
|
2009-10-30 00:30:25 +00:00
|
|
|
|
2006-12-18 10:31:32 +00:00
|
|
|
err_clk:
|
2013-08-27 10:06:03 +00:00
|
|
|
clk_disable_unprepare(wdt->clock);
|
2006-12-18 10:31:32 +00:00
|
|
|
|
2012-01-13 05:14:23 +00:00
|
|
|
err:
|
2006-12-18 10:31:32 +00:00
|
|
|
return ret;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2012-11-19 18:26:24 +00:00
|
|
|
static int s3c2410wdt_remove(struct platform_device *dev)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2013-12-06 05:47:47 +00:00
|
|
|
int ret;
|
2013-08-27 10:06:03 +00:00
|
|
|
struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
|
|
|
|
|
2013-12-06 05:47:47 +00:00
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
watchdog_unregister_device(&wdt->wdt_device);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
s3c2410wdt_cpufreq_deregister(wdt);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
clk_disable_unprepare(wdt->clock);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-11-09 22:32:44 +00:00
|
|
|
static void s3c2410wdt_shutdown(struct platform_device *dev)
|
2005-08-17 07:04:52 +00:00
|
|
|
{
|
2013-08-27 10:06:03 +00:00
|
|
|
struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
|
|
|
|
|
2013-12-06 05:47:47 +00:00
|
|
|
s3c2410wdt_mask_and_disable_reset(wdt, true);
|
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
2005-08-17 07:04:52 +00:00
|
|
|
}
|
|
|
|
|
2013-03-14 01:31:21 +00:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2005-08-17 07:03:23 +00:00
|
|
|
|
2013-03-14 01:31:21 +00:00
|
|
|
static int s3c2410wdt_suspend(struct device *dev)
|
2005-08-17 07:03:23 +00:00
|
|
|
{
|
2013-12-06 05:47:47 +00:00
|
|
|
int ret;
|
2013-08-27 10:06:03 +00:00
|
|
|
struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
|
|
|
|
|
2005-10-28 16:52:56 +00:00
|
|
|
/* Save watchdog state, and turn it off. */
|
2013-08-27 10:06:03 +00:00
|
|
|
wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
|
|
|
|
wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
|
2005-08-17 07:03:23 +00:00
|
|
|
|
2013-12-06 05:47:47 +00:00
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2005-10-28 16:52:56 +00:00
|
|
|
/* Note that WTCNT doesn't need to be saved. */
|
2013-08-27 10:06:03 +00:00
|
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
2005-08-17 07:03:23 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-03-14 01:31:21 +00:00
|
|
|
static int s3c2410wdt_resume(struct device *dev)
|
2005-08-17 07:03:23 +00:00
|
|
|
{
|
2013-12-06 05:47:47 +00:00
|
|
|
int ret;
|
2013-08-27 10:06:03 +00:00
|
|
|
struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
|
2005-08-17 07:03:23 +00:00
|
|
|
|
2013-08-27 10:06:03 +00:00
|
|
|
/* Restore watchdog state. */
|
|
|
|
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
|
|
|
|
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
|
|
|
|
writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
|
2005-08-17 07:03:23 +00:00
|
|
|
|
2013-12-06 05:47:47 +00:00
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2013-03-14 01:31:21 +00:00
|
|
|
dev_info(dev, "watchdog %sabled\n",
|
2013-08-27 10:06:03 +00:00
|
|
|
(wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
|
2005-08-17 07:03:23 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2013-03-14 01:31:21 +00:00
|
|
|
#endif
|
2005-08-17 07:03:23 +00:00
|
|
|
|
2013-03-14 01:31:21 +00:00
|
|
|
static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
|
|
|
|
s3c2410wdt_resume);
|
2005-08-17 07:03:23 +00:00
|
|
|
|
2005-11-09 22:32:44 +00:00
|
|
|
static struct platform_driver s3c2410wdt_driver = {
|
2005-04-16 22:20:36 +00:00
|
|
|
.probe = s3c2410wdt_probe,
|
2012-11-19 18:21:12 +00:00
|
|
|
.remove = s3c2410wdt_remove,
|
2005-08-17 07:04:52 +00:00
|
|
|
.shutdown = s3c2410wdt_shutdown,
|
2013-12-06 05:47:47 +00:00
|
|
|
.id_table = s3c2410_wdt_ids,
|
2005-11-09 22:32:44 +00:00
|
|
|
.driver = {
|
|
|
|
.name = "s3c2410-wdt",
|
2013-03-14 01:31:21 +00:00
|
|
|
.pm = &s3c2410wdt_pm_ops,
|
2012-05-03 05:24:17 +00:00
|
|
|
.of_match_table = of_match_ptr(s3c2410_wdt_match),
|
2005-11-09 22:32:44 +00:00
|
|
|
},
|
2005-04-16 22:20:36 +00:00
|
|
|
};
|
|
|
|
|
2012-07-12 11:47:40 +00:00
|
|
|
module_platform_driver(s3c2410wdt_driver);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2017-03-13 19:07:26 +00:00
|
|
|
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>");
|
2005-04-16 22:20:36 +00:00
|
|
|
MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
|
|
|
|
MODULE_LICENSE("GPL");
|