2008-02-05 06:28:22 +00:00
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/*
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* linux/arch/arm/mach-pxa/gpio.c
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*
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* Generic PXA GPIO handling
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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2008-03-04 03:42:26 +00:00
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#include <linux/irq.h>
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2008-03-04 08:13:58 +00:00
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#include <linux/sysdev.h>
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2008-09-06 11:10:45 +00:00
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#include <linux/io.h>
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2008-02-05 06:28:22 +00:00
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#include <asm/gpio.h>
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2008-08-05 15:14:15 +00:00
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#include <mach/hardware.h>
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#include <mach/pxa-regs.h>
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#include <mach/pxa2xx-gpio.h>
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2008-02-05 06:28:22 +00:00
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#include "generic.h"
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struct pxa_gpio_chip {
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struct gpio_chip chip;
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void __iomem *regbase;
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};
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int pxa_last_gpio;
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/*
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* Configure pins for GPIO or other functions
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*/
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int pxa_gpio_mode(int gpio_mode)
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{
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unsigned long flags;
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int gpio = gpio_mode & GPIO_MD_MASK_NR;
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int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
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int gafr;
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if (gpio > pxa_last_gpio)
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return -EINVAL;
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local_irq_save(flags);
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if (gpio_mode & GPIO_DFLT_LOW)
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GPCR(gpio) = GPIO_bit(gpio);
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else if (gpio_mode & GPIO_DFLT_HIGH)
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GPSR(gpio) = GPIO_bit(gpio);
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if (gpio_mode & GPIO_MD_MASK_DIR)
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GPDR(gpio) |= GPIO_bit(gpio);
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else
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GPDR(gpio) &= ~GPIO_bit(gpio);
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gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
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GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(pxa_gpio_mode);
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static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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unsigned long flags;
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u32 mask = 1 << offset;
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u32 value;
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struct pxa_gpio_chip *pxa;
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void __iomem *gpdr;
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pxa = container_of(chip, struct pxa_gpio_chip, chip);
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gpdr = pxa->regbase + GPDR_OFFSET;
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local_irq_save(flags);
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value = __raw_readl(gpdr);
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value &= ~mask;
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__raw_writel(value, gpdr);
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local_irq_restore(flags);
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return 0;
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}
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static int pxa_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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unsigned long flags;
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u32 mask = 1 << offset;
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u32 tmp;
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struct pxa_gpio_chip *pxa;
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void __iomem *gpdr;
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pxa = container_of(chip, struct pxa_gpio_chip, chip);
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__raw_writel(mask,
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pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
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gpdr = pxa->regbase + GPDR_OFFSET;
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local_irq_save(flags);
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tmp = __raw_readl(gpdr);
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tmp |= mask;
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__raw_writel(tmp, gpdr);
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local_irq_restore(flags);
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return 0;
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}
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/*
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* Return GPIO level
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*/
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static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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u32 mask = 1 << offset;
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struct pxa_gpio_chip *pxa;
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pxa = container_of(chip, struct pxa_gpio_chip, chip);
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return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
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}
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/*
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* Set output GPIO level
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*/
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static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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u32 mask = 1 << offset;
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struct pxa_gpio_chip *pxa;
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pxa = container_of(chip, struct pxa_gpio_chip, chip);
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if (value)
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__raw_writel(mask, pxa->regbase + GPSR_OFFSET);
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else
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__raw_writel(mask, pxa->regbase + GPCR_OFFSET);
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}
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2008-03-03 05:20:20 +00:00
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#define GPIO_CHIP(_n) \
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[_n] = { \
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.regbase = GPIO##_n##_BASE, \
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.chip = { \
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.label = "gpio-" #_n, \
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.direction_input = pxa_gpio_direction_input, \
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.direction_output = pxa_gpio_direction_output, \
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.get = pxa_gpio_get, \
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.set = pxa_gpio_set, \
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.base = (_n) * 32, \
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.ngpio = 32, \
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}, \
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}
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2008-02-05 06:28:22 +00:00
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static struct pxa_gpio_chip pxa_gpio_chip[] = {
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2008-03-03 05:20:20 +00:00
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GPIO_CHIP(0),
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GPIO_CHIP(1),
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GPIO_CHIP(2),
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2008-02-05 06:28:22 +00:00
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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2008-03-03 05:20:20 +00:00
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GPIO_CHIP(3),
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2008-02-05 06:28:22 +00:00
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#endif
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};
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2008-03-04 03:42:26 +00:00
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/*
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* PXA GPIO edge detection for IRQs:
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* IRQs are generated on Falling-Edge, Rising-Edge, or both.
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* Use this instead of directly setting GRER/GFER.
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*/
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2008-04-19 09:42:18 +00:00
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static unsigned long GPIO_IRQ_rising_edge[4];
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static unsigned long GPIO_IRQ_falling_edge[4];
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static unsigned long GPIO_IRQ_mask[4];
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2008-03-04 03:42:26 +00:00
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2008-03-04 09:18:38 +00:00
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/*
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* On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
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* function of a GPIO, and GPDRx cannot be altered once configured. It
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* is attributed as "occupied" here (I know this terminology isn't
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* accurate, you are welcome to propose a better one :-)
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*/
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static int __gpio_is_occupied(unsigned gpio)
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{
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if (cpu_is_pxa25x() || cpu_is_pxa27x())
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return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2));
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else
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return 0;
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}
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2008-03-04 03:42:26 +00:00
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static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
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{
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int gpio, idx;
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gpio = IRQ_TO_GPIO(irq);
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idx = gpio >> 5;
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if (type == IRQ_TYPE_PROBE) {
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/* Don't mess with enabled GPIOs using preconfigured edges or
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* GPIOs set to alternate function or to output during probe
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*/
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if ((GPIO_IRQ_rising_edge[idx] |
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GPIO_IRQ_falling_edge[idx] |
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GPDR(gpio)) & GPIO_bit(gpio))
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return 0;
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2008-03-04 09:18:38 +00:00
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if (__gpio_is_occupied(gpio))
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2008-03-04 03:42:26 +00:00
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return 0;
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2008-03-04 09:18:38 +00:00
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2008-03-04 03:42:26 +00:00
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type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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}
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2008-03-04 09:18:38 +00:00
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GPDR(gpio) &= ~GPIO_bit(gpio);
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2008-03-04 03:42:26 +00:00
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if (type & IRQ_TYPE_EDGE_RISING)
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__set_bit(gpio, GPIO_IRQ_rising_edge);
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else
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__clear_bit(gpio, GPIO_IRQ_rising_edge);
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if (type & IRQ_TYPE_EDGE_FALLING)
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__set_bit(gpio, GPIO_IRQ_falling_edge);
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else
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__clear_bit(gpio, GPIO_IRQ_falling_edge);
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GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
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GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
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pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
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((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
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((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
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return 0;
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}
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/*
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* GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
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*/
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static void pxa_ack_low_gpio(unsigned int irq)
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{
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GEDR0 = (1 << (irq - IRQ_GPIO0));
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}
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static void pxa_mask_low_gpio(unsigned int irq)
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{
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ICMR &= ~(1 << (irq - PXA_IRQ(0)));
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}
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static void pxa_unmask_low_gpio(unsigned int irq)
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{
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ICMR |= 1 << (irq - PXA_IRQ(0));
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}
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static struct irq_chip pxa_low_gpio_chip = {
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.name = "GPIO-l",
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.ack = pxa_ack_low_gpio,
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.mask = pxa_mask_low_gpio,
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.unmask = pxa_unmask_low_gpio,
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.set_type = pxa_gpio_irq_type,
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};
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/*
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* Demux handler for GPIO>=2 edge detect interrupts
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*/
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#define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
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static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
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{
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int loop, bit, n;
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unsigned long gedr[4];
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do {
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gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
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gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
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gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
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gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
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GEDR0 = gedr[0]; GEDR1 = gedr[1];
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GEDR2 = gedr[2]; GEDR3 = gedr[3];
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loop = 0;
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bit = find_first_bit(gedr, GEDR_BITS);
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while (bit < GEDR_BITS) {
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loop = 1;
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n = PXA_GPIO_IRQ_BASE + bit;
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2008-10-09 12:36:24 +00:00
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generic_handle_irq(n);
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2008-03-04 03:42:26 +00:00
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bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
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}
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} while (loop);
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}
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static void pxa_ack_muxed_gpio(unsigned int irq)
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{
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int gpio = irq - IRQ_GPIO(2) + 2;
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GEDR(gpio) = GPIO_bit(gpio);
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}
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static void pxa_mask_muxed_gpio(unsigned int irq)
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{
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int gpio = irq - IRQ_GPIO(2) + 2;
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__clear_bit(gpio, GPIO_IRQ_mask);
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GRER(gpio) &= ~GPIO_bit(gpio);
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GFER(gpio) &= ~GPIO_bit(gpio);
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}
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static void pxa_unmask_muxed_gpio(unsigned int irq)
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{
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int gpio = irq - IRQ_GPIO(2) + 2;
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int idx = gpio >> 5;
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__set_bit(gpio, GPIO_IRQ_mask);
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GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
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GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
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}
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static struct irq_chip pxa_muxed_gpio_chip = {
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.name = "GPIO",
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.ack = pxa_ack_muxed_gpio,
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.mask = pxa_mask_muxed_gpio,
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.unmask = pxa_unmask_muxed_gpio,
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.set_type = pxa_gpio_irq_type,
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};
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2008-03-04 06:19:58 +00:00
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void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
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2008-03-04 03:42:26 +00:00
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{
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2008-03-04 06:19:58 +00:00
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int irq, i, gpio;
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2008-03-04 03:42:26 +00:00
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pxa_last_gpio = gpio_nr - 1;
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/* clear all GPIO edge detects */
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for (i = 0; i < gpio_nr; i += 32) {
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GFER(i) = 0;
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GRER(i) = 0;
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GEDR(i) = GEDR(i);
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}
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/* GPIO 0 and 1 must have their mask bit always set */
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GPIO_IRQ_mask[0] = 3;
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for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
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set_irq_chip(irq, &pxa_low_gpio_chip);
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set_irq_handler(irq, handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
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set_irq_chip(irq, &pxa_muxed_gpio_chip);
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set_irq_handler(irq, handle_edge_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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/* Install handler for GPIO>=2 edge detect interrupts */
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set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
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2008-03-04 06:19:58 +00:00
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pxa_low_gpio_chip.set_wake = fn;
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pxa_muxed_gpio_chip.set_wake = fn;
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2008-03-04 03:42:26 +00:00
|
|
|
|
2008-03-04 06:19:58 +00:00
|
|
|
/* add a GPIO chip for each register bank.
|
|
|
|
* the last PXA25x register only contains 21 GPIOs
|
|
|
|
*/
|
|
|
|
for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
|
|
|
|
if (gpio + 32 > gpio_nr)
|
|
|
|
pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
|
|
|
|
gpiochip_add(&pxa_gpio_chip[i].chip);
|
|
|
|
}
|
2008-03-04 03:42:26 +00:00
|
|
|
}
|
2008-03-04 08:13:58 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
|
|
|
|
static unsigned long saved_gplr[4];
|
|
|
|
static unsigned long saved_gpdr[4];
|
|
|
|
static unsigned long saved_grer[4];
|
|
|
|
static unsigned long saved_gfer[4];
|
|
|
|
|
|
|
|
static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
|
|
|
|
{
|
|
|
|
int i, gpio;
|
|
|
|
|
|
|
|
for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
|
|
|
|
saved_gplr[i] = GPLR(gpio);
|
|
|
|
saved_gpdr[i] = GPDR(gpio);
|
|
|
|
saved_grer[i] = GRER(gpio);
|
|
|
|
saved_gfer[i] = GFER(gpio);
|
|
|
|
|
|
|
|
/* Clear GPIO transition detect bits */
|
|
|
|
GEDR(gpio) = GEDR(gpio);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pxa_gpio_resume(struct sys_device *dev)
|
|
|
|
{
|
|
|
|
int i, gpio;
|
|
|
|
|
|
|
|
for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
|
|
|
|
/* restore level with set/clear */
|
|
|
|
GPSR(gpio) = saved_gplr[i];
|
|
|
|
GPCR(gpio) = ~saved_gplr[i];
|
|
|
|
|
|
|
|
GRER(gpio) = saved_grer[i];
|
|
|
|
GFER(gpio) = saved_gfer[i];
|
|
|
|
GPDR(gpio) = saved_gpdr[i];
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
#define pxa_gpio_suspend NULL
|
|
|
|
#define pxa_gpio_resume NULL
|
|
|
|
#endif
|
|
|
|
|
|
|
|
struct sysdev_class pxa_gpio_sysclass = {
|
|
|
|
.name = "gpio",
|
|
|
|
.suspend = pxa_gpio_suspend,
|
|
|
|
.resume = pxa_gpio_resume,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init pxa_gpio_init(void)
|
|
|
|
{
|
|
|
|
return sysdev_class_register(&pxa_gpio_sysclass);
|
|
|
|
}
|
|
|
|
|
|
|
|
core_initcall(pxa_gpio_init);
|