2023-06-22 11:33:39 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Renesas RZ/V2M Clocked Serial Interface (CSI) driver
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*
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* Copyright (C) 2023 Renesas Electronics Corporation
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*/
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2023-07-15 01:03:58 +00:00
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#include <linux/bits.h>
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2023-06-22 11:33:39 +00:00
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#include <linux/clk.h>
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#include <linux/count_zeros.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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2023-07-18 19:24:52 +00:00
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#include <linux/log2.h>
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spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
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#include <linux/of.h>
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2023-06-22 11:33:39 +00:00
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#include <linux/platform_device.h>
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2023-07-18 19:24:53 +00:00
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#include <linux/property.h>
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2023-06-22 11:33:39 +00:00
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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2023-07-15 01:03:59 +00:00
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#include <linux/units.h>
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2023-06-22 11:33:39 +00:00
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/* Registers */
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#define CSI_MODE 0x00 /* CSI mode control */
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#define CSI_CLKSEL 0x04 /* CSI clock select */
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#define CSI_CNT 0x08 /* CSI control */
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#define CSI_INT 0x0C /* CSI interrupt status */
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#define CSI_IFIFOL 0x10 /* CSI receive FIFO level display */
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#define CSI_OFIFOL 0x14 /* CSI transmit FIFO level display */
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#define CSI_IFIFO 0x18 /* CSI receive window */
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#define CSI_OFIFO 0x1C /* CSI transmit window */
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#define CSI_FIFOTRG 0x20 /* CSI FIFO trigger level */
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/* CSI_MODE */
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#define CSI_MODE_CSIE BIT(7)
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#define CSI_MODE_TRMD BIT(6)
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#define CSI_MODE_CCL BIT(5)
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#define CSI_MODE_DIR BIT(4)
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#define CSI_MODE_CSOT BIT(0)
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#define CSI_MODE_SETUP 0x00000040
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/* CSI_CLKSEL */
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spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
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#define CSI_CLKSEL_SS_ENA BIT(19)
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#define CSI_CLKSEL_SS_POL BIT(18)
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#define CSI_CLKSEL_SS (CSI_CLKSEL_SS_ENA | CSI_CLKSEL_SS_POL)
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#define CSI_CLKSEL_CKP BIT(17)
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#define CSI_CLKSEL_DAP BIT(16)
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2023-07-18 19:24:50 +00:00
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#define CSI_CLKSEL_MODE (CSI_CLKSEL_CKP|CSI_CLKSEL_DAP)
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2023-06-22 11:33:39 +00:00
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#define CSI_CLKSEL_SLAVE BIT(15)
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#define CSI_CLKSEL_CKS GENMASK(14, 1)
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/* CSI_CNT */
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#define CSI_CNT_CSIRST BIT(28)
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#define CSI_CNT_R_TRGEN BIT(19)
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#define CSI_CNT_UNDER_E BIT(13)
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#define CSI_CNT_OVERF_E BIT(12)
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#define CSI_CNT_TREND_E BIT(9)
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#define CSI_CNT_CSIEND_E BIT(8)
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#define CSI_CNT_T_TRGR_E BIT(4)
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#define CSI_CNT_R_TRGR_E BIT(0)
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/* CSI_INT */
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#define CSI_INT_UNDER BIT(13)
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#define CSI_INT_OVERF BIT(12)
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#define CSI_INT_TREND BIT(9)
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#define CSI_INT_CSIEND BIT(8)
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#define CSI_INT_T_TRGR BIT(4)
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#define CSI_INT_R_TRGR BIT(0)
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/* CSI_FIFOTRG */
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#define CSI_FIFOTRG_R_TRG GENMASK(2, 0)
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2023-07-18 19:24:51 +00:00
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#define CSI_FIFO_SIZE_BYTES 32U
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#define CSI_FIFO_HALF_SIZE 16U
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2023-06-22 11:33:39 +00:00
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#define CSI_EN_DIS_TIMEOUT_US 100
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2023-07-15 01:04:00 +00:00
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/*
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* Clock "csiclk" gets divided by 2 * CSI_CLKSEL_CKS in order to generate the
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* serial clock (output from master), with CSI_CLKSEL_CKS ranging from 0x1 (that
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* means "csiclk" is divided by 2) to 0x3FFF ("csiclk" is divided by 32766).
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*/
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#define CSI_CKS_MAX GENMASK(13, 0)
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2023-06-22 11:33:39 +00:00
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#define UNDERRUN_ERROR BIT(0)
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#define OVERFLOW_ERROR BIT(1)
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#define TX_TIMEOUT_ERROR BIT(2)
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#define RX_TIMEOUT_ERROR BIT(3)
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2023-07-15 01:03:59 +00:00
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#define CSI_MAX_SPI_SCKO (8 * HZ_PER_MHZ)
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2023-06-22 11:33:39 +00:00
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spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
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#define CSI_CLKSEL_SS_DISABLED 0
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#define CSI_CLKSEL_SS_ENABLED_ACTIVE_LOW BIT(1)
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#define CSI_CLKSEL_SS_ENABLED_ACTIVE_HIGH GENMASK(1, 0)
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2023-06-22 11:33:39 +00:00
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struct rzv2m_csi_priv {
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void __iomem *base;
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struct clk *csiclk;
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struct clk *pclk;
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struct device *dev;
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struct spi_controller *controller;
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2023-07-18 19:24:51 +00:00
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const void *txbuf;
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void *rxbuf;
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unsigned int buffer_len;
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unsigned int bytes_sent;
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unsigned int bytes_received;
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unsigned int bytes_to_transfer;
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unsigned int words_to_transfer;
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unsigned int bytes_per_word;
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2023-06-22 11:33:39 +00:00
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wait_queue_head_t wait;
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u32 errors;
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2023-06-22 11:33:39 +00:00
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u32 status;
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spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
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bool target_aborted;
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bool use_ss_pin;
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2023-06-22 11:33:39 +00:00
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};
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static void rzv2m_csi_reg_write_bit(const struct rzv2m_csi_priv *csi,
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int reg_offs, int bit_mask, u32 value)
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{
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int nr_zeros;
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u32 tmp;
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nr_zeros = count_trailing_zeros(bit_mask);
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value <<= nr_zeros;
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tmp = (readl(csi->base + reg_offs) & ~bit_mask) | value;
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writel(tmp, csi->base + reg_offs);
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}
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static int rzv2m_csi_sw_reset(struct rzv2m_csi_priv *csi, int assert)
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{
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u32 reg;
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rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_CSIRST, assert);
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2023-07-15 01:04:01 +00:00
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if (!assert)
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return 0;
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2023-06-22 11:33:39 +00:00
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2023-07-15 01:04:01 +00:00
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return readl_poll_timeout(csi->base + CSI_MODE, reg,
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!(reg & CSI_MODE_CSOT), 0,
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CSI_EN_DIS_TIMEOUT_US);
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2023-06-22 11:33:39 +00:00
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}
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static int rzv2m_csi_start_stop_operation(const struct rzv2m_csi_priv *csi,
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int enable, bool wait)
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{
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u32 reg;
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rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CSIE, enable);
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2023-07-15 01:04:01 +00:00
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if (enable || !wait)
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return 0;
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2023-06-22 11:33:39 +00:00
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2023-07-15 01:04:01 +00:00
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return readl_poll_timeout(csi->base + CSI_MODE, reg,
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!(reg & CSI_MODE_CSOT), 0,
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CSI_EN_DIS_TIMEOUT_US);
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2023-06-22 11:33:39 +00:00
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}
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static int rzv2m_csi_fill_txfifo(struct rzv2m_csi_priv *csi)
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{
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2023-07-18 19:24:51 +00:00
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unsigned int i;
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2023-06-22 11:33:39 +00:00
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if (readl(csi->base + CSI_OFIFOL))
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return -EIO;
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if (csi->bytes_per_word == 2) {
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2023-07-18 19:24:51 +00:00
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const u16 *buf = csi->txbuf;
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2023-06-22 11:33:39 +00:00
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for (i = 0; i < csi->words_to_transfer; i++)
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writel(buf[i], csi->base + CSI_OFIFO);
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} else {
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2023-07-18 19:24:51 +00:00
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const u8 *buf = csi->txbuf;
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2023-06-22 11:33:39 +00:00
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for (i = 0; i < csi->words_to_transfer; i++)
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writel(buf[i], csi->base + CSI_OFIFO);
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}
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csi->txbuf += csi->bytes_to_transfer;
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csi->bytes_sent += csi->bytes_to_transfer;
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return 0;
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}
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static int rzv2m_csi_read_rxfifo(struct rzv2m_csi_priv *csi)
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{
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2023-07-18 19:24:51 +00:00
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unsigned int i;
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2023-06-22 11:33:39 +00:00
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if (readl(csi->base + CSI_IFIFOL) != csi->bytes_to_transfer)
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return -EIO;
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if (csi->bytes_per_word == 2) {
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2023-07-18 19:24:51 +00:00
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u16 *buf = csi->rxbuf;
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2023-06-22 11:33:39 +00:00
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for (i = 0; i < csi->words_to_transfer; i++)
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buf[i] = (u16)readl(csi->base + CSI_IFIFO);
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} else {
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2023-07-18 19:24:51 +00:00
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u8 *buf = csi->rxbuf;
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2023-06-22 11:33:39 +00:00
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for (i = 0; i < csi->words_to_transfer; i++)
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buf[i] = (u8)readl(csi->base + CSI_IFIFO);
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}
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csi->rxbuf += csi->bytes_to_transfer;
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csi->bytes_received += csi->bytes_to_transfer;
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return 0;
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}
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spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
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static inline void rzv2m_csi_empty_rxfifo(struct rzv2m_csi_priv *csi)
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{
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unsigned int i;
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for (i = 0; i < csi->words_to_transfer; i++)
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readl(csi->base + CSI_IFIFO);
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}
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2023-06-22 11:33:39 +00:00
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static inline void rzv2m_csi_calc_current_transfer(struct rzv2m_csi_priv *csi)
|
|
|
|
|
{
|
2023-07-18 19:24:51 +00:00
|
|
|
unsigned int bytes_transferred = max(csi->bytes_received, csi->bytes_sent);
|
|
|
|
|
unsigned int bytes_remaining = csi->buffer_len - bytes_transferred;
|
|
|
|
|
unsigned int to_transfer;
|
2023-06-22 11:33:39 +00:00
|
|
|
|
|
|
|
|
if (csi->txbuf)
|
|
|
|
|
/*
|
|
|
|
|
* Leaving a little bit of headroom in the FIFOs makes it very
|
|
|
|
|
* hard to raise an overflow error (which is only possible
|
|
|
|
|
* when IP transmits and receives at the same time).
|
|
|
|
|
*/
|
2023-07-18 19:24:51 +00:00
|
|
|
to_transfer = min(CSI_FIFO_HALF_SIZE, bytes_remaining);
|
2023-06-22 11:33:39 +00:00
|
|
|
else
|
2023-07-18 19:24:51 +00:00
|
|
|
to_transfer = min(CSI_FIFO_SIZE_BYTES, bytes_remaining);
|
2023-06-22 11:33:39 +00:00
|
|
|
|
|
|
|
|
if (csi->bytes_per_word == 2)
|
|
|
|
|
to_transfer >>= 1;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We can only choose a trigger level from a predefined set of values.
|
|
|
|
|
* This will pick a value that is the greatest possible integer that's
|
|
|
|
|
* less than or equal to the number of bytes we need to transfer.
|
|
|
|
|
* This may result in multiple smaller transfers.
|
|
|
|
|
*/
|
2023-07-18 19:24:52 +00:00
|
|
|
csi->words_to_transfer = rounddown_pow_of_two(to_transfer);
|
2023-06-22 11:33:39 +00:00
|
|
|
|
|
|
|
|
if (csi->bytes_per_word == 2)
|
|
|
|
|
csi->bytes_to_transfer = csi->words_to_transfer << 1;
|
|
|
|
|
else
|
|
|
|
|
csi->bytes_to_transfer = csi->words_to_transfer;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void rzv2m_csi_set_rx_fifo_trigger_level(struct rzv2m_csi_priv *csi)
|
|
|
|
|
{
|
|
|
|
|
rzv2m_csi_reg_write_bit(csi, CSI_FIFOTRG, CSI_FIFOTRG_R_TRG,
|
2023-07-18 19:24:52 +00:00
|
|
|
ilog2(csi->words_to_transfer));
|
2023-06-22 11:33:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void rzv2m_csi_enable_rx_trigger(struct rzv2m_csi_priv *csi,
|
|
|
|
|
bool enable)
|
|
|
|
|
{
|
|
|
|
|
rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_R_TRGEN, enable);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rzv2m_csi_disable_irqs(const struct rzv2m_csi_priv *csi,
|
|
|
|
|
u32 enable_bits)
|
|
|
|
|
{
|
|
|
|
|
u32 cnt = readl(csi->base + CSI_CNT);
|
|
|
|
|
|
|
|
|
|
writel(cnt & ~enable_bits, csi->base + CSI_CNT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rzv2m_csi_disable_all_irqs(struct rzv2m_csi_priv *csi)
|
|
|
|
|
{
|
|
|
|
|
rzv2m_csi_disable_irqs(csi, CSI_CNT_R_TRGR_E | CSI_CNT_T_TRGR_E |
|
|
|
|
|
CSI_CNT_CSIEND_E | CSI_CNT_TREND_E |
|
|
|
|
|
CSI_CNT_OVERF_E | CSI_CNT_UNDER_E);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void rzv2m_csi_clear_irqs(struct rzv2m_csi_priv *csi, u32 irqs)
|
|
|
|
|
{
|
|
|
|
|
writel(irqs, csi->base + CSI_INT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rzv2m_csi_clear_all_irqs(struct rzv2m_csi_priv *csi)
|
|
|
|
|
{
|
|
|
|
|
rzv2m_csi_clear_irqs(csi, CSI_INT_UNDER | CSI_INT_OVERF |
|
|
|
|
|
CSI_INT_TREND | CSI_INT_CSIEND | CSI_INT_T_TRGR |
|
|
|
|
|
CSI_INT_R_TRGR);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rzv2m_csi_enable_irqs(struct rzv2m_csi_priv *csi, u32 enable_bits)
|
|
|
|
|
{
|
|
|
|
|
u32 cnt = readl(csi->base + CSI_CNT);
|
|
|
|
|
|
|
|
|
|
writel(cnt | enable_bits, csi->base + CSI_CNT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rzv2m_csi_wait_for_interrupt(struct rzv2m_csi_priv *csi,
|
|
|
|
|
u32 wait_mask, u32 enable_bits)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
rzv2m_csi_enable_irqs(csi, enable_bits);
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
if (spi_controller_is_target(csi->controller)) {
|
|
|
|
|
ret = wait_event_interruptible(csi->wait,
|
|
|
|
|
((csi->status & wait_mask) == wait_mask) ||
|
|
|
|
|
csi->errors || csi->target_aborted);
|
|
|
|
|
if (ret || csi->target_aborted)
|
|
|
|
|
ret = -EINTR;
|
|
|
|
|
} else {
|
|
|
|
|
ret = wait_event_timeout(csi->wait,
|
|
|
|
|
((csi->status & wait_mask) == wait_mask) ||
|
|
|
|
|
csi->errors, HZ) == 0 ? -ETIMEDOUT : 0;
|
|
|
|
|
}
|
2023-06-22 11:33:39 +00:00
|
|
|
|
|
|
|
|
rzv2m_csi_disable_irqs(csi, enable_bits);
|
|
|
|
|
|
|
|
|
|
if (csi->errors)
|
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int rzv2m_csi_wait_for_rx_ready(struct rzv2m_csi_priv *csi)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
if (readl(csi->base + CSI_IFIFOL) >= csi->bytes_to_transfer)
|
2023-06-22 11:33:39 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_R_TRGR,
|
|
|
|
|
CSI_CNT_R_TRGR_E);
|
|
|
|
|
if (ret == -ETIMEDOUT)
|
|
|
|
|
csi->errors |= RX_TIMEOUT_ERROR;
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t rzv2m_csi_irq_handler(int irq, void *data)
|
|
|
|
|
{
|
2023-07-18 19:24:51 +00:00
|
|
|
struct rzv2m_csi_priv *csi = data;
|
2023-06-22 11:33:39 +00:00
|
|
|
|
|
|
|
|
csi->status = readl(csi->base + CSI_INT);
|
|
|
|
|
rzv2m_csi_disable_irqs(csi, csi->status);
|
|
|
|
|
|
|
|
|
|
if (csi->status & CSI_INT_OVERF)
|
|
|
|
|
csi->errors |= OVERFLOW_ERROR;
|
|
|
|
|
if (csi->status & CSI_INT_UNDER)
|
|
|
|
|
csi->errors |= UNDERRUN_ERROR;
|
|
|
|
|
|
|
|
|
|
wake_up(&csi->wait);
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rzv2m_csi_setup_clock(struct rzv2m_csi_priv *csi, u32 spi_hz)
|
|
|
|
|
{
|
|
|
|
|
unsigned long csiclk_rate = clk_get_rate(csi->csiclk);
|
|
|
|
|
unsigned long pclk_rate = clk_get_rate(csi->pclk);
|
|
|
|
|
unsigned long csiclk_rate_limit = pclk_rate >> 1;
|
|
|
|
|
u32 cks;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* There is a restriction on the frequency of CSICLK, it has to be <=
|
|
|
|
|
* PCLK / 2.
|
|
|
|
|
*/
|
|
|
|
|
if (csiclk_rate > csiclk_rate_limit) {
|
|
|
|
|
clk_set_rate(csi->csiclk, csiclk_rate >> 1);
|
|
|
|
|
csiclk_rate = clk_get_rate(csi->csiclk);
|
|
|
|
|
} else if ((csiclk_rate << 1) <= csiclk_rate_limit) {
|
|
|
|
|
clk_set_rate(csi->csiclk, csiclk_rate << 1);
|
|
|
|
|
csiclk_rate = clk_get_rate(csi->csiclk);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spi_hz = spi_hz > CSI_MAX_SPI_SCKO ? CSI_MAX_SPI_SCKO : spi_hz;
|
|
|
|
|
|
|
|
|
|
cks = DIV_ROUND_UP(csiclk_rate, spi_hz << 1);
|
|
|
|
|
if (cks > CSI_CKS_MAX)
|
|
|
|
|
cks = CSI_CKS_MAX;
|
|
|
|
|
|
|
|
|
|
dev_dbg(csi->dev, "SPI clk rate is %ldHz\n", csiclk_rate / (cks << 1));
|
|
|
|
|
|
|
|
|
|
rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_CKS, cks);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void rzv2m_csi_setup_operating_mode(struct rzv2m_csi_priv *csi,
|
|
|
|
|
struct spi_transfer *t)
|
|
|
|
|
{
|
|
|
|
|
if (t->rx_buf && !t->tx_buf)
|
|
|
|
|
/* Reception-only mode */
|
|
|
|
|
rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 0);
|
|
|
|
|
else
|
|
|
|
|
/* Send and receive mode */
|
|
|
|
|
rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 1);
|
|
|
|
|
|
|
|
|
|
csi->bytes_per_word = t->bits_per_word / 8;
|
|
|
|
|
rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CCL,
|
|
|
|
|
csi->bytes_per_word == 2);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rzv2m_csi_setup(struct spi_device *spi)
|
|
|
|
|
{
|
|
|
|
|
struct rzv2m_csi_priv *csi = spi_controller_get_devdata(spi->controller);
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
u32 slave_selection = CSI_CLKSEL_SS_DISABLED;
|
2023-06-22 11:33:39 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
rzv2m_csi_sw_reset(csi, 0);
|
|
|
|
|
|
|
|
|
|
writel(CSI_MODE_SETUP, csi->base + CSI_MODE);
|
|
|
|
|
|
|
|
|
|
/* Setup clock polarity and phase timing */
|
2023-07-18 19:24:50 +00:00
|
|
|
rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_MODE,
|
|
|
|
|
~spi->mode & SPI_MODE_X_MASK);
|
2023-06-22 11:33:39 +00:00
|
|
|
|
|
|
|
|
/* Setup serial data order */
|
|
|
|
|
rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_DIR,
|
|
|
|
|
!!(spi->mode & SPI_LSB_FIRST));
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
/* Set the role, 1 for target and 0 for host */
|
|
|
|
|
rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SLAVE,
|
|
|
|
|
!!spi_controller_is_target(csi->controller));
|
|
|
|
|
|
|
|
|
|
if (csi->use_ss_pin)
|
|
|
|
|
slave_selection = spi->mode & SPI_CS_HIGH ?
|
|
|
|
|
CSI_CLKSEL_SS_ENABLED_ACTIVE_HIGH :
|
|
|
|
|
CSI_CLKSEL_SS_ENABLED_ACTIVE_LOW;
|
|
|
|
|
|
|
|
|
|
/* Configure the slave selection (SS) pin */
|
|
|
|
|
rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SS, slave_selection);
|
2023-06-22 11:33:39 +00:00
|
|
|
|
|
|
|
|
/* Give the IP a SW reset */
|
|
|
|
|
ret = rzv2m_csi_sw_reset(csi, 1);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
rzv2m_csi_sw_reset(csi, 0);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We need to enable the communication so that the clock will settle
|
|
|
|
|
* for the right polarity before enabling the CS.
|
|
|
|
|
*/
|
|
|
|
|
rzv2m_csi_start_stop_operation(csi, 1, false);
|
|
|
|
|
udelay(10);
|
|
|
|
|
rzv2m_csi_start_stop_operation(csi, 0, false);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi)
|
|
|
|
|
{
|
2023-07-15 01:04:02 +00:00
|
|
|
bool tx_completed = !csi->txbuf;
|
|
|
|
|
bool rx_completed = !csi->rxbuf;
|
2023-06-22 11:33:39 +00:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
/* Make sure the TX FIFO is empty */
|
|
|
|
|
writel(0, csi->base + CSI_OFIFOL);
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
/* Make sure the RX FIFO is empty */
|
|
|
|
|
writel(0, csi->base + CSI_IFIFOL);
|
|
|
|
|
|
2023-06-22 11:33:39 +00:00
|
|
|
csi->bytes_sent = 0;
|
|
|
|
|
csi->bytes_received = 0;
|
|
|
|
|
csi->errors = 0;
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
csi->target_aborted = false;
|
2023-06-22 11:33:39 +00:00
|
|
|
|
|
|
|
|
rzv2m_csi_disable_all_irqs(csi);
|
|
|
|
|
rzv2m_csi_clear_all_irqs(csi);
|
|
|
|
|
rzv2m_csi_enable_rx_trigger(csi, true);
|
|
|
|
|
|
|
|
|
|
while (!tx_completed || !rx_completed) {
|
|
|
|
|
/*
|
|
|
|
|
* Decide how many words we are going to transfer during
|
|
|
|
|
* this cycle (for both TX and RX), then set the RX FIFO trigger
|
|
|
|
|
* level accordingly. No need to set a trigger level for the
|
|
|
|
|
* TX FIFO, as this IP comes with an interrupt that fires when
|
|
|
|
|
* the TX FIFO is empty.
|
|
|
|
|
*/
|
|
|
|
|
rzv2m_csi_calc_current_transfer(csi);
|
|
|
|
|
rzv2m_csi_set_rx_fifo_trigger_level(csi);
|
|
|
|
|
|
|
|
|
|
rzv2m_csi_enable_irqs(csi, CSI_INT_OVERF | CSI_INT_UNDER);
|
|
|
|
|
|
|
|
|
|
writel(readl(csi->base + CSI_INT), csi->base + CSI_INT);
|
|
|
|
|
csi->status = 0;
|
|
|
|
|
|
|
|
|
|
/* TX */
|
|
|
|
|
if (csi->txbuf) {
|
|
|
|
|
ret = rzv2m_csi_fill_txfifo(csi);
|
|
|
|
|
if (ret)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
if (csi->bytes_sent == csi->buffer_len)
|
|
|
|
|
tx_completed = true;
|
|
|
|
|
}
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
rzv2m_csi_start_stop_operation(csi, 1, false);
|
|
|
|
|
|
2023-06-22 11:33:39 +00:00
|
|
|
/*
|
|
|
|
|
* Make sure the RX FIFO contains the desired number of words.
|
|
|
|
|
* We then either flush its content, or we copy it onto
|
|
|
|
|
* csi->rxbuf.
|
|
|
|
|
*/
|
|
|
|
|
ret = rzv2m_csi_wait_for_rx_ready(csi);
|
|
|
|
|
if (ret)
|
|
|
|
|
break;
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
if (!spi_controller_is_target(csi->controller))
|
2023-06-22 11:33:39 +00:00
|
|
|
rzv2m_csi_start_stop_operation(csi, 0, false);
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
/* RX */
|
|
|
|
|
if (csi->rxbuf) {
|
2023-06-22 11:33:39 +00:00
|
|
|
ret = rzv2m_csi_read_rxfifo(csi);
|
|
|
|
|
if (ret)
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
if (csi->bytes_received == csi->buffer_len)
|
|
|
|
|
rx_completed = true;
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
} else {
|
|
|
|
|
rzv2m_csi_empty_rxfifo(csi);
|
2023-06-22 11:33:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (csi->errors) {
|
|
|
|
|
ret = -EIO;
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
break;
|
2023-06-22 11:33:39 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
rzv2m_csi_start_stop_operation(csi, 0, true);
|
|
|
|
|
rzv2m_csi_disable_all_irqs(csi);
|
|
|
|
|
rzv2m_csi_enable_rx_trigger(csi, false);
|
|
|
|
|
rzv2m_csi_clear_all_irqs(csi);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rzv2m_csi_transfer_one(struct spi_controller *controller,
|
|
|
|
|
struct spi_device *spi,
|
|
|
|
|
struct spi_transfer *transfer)
|
|
|
|
|
{
|
|
|
|
|
struct rzv2m_csi_priv *csi = spi_controller_get_devdata(controller);
|
|
|
|
|
struct device *dev = csi->dev;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
csi->txbuf = transfer->tx_buf;
|
|
|
|
|
csi->rxbuf = transfer->rx_buf;
|
|
|
|
|
csi->buffer_len = transfer->len;
|
|
|
|
|
|
|
|
|
|
rzv2m_csi_setup_operating_mode(csi, transfer);
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
if (!spi_controller_is_target(csi->controller))
|
|
|
|
|
rzv2m_csi_setup_clock(csi, transfer->speed_hz);
|
2023-06-22 11:33:39 +00:00
|
|
|
|
|
|
|
|
ret = rzv2m_csi_pio_transfer(csi);
|
|
|
|
|
if (ret) {
|
|
|
|
|
if (csi->errors & UNDERRUN_ERROR)
|
|
|
|
|
dev_err(dev, "Underrun error\n");
|
|
|
|
|
if (csi->errors & OVERFLOW_ERROR)
|
|
|
|
|
dev_err(dev, "Overflow error\n");
|
|
|
|
|
if (csi->errors & TX_TIMEOUT_ERROR)
|
|
|
|
|
dev_err(dev, "TX timeout error\n");
|
|
|
|
|
if (csi->errors & RX_TIMEOUT_ERROR)
|
|
|
|
|
dev_err(dev, "RX timeout error\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
static int rzv2m_csi_target_abort(struct spi_controller *ctlr)
|
|
|
|
|
{
|
|
|
|
|
struct rzv2m_csi_priv *csi = spi_controller_get_devdata(ctlr);
|
|
|
|
|
|
|
|
|
|
csi->target_aborted = true;
|
|
|
|
|
wake_up(&csi->wait);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2023-06-22 11:33:39 +00:00
|
|
|
static int rzv2m_csi_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
struct device_node *np = pdev->dev.of_node;
|
2023-06-22 11:33:39 +00:00
|
|
|
struct spi_controller *controller;
|
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
|
struct rzv2m_csi_priv *csi;
|
|
|
|
|
struct reset_control *rstc;
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
bool target_mode;
|
2023-06-22 11:33:39 +00:00
|
|
|
int irq;
|
|
|
|
|
int ret;
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
target_mode = of_property_read_bool(np, "spi-slave");
|
|
|
|
|
|
|
|
|
|
if (target_mode)
|
|
|
|
|
controller = devm_spi_alloc_target(dev, sizeof(*csi));
|
|
|
|
|
else
|
|
|
|
|
controller = devm_spi_alloc_host(dev, sizeof(*csi));
|
|
|
|
|
|
2023-06-22 11:33:39 +00:00
|
|
|
if (!controller)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
csi = spi_controller_get_devdata(controller);
|
|
|
|
|
platform_set_drvdata(pdev, csi);
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
csi->use_ss_pin = false;
|
|
|
|
|
if (spi_controller_is_target(controller) &&
|
|
|
|
|
!of_property_read_bool(np, "renesas,csi-no-ss"))
|
|
|
|
|
csi->use_ss_pin = true;
|
|
|
|
|
|
2023-06-22 11:33:39 +00:00
|
|
|
csi->dev = dev;
|
|
|
|
|
csi->controller = controller;
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
csi->target_aborted = false;
|
2023-06-22 11:33:39 +00:00
|
|
|
|
|
|
|
|
csi->base = devm_platform_ioremap_resource(pdev, 0);
|
|
|
|
|
if (IS_ERR(csi->base))
|
|
|
|
|
return PTR_ERR(csi->base);
|
|
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
|
if (irq < 0)
|
|
|
|
|
return irq;
|
|
|
|
|
|
|
|
|
|
csi->csiclk = devm_clk_get(dev, "csiclk");
|
|
|
|
|
if (IS_ERR(csi->csiclk))
|
|
|
|
|
return dev_err_probe(dev, PTR_ERR(csi->csiclk),
|
|
|
|
|
"could not get csiclk\n");
|
|
|
|
|
|
|
|
|
|
csi->pclk = devm_clk_get(dev, "pclk");
|
|
|
|
|
if (IS_ERR(csi->pclk))
|
|
|
|
|
return dev_err_probe(dev, PTR_ERR(csi->pclk),
|
|
|
|
|
"could not get pclk\n");
|
|
|
|
|
|
|
|
|
|
rstc = devm_reset_control_get_shared(dev, NULL);
|
|
|
|
|
if (IS_ERR(rstc))
|
|
|
|
|
return dev_err_probe(dev, PTR_ERR(rstc), "Missing reset ctrl\n");
|
|
|
|
|
|
|
|
|
|
init_waitqueue_head(&csi->wait);
|
|
|
|
|
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
|
2023-06-22 11:33:39 +00:00
|
|
|
controller->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
|
|
|
|
|
controller->setup = rzv2m_csi_setup;
|
|
|
|
|
controller->transfer_one = rzv2m_csi_transfer_one;
|
|
|
|
|
controller->use_gpio_descriptors = true;
|
spi: rzv2m-csi: Add target mode support
The CSI IP found inside the Renesas RZ/V2M SoC supports
both SPI host and SPI target roles.
When working in target mode, the CSI IP has the option
of using its Slave Selection (SS) pin to enable TX and RX
operations. Since the SPI target cannot control the clock,
when working as target it's best not to stop operations
during a transfer, as by doing so the IP will not send or
receive data, regardless of clock and active level on pin SS.
A side effect from not stopping operations is that the RX
FIFO needs to be flushed, word by word, when RX data needs
to be discarded.
Finally, when in target mode timings are tighter, as missing a
deadline translates to errors being thrown, resulting in
aborting the transfer. In order to speed things up, we can
avoid waiting for the TX FIFO to be empty, we can just wait
for the RX FIFO to contain at least the number of words that
we expect.
Add target support to the currently existing CSI driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20230927162508.328736-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-09-27 16:25:08 +00:00
|
|
|
controller->target_abort = rzv2m_csi_target_abort;
|
2023-06-22 11:33:39 +00:00
|
|
|
|
2023-07-18 19:24:53 +00:00
|
|
|
device_set_node(&controller->dev, dev_fwnode(dev));
|
|
|
|
|
|
2023-06-22 11:33:39 +00:00
|
|
|
ret = devm_request_irq(dev, irq, rzv2m_csi_irq_handler, 0,
|
|
|
|
|
dev_name(dev), csi);
|
|
|
|
|
if (ret)
|
|
|
|
|
return dev_err_probe(dev, ret, "cannot request IRQ\n");
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The reset also affects other HW that is not under the control
|
|
|
|
|
* of Linux. Therefore, all we can do is make sure the reset is
|
|
|
|
|
* deasserted.
|
|
|
|
|
*/
|
|
|
|
|
reset_control_deassert(rstc);
|
|
|
|
|
|
|
|
|
|
/* Make sure the IP is in SW reset state */
|
|
|
|
|
ret = rzv2m_csi_sw_reset(csi, 1);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(csi->csiclk);
|
|
|
|
|
if (ret)
|
|
|
|
|
return dev_err_probe(dev, ret, "could not enable csiclk\n");
|
|
|
|
|
|
|
|
|
|
ret = spi_register_controller(controller);
|
|
|
|
|
if (ret) {
|
|
|
|
|
clk_disable_unprepare(csi->csiclk);
|
|
|
|
|
return dev_err_probe(dev, ret, "register controller failed\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-07 07:11:19 +00:00
|
|
|
static void rzv2m_csi_remove(struct platform_device *pdev)
|
2023-06-22 11:33:39 +00:00
|
|
|
{
|
|
|
|
|
struct rzv2m_csi_priv *csi = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
|
|
spi_unregister_controller(csi->controller);
|
|
|
|
|
rzv2m_csi_sw_reset(csi, 1);
|
|
|
|
|
clk_disable_unprepare(csi->csiclk);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct of_device_id rzv2m_csi_match[] = {
|
|
|
|
|
{ .compatible = "renesas,rzv2m-csi" },
|
|
|
|
|
{ /* sentinel */ }
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(of, rzv2m_csi_match);
|
|
|
|
|
|
|
|
|
|
static struct platform_driver rzv2m_csi_drv = {
|
|
|
|
|
.probe = rzv2m_csi_probe,
|
2023-07-07 07:11:19 +00:00
|
|
|
.remove_new = rzv2m_csi_remove,
|
2023-06-22 11:33:39 +00:00
|
|
|
.driver = {
|
|
|
|
|
.name = "rzv2m_csi",
|
|
|
|
|
.of_match_table = rzv2m_csi_match,
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
module_platform_driver(rzv2m_csi_drv);
|
|
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
MODULE_AUTHOR("Fabrizio Castro <castro.fabrizio.jz@renesas.com>");
|
|
|
|
|
MODULE_DESCRIPTION("Clocked Serial Interface Driver");
|
