2019-05-19 12:07:45 +00:00
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# SPDX-License-Identifier: GPL-2.0-only
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
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#
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# SPI driver configuration
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#
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2008-04-28 09:14:16 +00:00
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menuconfig SPI
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
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bool "SPI support"
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2008-04-28 09:14:16 +00:00
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depends on HAS_IOMEM
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
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help
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The "Serial Peripheral Interface" is a low level synchronous
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protocol. Chips that support SPI can have data transfer rates
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up to several tens of Mbit/sec. Chips are addressed with a
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controller and a chipselect. Most SPI slaves don't support
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dynamic device discovery; some are even write-only or read-only.
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2006-11-30 04:22:59 +00:00
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SPI is widely used by microcontrollers to talk with sensors,
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
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eeprom and flash memory, codecs and various other controller
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chips, analog to digital (and d-to-a) converters, and more.
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MMC and SD cards can be accessed using SPI protocol; and for
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DataFlash cards used in MMC sockets, SPI must always be used.
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SPI is one of a family of similar protocols using a four wire
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interface (select, clock, data in, data out) including Microwire
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(half duplex), SSP, SSI, and PSP. This driver framework should
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work with most such devices and controllers.
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2008-04-28 09:14:16 +00:00
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if SPI
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
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config SPI_DEBUG
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2014-12-20 20:41:11 +00:00
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bool "Debug support for SPI drivers"
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2008-04-28 09:14:16 +00:00
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depends on DEBUG_KERNEL
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
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help
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Say "yes" to enable debug messaging (like dev_dbg and pr_debug),
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sysfs, and debugfs support in SPI controller and protocol drivers.
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#
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# MASTER side ... talking to discrete SPI slave chips including microcontrollers
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#
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config SPI_MASTER
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2014-12-20 20:41:11 +00:00
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# bool "SPI Master Support"
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bool
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
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default SPI
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help
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If your system has an master-capable SPI controller (which
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provides the clock and chipselect), you can enable that
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controller and the protocol drivers for the SPI slave chips
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that are connected.
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2008-07-24 04:29:53 +00:00
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if SPI_MASTER
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2018-04-26 16:18:14 +00:00
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config SPI_MEM
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bool "SPI memory extension"
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help
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Enable this option if you want to enable the SPI memory extension.
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This extension is meant to simplify interaction with SPI memories
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2018-05-30 19:29:15 +00:00
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by providing a high-level interface to send memory-like commands.
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2018-04-26 16:18:14 +00:00
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
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comment "SPI Master Controller Drivers"
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2011-02-14 02:10:43 +00:00
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config SPI_ALTERA
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2021-04-16 16:57:19 +00:00
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tristate "Altera SPI Controller platform driver"
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select SPI_ALTERA_CORE
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2020-06-19 01:43:39 +00:00
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select REGMAP_MMIO
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2011-02-14 02:10:43 +00:00
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help
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This is the driver for the Altera SPI Controller.
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2021-04-16 16:57:19 +00:00
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config SPI_ALTERA_CORE
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2021-04-27 14:38:42 +00:00
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tristate "Altera SPI Controller core code" if COMPILE_TEST
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2021-04-16 16:57:19 +00:00
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select REGMAP
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help
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"The core code for the Altera SPI Controller"
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2021-04-16 16:57:20 +00:00
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config SPI_ALTERA_DFL
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tristate "DFL bus driver for Altera SPI Controller"
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depends on FPGA_DFL
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select SPI_ALTERA_CORE
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help
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This is a Device Feature List (DFL) bus driver for the
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Altera SPI master controller. The SPI master is connected
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to a SPI slave to Avalon bridge in a Intel MAX BMC.
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2023-04-03 18:32:17 +00:00
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config SPI_AMLOGIC_SPIFC_A1
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tristate "Amlogic A1 SPIFC controller"
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depends on ARCH_MESON || COMPILE_TEST
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help
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This enables master mode support for the SPIFC (SPI flash
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controller) available in Amlogic A1 (A113L SoC).
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2020-02-10 03:41:51 +00:00
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config SPI_AR934X
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tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
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depends on ATH79 || COMPILE_TEST
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help
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This enables support for the SPI controller present on the
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Qualcomm Atheros AR934X/QCA95XX SoCs.
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2011-01-04 20:28:22 +00:00
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config SPI_ATH79
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tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
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2019-01-16 18:55:46 +00:00
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depends on ATH79 || COMPILE_TEST
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2011-01-04 20:28:22 +00:00
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select SPI_BITBANG
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help
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This enables support for the SPI controller present on the
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Atheros AR71XX/AR724X/AR913X SoCs.
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2016-12-08 14:58:44 +00:00
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config SPI_ARMADA_3700
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tristate "Marvell Armada 3700 SPI Controller"
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depends on (ARCH_MVEBU && OF) || COMPILE_TEST
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help
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This enables support for the SPI controller present on the
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Marvell Armada 3700 SoCs.
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2022-05-09 17:56:08 +00:00
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config SPI_ASPEED_SMC
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tristate "Aspeed flash controllers in SPI mode"
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depends on ARCH_ASPEED || COMPILE_TEST
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depends on OF
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help
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This enables support for the Firmware Memory controller (FMC)
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in the Aspeed AST2600, AST2500 and AST2400 SoCs when attached
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to SPI NOR chips, and support for the SPI flash memory
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controller (SPI) for the host firmware. The implementation
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only supports SPI NOR.
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2007-02-14 08:33:09 +00:00
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config SPI_ATMEL
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tristate "Atmel SPI Controller"
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2018-03-07 22:30:54 +00:00
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depends on ARCH_AT91 || COMPILE_TEST
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2019-10-17 14:18:44 +00:00
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depends on OF
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2007-02-14 08:33:09 +00:00
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help
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This selects a driver for the Atmel SPI Controller, present on
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2018-03-07 22:30:54 +00:00
|
|
|
many AT91 ARM chips.
|
2007-02-14 08:33:09 +00:00
|
|
|
|
2018-07-13 16:47:35 +00:00
|
|
|
config SPI_AT91_USART
|
|
|
|
|
tristate "Atmel USART Controller SPI driver"
|
|
|
|
|
depends on (ARCH_AT91 || COMPILE_TEST)
|
|
|
|
|
depends on MFD_AT91_USART
|
|
|
|
|
help
|
|
|
|
|
This selects a driver for the AT91 USART Controller as SPI Master,
|
|
|
|
|
present on AT91 and SAMA5 SoC series.
|
|
|
|
|
|
2018-11-05 10:36:24 +00:00
|
|
|
config SPI_ATMEL_QUADSPI
|
|
|
|
|
tristate "Atmel Quad SPI Controller"
|
2020-07-16 04:31:39 +00:00
|
|
|
depends on ARCH_AT91 || COMPILE_TEST
|
2018-11-05 10:36:24 +00:00
|
|
|
depends on OF && HAS_IOMEM
|
|
|
|
|
help
|
|
|
|
|
This enables support for the Quad SPI controller in master mode.
|
|
|
|
|
This driver does not support generic SPI. The implementation only
|
|
|
|
|
supports spi-mem interface.
|
|
|
|
|
|
2016-02-02 11:27:42 +00:00
|
|
|
config SPI_AU1550
|
|
|
|
|
tristate "Au1550/Au1200/Au1300 SPI Controller"
|
|
|
|
|
depends on MIPS_ALCHEMY
|
|
|
|
|
select SPI_BITBANG
|
|
|
|
|
help
|
|
|
|
|
If you say yes to this option, support will be included for the
|
|
|
|
|
PSC SPI controller found on Au1550, Au1200 and Au1300 series.
|
|
|
|
|
|
2016-02-04 16:13:30 +00:00
|
|
|
config SPI_AXI_SPI_ENGINE
|
|
|
|
|
tristate "Analog Devices AXI SPI Engine controller"
|
|
|
|
|
depends on HAS_IOMEM
|
|
|
|
|
help
|
|
|
|
|
This enables support for the Analog Devices AXI SPI Engine SPI controller.
|
|
|
|
|
It is part of the SPI Engine framework that is used in some Analog Devices
|
|
|
|
|
reference designs for FPGAs.
|
|
|
|
|
|
2013-03-12 03:38:24 +00:00
|
|
|
config SPI_BCM2835
|
|
|
|
|
tristate "BCM2835 SPI controller"
|
2015-05-03 15:16:36 +00:00
|
|
|
depends on GPIOLIB
|
2019-05-09 20:36:00 +00:00
|
|
|
depends on ARCH_BCM2835 || ARCH_BRCMSTB || COMPILE_TEST
|
2013-03-12 03:38:24 +00:00
|
|
|
help
|
|
|
|
|
This selects a driver for the Broadcom BCM2835 SPI master.
|
|
|
|
|
|
|
|
|
|
The BCM2835 contains two types of SPI master controller; the
|
|
|
|
|
"universal SPI master", and the regular SPI controller. This driver
|
|
|
|
|
is for the regular SPI controller. Slave mode operation is not also
|
|
|
|
|
not supported.
|
|
|
|
|
|
2015-09-11 11:22:04 +00:00
|
|
|
config SPI_BCM2835AUX
|
|
|
|
|
tristate "BCM2835 SPI auxiliary controller"
|
2019-05-09 20:36:00 +00:00
|
|
|
depends on ((ARCH_BCM2835 || ARCH_BRCMSTB) && GPIOLIB) || COMPILE_TEST
|
2015-09-11 11:22:04 +00:00
|
|
|
help
|
|
|
|
|
This selects a driver for the Broadcom BCM2835 SPI aux master.
|
|
|
|
|
|
|
|
|
|
The BCM2835 contains two types of SPI master controller; the
|
|
|
|
|
"universal SPI master", and the regular SPI controller.
|
|
|
|
|
This driver is for the universal/auxiliary SPI controller.
|
|
|
|
|
|
2012-02-01 10:14:09 +00:00
|
|
|
config SPI_BCM63XX
|
|
|
|
|
tristate "Broadcom BCM63xx SPI controller"
|
2020-06-15 09:09:41 +00:00
|
|
|
depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST
|
2012-02-01 10:14:09 +00:00
|
|
|
help
|
2019-11-20 13:39:16 +00:00
|
|
|
Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
|
2012-02-01 10:14:09 +00:00
|
|
|
|
2013-11-30 11:42:06 +00:00
|
|
|
config SPI_BCM63XX_HSSPI
|
|
|
|
|
tristate "Broadcom BCM63XX HS SPI controller driver"
|
2022-07-07 06:57:58 +00:00
|
|
|
depends on BCM63XX || BMIPS_GENERIC || ARCH_BCMBCA || COMPILE_TEST
|
2013-11-30 11:42:06 +00:00
|
|
|
help
|
|
|
|
|
This enables support for the High Speed SPI controller present on
|
|
|
|
|
newer Broadcom BCM63XX SoCs.
|
|
|
|
|
|
2016-08-24 22:04:23 +00:00
|
|
|
config SPI_BCM_QSPI
|
|
|
|
|
tristate "Broadcom BSPI and MSPI controller support"
|
2016-12-30 06:30:00 +00:00
|
|
|
depends on ARCH_BRCMSTB || ARCH_BCM || ARCH_BCM_IPROC || \
|
|
|
|
|
BMIPS_GENERIC || COMPILE_TEST
|
2016-08-24 22:04:23 +00:00
|
|
|
default ARCH_BCM_IPROC
|
|
|
|
|
help
|
|
|
|
|
Enables support for the Broadcom SPI flash and MSPI controller.
|
|
|
|
|
Select this option for any one of BRCMSTB, iProc NSP and NS2 SoCs
|
2020-07-16 05:11:44 +00:00
|
|
|
based platforms. This driver works for both SPI master for SPI NOR
|
2016-08-24 22:04:23 +00:00
|
|
|
flash device as well as MSPI device.
|
|
|
|
|
|
2023-02-09 20:02:45 +00:00
|
|
|
config SPI_BCMBCA_HSSPI
|
|
|
|
|
tristate "Broadcom BCMBCA HS SPI controller driver"
|
|
|
|
|
depends on ARCH_BCMBCA || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This enables support for the High Speed SPI controller present on
|
|
|
|
|
newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller
|
|
|
|
|
that adds the capability to allow the driver to control chip select
|
|
|
|
|
explicitly.
|
|
|
|
|
|
2006-01-08 21:34:26 +00:00
|
|
|
config SPI_BITBANG
|
2009-01-06 22:41:41 +00:00
|
|
|
tristate "Utilities for Bitbanging SPI masters"
|
2006-01-08 21:34:26 +00:00
|
|
|
help
|
|
|
|
|
With a few GPIO pins, your system can bitbang the SPI protocol.
|
|
|
|
|
Select this to get SPI support through I/O pins (GPIO, parallel
|
|
|
|
|
port, etc). Or, some systems' SPI master controller drivers use
|
|
|
|
|
this code to manage the per-word or per-transfer accesses to the
|
|
|
|
|
hardware shift registers.
|
|
|
|
|
|
|
|
|
|
This is library code, and is automatically selected by drivers that
|
|
|
|
|
need it. You only need to select this explicitly to support driver
|
|
|
|
|
modules that aren't part of this kernel tree.
|
[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
|
|
|
|
2006-01-08 21:34:29 +00:00
|
|
|
config SPI_BUTTERFLY
|
|
|
|
|
tristate "Parallel port adapter for AVR Butterfly (DEVELOPMENT)"
|
2008-07-24 04:29:53 +00:00
|
|
|
depends on PARPORT
|
2006-01-08 21:34:29 +00:00
|
|
|
select SPI_BITBANG
|
|
|
|
|
help
|
|
|
|
|
This uses a custom parallel port cable to connect to an AVR
|
|
|
|
|
Butterfly <http://www.atmel.com/products/avr/butterfly>, an
|
|
|
|
|
inexpensive battery powered microcontroller evaluation board.
|
|
|
|
|
This same cable can be used to flash new firmware.
|
|
|
|
|
|
2014-04-14 09:06:53 +00:00
|
|
|
config SPI_CADENCE
|
|
|
|
|
tristate "Cadence SPI controller"
|
|
|
|
|
help
|
|
|
|
|
This selects the Cadence SPI controller master driver
|
2015-03-09 08:46:15 +00:00
|
|
|
used by Xilinx Zynq and ZynqMP.
|
2014-04-14 09:06:53 +00:00
|
|
|
|
2020-06-01 07:04:44 +00:00
|
|
|
config SPI_CADENCE_QUADSPI
|
|
|
|
|
tristate "Cadence Quad SPI controller"
|
2023-03-02 10:52:21 +00:00
|
|
|
depends on OF && (ARM || ARM64 || X86 || RISCV || COMPILE_TEST)
|
2020-06-01 07:04:44 +00:00
|
|
|
help
|
|
|
|
|
Enable support for the Cadence Quad SPI Flash controller.
|
|
|
|
|
|
|
|
|
|
Cadence QSPI is a specialized controller for connecting an SPI
|
|
|
|
|
Flash over 1/2/4-bit wide bus. Enable this option if you have a
|
|
|
|
|
device with a Cadence QSPI controller and want to access the
|
|
|
|
|
Flash as an MTD device.
|
|
|
|
|
|
2021-09-19 08:05:34 +00:00
|
|
|
config SPI_CADENCE_XSPI
|
|
|
|
|
tristate "Cadence XSPI controller"
|
2022-11-25 07:31:14 +00:00
|
|
|
depends on OF && HAS_IOMEM
|
2021-09-19 08:05:34 +00:00
|
|
|
depends on SPI_MEM
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Cadence XSPI Flash controller.
|
|
|
|
|
|
|
|
|
|
Cadence XSPI is a specialized controller for connecting an SPI
|
2023-01-24 23:35:02 +00:00
|
|
|
Flash over up to 8-bit wide bus. Enable this option if you have a
|
2021-09-19 08:05:34 +00:00
|
|
|
device with a Cadence XSPI controller and want to access the
|
|
|
|
|
Flash as an MTD device.
|
|
|
|
|
|
2012-11-07 17:30:29 +00:00
|
|
|
config SPI_CLPS711X
|
|
|
|
|
tristate "CLPS711X host SPI controller"
|
2014-03-26 08:53:18 +00:00
|
|
|
depends on ARCH_CLPS711X || COMPILE_TEST
|
2012-11-07 17:30:29 +00:00
|
|
|
help
|
|
|
|
|
This enables dedicated general purpose SPI/Microwire1-compatible
|
|
|
|
|
master mode interface (SSI1) for CLPS711X-based CPUs.
|
|
|
|
|
|
2010-01-20 20:49:44 +00:00
|
|
|
config SPI_COLDFIRE_QSPI
|
|
|
|
|
tristate "Freescale Coldfire QSPI controller"
|
2012-06-05 16:24:59 +00:00
|
|
|
depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
|
2010-01-20 20:49:44 +00:00
|
|
|
help
|
|
|
|
|
This enables support for the Coldfire QSPI controller in master
|
|
|
|
|
mode.
|
|
|
|
|
|
2009-12-16 22:02:18 +00:00
|
|
|
config SPI_DAVINCI
|
2010-10-12 06:28:02 +00:00
|
|
|
tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller"
|
2023-02-23 17:20:24 +00:00
|
|
|
depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST
|
2009-12-16 22:02:18 +00:00
|
|
|
select SPI_BITBANG
|
|
|
|
|
help
|
2010-10-12 06:28:02 +00:00
|
|
|
SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules.
|
|
|
|
|
|
2016-02-02 11:27:42 +00:00
|
|
|
config SPI_DESIGNWARE
|
|
|
|
|
tristate "DesignWare SPI controller core support"
|
2020-10-07 23:55:06 +00:00
|
|
|
imply SPI_MEM
|
2016-02-02 11:27:42 +00:00
|
|
|
help
|
|
|
|
|
general driver for SPI controller core from DesignWare
|
|
|
|
|
|
2020-05-29 13:12:01 +00:00
|
|
|
if SPI_DESIGNWARE
|
|
|
|
|
|
2020-05-29 13:11:59 +00:00
|
|
|
config SPI_DW_DMA
|
|
|
|
|
bool "DMA support for DW SPI controller"
|
|
|
|
|
|
2016-02-02 11:27:42 +00:00
|
|
|
config SPI_DW_PCI
|
|
|
|
|
tristate "PCI interface driver for DW SPI core"
|
2020-05-29 13:12:01 +00:00
|
|
|
depends on PCI
|
2016-02-02 11:27:42 +00:00
|
|
|
|
|
|
|
|
config SPI_DW_MMIO
|
|
|
|
|
tristate "Memory-mapped io interface driver for DW SPI core"
|
2020-05-29 13:12:01 +00:00
|
|
|
depends on HAS_IOMEM
|
|
|
|
|
|
2020-10-07 23:55:10 +00:00
|
|
|
config SPI_DW_BT1
|
|
|
|
|
tristate "Baikal-T1 SPI driver for DW SPI core"
|
|
|
|
|
depends on MIPS_BAIKAL_T1 || COMPILE_TEST
|
2020-11-27 14:46:11 +00:00
|
|
|
select MULTIPLEXER
|
2020-10-07 23:55:10 +00:00
|
|
|
help
|
|
|
|
|
Baikal-T1 SoC is equipped with three DW APB SSI-based MMIO SPI
|
|
|
|
|
controllers. Two of them are pretty much normal: with IRQ, DMA,
|
|
|
|
|
FIFOs of 64 words depth, 4x CSs, but the third one as being a
|
|
|
|
|
part of the Baikal-T1 System Boot Controller has got a very
|
|
|
|
|
limited resources: no IRQ, no DMA, only a single native
|
|
|
|
|
chip-select and Tx/Rx FIFO with just 8 words depth available.
|
|
|
|
|
The later one is normally connected to an external SPI-nor flash
|
|
|
|
|
of 128Mb (in general can be of bigger size).
|
|
|
|
|
|
|
|
|
|
config SPI_DW_BT1_DIRMAP
|
|
|
|
|
bool "Directly mapped Baikal-T1 Boot SPI flash support"
|
|
|
|
|
depends on SPI_DW_BT1
|
|
|
|
|
help
|
|
|
|
|
Directly mapped SPI flash memory is an interface specific to the
|
|
|
|
|
Baikal-T1 System Boot Controller. It is a 16MB MMIO region, which
|
|
|
|
|
can be used to access a peripheral memory device just by
|
|
|
|
|
reading/writing data from/to it. Note that the system APB bus
|
|
|
|
|
will stall during each IO from/to the dirmap region until the
|
|
|
|
|
operation is finished. So try not to use it concurrently with
|
|
|
|
|
time-critical tasks (like the SPI memory operations implemented
|
|
|
|
|
in this driver).
|
|
|
|
|
|
2020-05-29 13:12:01 +00:00
|
|
|
endif
|
2016-02-02 11:27:42 +00:00
|
|
|
|
2014-12-08 13:52:29 +00:00
|
|
|
config SPI_DLN2
|
|
|
|
|
tristate "Diolan DLN-2 USB SPI adapter"
|
|
|
|
|
depends on MFD_DLN2
|
|
|
|
|
help
|
2019-11-20 13:39:16 +00:00
|
|
|
If you say yes to this option, support will be included for Diolan
|
|
|
|
|
DLN2, a USB to SPI interface.
|
2014-12-08 13:52:29 +00:00
|
|
|
|
2019-11-20 13:39:16 +00:00
|
|
|
This driver can also be built as a module. If so, the module
|
|
|
|
|
will be called spi-dln2.
|
2014-12-08 13:52:29 +00:00
|
|
|
|
2010-05-06 04:47:04 +00:00
|
|
|
config SPI_EP93XX
|
|
|
|
|
tristate "Cirrus Logic EP93xx SPI controller"
|
2013-07-05 18:42:58 +00:00
|
|
|
depends on ARCH_EP93XX || COMPILE_TEST
|
2010-05-06 04:47:04 +00:00
|
|
|
help
|
|
|
|
|
This enables using the Cirrus EP93xx SPI controller in master
|
|
|
|
|
mode.
|
|
|
|
|
|
2012-05-20 13:46:19 +00:00
|
|
|
config SPI_FALCON
|
2017-01-03 17:04:27 +00:00
|
|
|
bool "Falcon SPI controller support"
|
2012-05-20 13:46:19 +00:00
|
|
|
depends on SOC_FALCON
|
|
|
|
|
help
|
|
|
|
|
The external bus unit (EBU) found on the FALC-ON SoC has SPI
|
|
|
|
|
emulation that is designed for serial flash access. This driver
|
|
|
|
|
has only been tested with m25p80 type chips. The hardware has no
|
|
|
|
|
support for other types of SPI peripherals.
|
|
|
|
|
|
2020-03-06 19:41:18 +00:00
|
|
|
config SPI_FSI
|
|
|
|
|
tristate "FSI SPI driver"
|
2023-03-10 14:05:37 +00:00
|
|
|
depends on FSI
|
2020-03-06 19:41:18 +00:00
|
|
|
help
|
|
|
|
|
This enables support for the driver for FSI bus attached SPI
|
|
|
|
|
controllers.
|
|
|
|
|
|
2016-11-22 13:52:17 +00:00
|
|
|
config SPI_FSL_LPSPI
|
|
|
|
|
tristate "Freescale i.MX LPSPI controller"
|
|
|
|
|
depends on ARCH_MXC || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This enables Freescale i.MX LPSPI controllers in master mode.
|
|
|
|
|
|
2019-01-07 09:29:47 +00:00
|
|
|
config SPI_FSL_QUADSPI
|
|
|
|
|
tristate "Freescale QSPI controller"
|
|
|
|
|
depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
|
|
|
|
|
depends on HAS_IOMEM
|
|
|
|
|
help
|
|
|
|
|
This enables support for the Quad SPI controller in master mode.
|
|
|
|
|
Up to four flash chips can be connected on two buses with two
|
|
|
|
|
chipselects each.
|
|
|
|
|
This controller does not support generic SPI messages. It only
|
|
|
|
|
supports the high-level SPI memory interface.
|
|
|
|
|
|
2022-07-28 16:14:55 +00:00
|
|
|
config SPI_GXP
|
|
|
|
|
tristate "GXP SPI driver"
|
|
|
|
|
depends on ARCH_HPE || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This enables support for the driver for GXP bus attached SPI
|
|
|
|
|
controllers.
|
|
|
|
|
|
2021-03-27 09:10:00 +00:00
|
|
|
config SPI_HISI_KUNPENG
|
|
|
|
|
tristate "HiSilicon SPI Controller for Kunpeng SoCs"
|
|
|
|
|
depends on (ARM64 && ACPI) || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This enables support for HiSilicon SPI controller found on
|
|
|
|
|
Kunpeng SoCs.
|
|
|
|
|
|
|
|
|
|
This driver can also be built as a module. If so, the module
|
|
|
|
|
will be called hisi-kunpeng-spi.
|
|
|
|
|
|
2019-12-09 14:08:09 +00:00
|
|
|
config SPI_HISI_SFC_V3XX
|
2020-07-16 05:11:44 +00:00
|
|
|
tristate "HiSilicon SPI NOR Flash Controller for Hi16XX chipsets"
|
2019-12-09 14:08:09 +00:00
|
|
|
depends on (ARM64 && ACPI) || COMPILE_TEST
|
|
|
|
|
depends on HAS_IOMEM
|
|
|
|
|
help
|
2020-07-16 05:11:44 +00:00
|
|
|
This enables support for HiSilicon v3xx SPI NOR flash controller
|
2019-12-09 14:08:09 +00:00
|
|
|
found in hi16xx chipsets.
|
|
|
|
|
|
2019-01-15 12:00:15 +00:00
|
|
|
config SPI_NXP_FLEXSPI
|
|
|
|
|
tristate "NXP Flex SPI controller"
|
2023-03-13 08:36:21 +00:00
|
|
|
depends on ARCH_LAYERSCAPE || ARCH_MXC || COMPILE_TEST
|
2023-02-23 17:20:23 +00:00
|
|
|
depends on HAS_IOMEM
|
2019-01-15 12:00:15 +00:00
|
|
|
help
|
|
|
|
|
This enables support for the Flex SPI controller in master mode.
|
|
|
|
|
Up to four slave devices can be connected on two buses with two
|
|
|
|
|
chipselects each.
|
|
|
|
|
This controller does not support generic SPI messages and only
|
|
|
|
|
supports the high-level SPI memory interface.
|
|
|
|
|
|
2009-01-06 22:41:41 +00:00
|
|
|
config SPI_GPIO
|
|
|
|
|
tristate "GPIO-based bitbanging SPI Master"
|
2015-05-05 16:32:33 +00:00
|
|
|
depends on GPIOLIB || COMPILE_TEST
|
2009-01-06 22:41:41 +00:00
|
|
|
select SPI_BITBANG
|
|
|
|
|
help
|
|
|
|
|
This simple GPIO bitbanging SPI master uses the arch-neutral GPIO
|
|
|
|
|
interface to manage MOSI, MISO, SCK, and chipselect signals. SPI
|
|
|
|
|
slaves connected to a bus using this driver are configured as usual,
|
|
|
|
|
except that the spi_board_info.controller_data holds the GPIO number
|
|
|
|
|
for the chipselect used by this controller driver.
|
|
|
|
|
|
|
|
|
|
Note that this driver often won't achieve even 1 Mbit/sec speeds,
|
|
|
|
|
making it unusually slow for SPI. If your platform can inline
|
|
|
|
|
GPIO operations, you should be able to leverage that for better
|
|
|
|
|
speed with a custom version of this driver; see the source code.
|
|
|
|
|
|
2014-11-14 18:48:32 +00:00
|
|
|
config SPI_IMG_SPFI
|
|
|
|
|
tristate "IMG SPFI controller"
|
|
|
|
|
depends on MIPS || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This enables support for the SPFI master controller found on
|
|
|
|
|
IMG SoCs.
|
|
|
|
|
|
2009-09-22 23:46:02 +00:00
|
|
|
config SPI_IMX
|
|
|
|
|
tristate "Freescale i.MX SPI controllers"
|
2013-07-05 18:42:58 +00:00
|
|
|
depends on ARCH_MXC || COMPILE_TEST
|
2009-09-22 23:46:02 +00:00
|
|
|
help
|
2019-01-26 21:32:07 +00:00
|
|
|
This enables support for the Freescale i.MX SPI controllers.
|
2009-09-22 23:46:02 +00:00
|
|
|
|
2021-08-30 23:01:38 +00:00
|
|
|
config SPI_INGENIC
|
spi: ingenic: Add support for new Ingenic SoCs.
1.Since it would be dangerous to specify a newer SoC's compatible
string as the fallback of an older SoC's compatible string, we
add support for the "ingenic,jz4775-spi" compatible string in
the driver.
This will permit to support the JZ4775 by having:
compatible = "ingenic,jz4775-spi";
Instead of doing:
compatible = "ingenic,jz4775-spi", "ingenic,jz4780-spi";
2.Add support for probing the spi-ingenic driver on the X1000 SoC
from Ingenic. From the X1000 SoC onwards, the maximum frequency
allowed by the SSI module of Ingenic SoCs has been changed from
54MHz to 50MHz. So "max_speed_hz" is introduced in "jz_soc_info"
to set different maximum frequency values.
3.Add support for probing the spi-ingenic driver on the X2000 SoC
from Ingenic. The X2000 SoC has only one native chip select line,
so "max_native_cs" is introduced in "jz_soc_info" to set different
maximum number of native chip select lines.
4.Because of the introduction of support for the X-series SoCs, the
current driver is not only applicable to the JZ-series SoCs, so
the description texts has been modified to avoid misunderstanding.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/1650724725-93758-4-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-23 14:38:45 +00:00
|
|
|
tristate "Ingenic SoCs SPI controller"
|
2021-08-30 23:01:38 +00:00
|
|
|
depends on MACH_INGENIC || COMPILE_TEST
|
|
|
|
|
help
|
spi: ingenic: Add support for new Ingenic SoCs.
1.Since it would be dangerous to specify a newer SoC's compatible
string as the fallback of an older SoC's compatible string, we
add support for the "ingenic,jz4775-spi" compatible string in
the driver.
This will permit to support the JZ4775 by having:
compatible = "ingenic,jz4775-spi";
Instead of doing:
compatible = "ingenic,jz4775-spi", "ingenic,jz4780-spi";
2.Add support for probing the spi-ingenic driver on the X1000 SoC
from Ingenic. From the X1000 SoC onwards, the maximum frequency
allowed by the SSI module of Ingenic SoCs has been changed from
54MHz to 50MHz. So "max_speed_hz" is introduced in "jz_soc_info"
to set different maximum frequency values.
3.Add support for probing the spi-ingenic driver on the X2000 SoC
from Ingenic. The X2000 SoC has only one native chip select line,
so "max_native_cs" is introduced in "jz_soc_info" to set different
maximum number of native chip select lines.
4.Because of the introduction of support for the X-series SoCs, the
current driver is not only applicable to the JZ-series SoCs, so
the description texts has been modified to avoid misunderstanding.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/1650724725-93758-4-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-23 14:38:45 +00:00
|
|
|
This enables support for the Ingenic SoCs SPI controller.
|
2021-08-30 23:01:38 +00:00
|
|
|
|
|
|
|
|
To compile this driver as a module, choose M here: the module
|
|
|
|
|
will be called spi-ingenic.
|
|
|
|
|
|
2022-02-09 12:27:05 +00:00
|
|
|
config SPI_INTEL
|
|
|
|
|
tristate
|
|
|
|
|
|
|
|
|
|
config SPI_INTEL_PCI
|
2023-02-06 18:31:43 +00:00
|
|
|
tristate "Intel PCH/PCU SPI flash PCI driver"
|
2022-02-09 12:27:05 +00:00
|
|
|
depends on PCI
|
|
|
|
|
depends on X86 || COMPILE_TEST
|
|
|
|
|
depends on SPI_MEM
|
|
|
|
|
select SPI_INTEL
|
|
|
|
|
help
|
|
|
|
|
This enables PCI support for the Intel PCH/PCU SPI controller in
|
2023-02-10 16:41:58 +00:00
|
|
|
master mode. This controller is used to hold BIOS and other
|
|
|
|
|
persistent settings. Controllers present in modern Intel hardware
|
|
|
|
|
only work in hardware sequencing mode, this means that the
|
|
|
|
|
controller exposes a subset of operations that makes it safer to
|
|
|
|
|
use. Using this driver it is possible to upgrade BIOS directly
|
|
|
|
|
from Linux.
|
2022-02-09 12:27:05 +00:00
|
|
|
|
|
|
|
|
To compile this driver as a module, choose M here: the module
|
|
|
|
|
will be called spi-intel-pci.
|
|
|
|
|
|
|
|
|
|
config SPI_INTEL_PLATFORM
|
|
|
|
|
tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)"
|
|
|
|
|
depends on X86 || COMPILE_TEST
|
|
|
|
|
depends on SPI_MEM
|
|
|
|
|
select SPI_INTEL
|
|
|
|
|
help
|
|
|
|
|
This enables platform support for the Intel PCH/PCU SPI
|
2023-02-06 18:31:43 +00:00
|
|
|
controller in master mode that is used to hold BIOS and other
|
2023-02-10 16:41:58 +00:00
|
|
|
persistent settings. Most of these controllers work in
|
|
|
|
|
software sequencing mode, which means that the controller
|
|
|
|
|
exposes the low level SPI-NOR opcodes to the software. Using
|
|
|
|
|
this driver it is possible to upgrade BIOS directly from Linux.
|
2022-02-09 12:27:05 +00:00
|
|
|
|
|
|
|
|
Say N here unless you know what you are doing. Overwriting the
|
|
|
|
|
SPI flash may render the system unbootable.
|
|
|
|
|
|
|
|
|
|
To compile this driver as a module, choose M here: the module
|
|
|
|
|
will be called spi-intel-platform.
|
|
|
|
|
|
2016-08-04 04:30:37 +00:00
|
|
|
config SPI_JCORE
|
|
|
|
|
tristate "J-Core SPI Master"
|
|
|
|
|
depends on OF && (SUPERH || COMPILE_TEST)
|
|
|
|
|
help
|
|
|
|
|
This enables support for the SPI master controller in the J-Core
|
|
|
|
|
synthesizable, open source SoC.
|
|
|
|
|
|
2007-07-17 11:04:05 +00:00
|
|
|
config SPI_LM70_LLP
|
|
|
|
|
tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
|
2013-01-17 02:53:55 +00:00
|
|
|
depends on PARPORT
|
2007-07-17 11:04:05 +00:00
|
|
|
select SPI_BITBANG
|
|
|
|
|
help
|
|
|
|
|
This driver supports the NS LM70 LLP Evaluation Board,
|
|
|
|
|
which interfaces to an LM70 temperature sensor using
|
|
|
|
|
a parallel port.
|
|
|
|
|
|
2016-02-23 10:44:28 +00:00
|
|
|
config SPI_LP8841_RTC
|
|
|
|
|
tristate "ICP DAS LP-8841 SPI Controller for RTC"
|
|
|
|
|
depends on MACH_PXA27X_DT || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This driver provides an SPI master device to drive Maxim
|
|
|
|
|
DS-1302 real time clock.
|
|
|
|
|
|
|
|
|
|
Say N here unless you plan to run the kernel on an ICP DAS
|
|
|
|
|
LP-8x4x industrial computer.
|
|
|
|
|
|
2009-11-04 22:34:18 +00:00
|
|
|
config SPI_MPC52xx
|
|
|
|
|
tristate "Freescale MPC52xx SPI (non-PSC) controller support"
|
2011-11-13 21:52:40 +00:00
|
|
|
depends on PPC_MPC52xx
|
2009-11-04 22:34:18 +00:00
|
|
|
help
|
|
|
|
|
This drivers supports the MPC52xx SPI controller in master SPI
|
|
|
|
|
mode.
|
|
|
|
|
|
2007-05-11 05:22:52 +00:00
|
|
|
config SPI_MPC52xx_PSC
|
|
|
|
|
tristate "Freescale MPC52xx PSC SPI controller"
|
2013-01-17 02:53:55 +00:00
|
|
|
depends on PPC_MPC52xx
|
2007-05-11 05:22:52 +00:00
|
|
|
help
|
|
|
|
|
This enables using the Freescale MPC52xx Programmable Serial
|
|
|
|
|
Controller in master SPI mode.
|
|
|
|
|
|
2010-04-30 13:21:27 +00:00
|
|
|
config SPI_MPC512x_PSC
|
|
|
|
|
tristate "Freescale MPC512x PSC SPI controller"
|
2012-02-23 09:37:55 +00:00
|
|
|
depends on PPC_MPC512x
|
2010-04-30 13:21:27 +00:00
|
|
|
help
|
|
|
|
|
This enables using the Freescale MPC5121 Programmable Serial
|
|
|
|
|
Controller in SPI master mode.
|
|
|
|
|
|
2010-10-12 10:18:31 +00:00
|
|
|
config SPI_FSL_LIB
|
2013-02-15 15:52:21 +00:00
|
|
|
tristate
|
|
|
|
|
depends on OF
|
|
|
|
|
|
|
|
|
|
config SPI_FSL_CPM
|
2010-10-12 10:18:31 +00:00
|
|
|
tristate
|
|
|
|
|
depends on FSL_SOC
|
|
|
|
|
|
2010-10-12 10:18:30 +00:00
|
|
|
config SPI_FSL_SPI
|
2015-01-06 13:07:34 +00:00
|
|
|
tristate "Freescale SPI controller and Aeroflex Gaisler GRLIB SPI controller"
|
2013-02-15 15:52:21 +00:00
|
|
|
depends on OF
|
2010-10-12 10:18:31 +00:00
|
|
|
select SPI_FSL_LIB
|
2013-02-15 15:52:21 +00:00
|
|
|
select SPI_FSL_CPM if FSL_SOC
|
2006-05-20 22:00:15 +00:00
|
|
|
help
|
2010-10-12 10:18:30 +00:00
|
|
|
This enables using the Freescale SPI controllers in master mode.
|
|
|
|
|
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
|
|
|
|
|
MPC8569 uses the controller in QE mode, MPC8610 in cpu mode.
|
2013-02-15 15:52:26 +00:00
|
|
|
This also enables using the Aeroflex Gaisler GRLIB SPI controller in
|
|
|
|
|
master mode.
|
2006-05-20 22:00:15 +00:00
|
|
|
|
2013-08-16 03:08:55 +00:00
|
|
|
config SPI_FSL_DSPI
|
|
|
|
|
tristate "Freescale DSPI controller"
|
2014-02-12 07:29:05 +00:00
|
|
|
select REGMAP_MMIO
|
2017-10-27 22:23:01 +00:00
|
|
|
depends on SOC_VF610 || SOC_LS1021A || ARCH_LAYERSCAPE || M5441x || COMPILE_TEST
|
2013-08-16 03:08:55 +00:00
|
|
|
help
|
|
|
|
|
This enables support for the Freescale DSPI controller in master
|
2018-12-26 21:43:00 +00:00
|
|
|
mode. VF610, LS1021A and ColdFire platforms uses the controller.
|
2013-08-16 03:08:55 +00:00
|
|
|
|
spi/fsl_spi: add eSPI controller support
Add eSPI controller support based on the library code spi_fsl_lib.c.
The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:
1. Has different register map and different bit definition
So leave the code operated the register to the driver code, not
the common code.
2. Support 4 dedicated chip selects
The software can't controll the chip selects directly, The SPCOM[CS]
field is used to select which chip selects is used, and the
SPCOM[TRANLEN] field is set to tell the controller how long the CS
signal need to be asserted. So the driver doesn't need the chipselect
related function when transfering data, just set corresponding register
fields to controll the chipseclect.
3. Different Transmit/Receive FIFO access register behavior
For SPI controller, the Tx/Rx FIFO access register can hold only
one character regardless of the character length, but for eSPI
controller, the register can hold 4 or 2 characters according to
the character lengths. Access the Tx/Rx FIFO access register of the
eSPI controller will shift out/in 4/2 characters one time. For SPI
subsystem, the command and data are put into different transfers, so
we need to combine all the transfers to one transfer in order to pass
the transfer to eSPI controller.
4. The max transaction length limitation
The max transaction length one time is limitted by the SPCOM[TRANSLEN]
field which is 0xFFFF. When used mkfs.ext2 command to create ext2
filesystem on the flash, the read length will exceed the max value of
the SPCOM[TRANSLEN] field.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 10:18:32 +00:00
|
|
|
config SPI_FSL_ESPI
|
2015-01-06 13:07:34 +00:00
|
|
|
tristate "Freescale eSPI controller"
|
spi/fsl_spi: add eSPI controller support
Add eSPI controller support based on the library code spi_fsl_lib.c.
The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:
1. Has different register map and different bit definition
So leave the code operated the register to the driver code, not
the common code.
2. Support 4 dedicated chip selects
The software can't controll the chip selects directly, The SPCOM[CS]
field is used to select which chip selects is used, and the
SPCOM[TRANLEN] field is set to tell the controller how long the CS
signal need to be asserted. So the driver doesn't need the chipselect
related function when transfering data, just set corresponding register
fields to controll the chipseclect.
3. Different Transmit/Receive FIFO access register behavior
For SPI controller, the Tx/Rx FIFO access register can hold only
one character regardless of the character length, but for eSPI
controller, the register can hold 4 or 2 characters according to
the character lengths. Access the Tx/Rx FIFO access register of the
eSPI controller will shift out/in 4/2 characters one time. For SPI
subsystem, the command and data are put into different transfers, so
we need to combine all the transfers to one transfer in order to pass
the transfer to eSPI controller.
4. The max transaction length limitation
The max transaction length one time is limitted by the SPCOM[TRANSLEN]
field which is 0xFFFF. When used mkfs.ext2 command to create ext2
filesystem on the flash, the read length will exceed the max value of
the SPCOM[TRANSLEN] field.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 10:18:32 +00:00
|
|
|
depends on FSL_SOC
|
|
|
|
|
help
|
|
|
|
|
This enables using the Freescale eSPI controllers in master mode.
|
|
|
|
|
From MPC8536, 85xx platform uses the controller, and all P10xx,
|
|
|
|
|
P20xx, P30xx,P40xx, P50xx uses this controller.
|
|
|
|
|
|
2017-05-23 13:39:33 +00:00
|
|
|
config SPI_MESON_SPICC
|
|
|
|
|
tristate "Amlogic Meson SPICC controller"
|
2020-03-12 13:31:25 +00:00
|
|
|
depends on COMMON_CLK
|
2017-05-23 13:39:33 +00:00
|
|
|
depends on ARCH_MESON || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This enables master mode support for the SPICC (SPI communication
|
|
|
|
|
controller) available in Amlogic Meson SoCs.
|
|
|
|
|
|
2014-11-22 15:21:41 +00:00
|
|
|
config SPI_MESON_SPIFC
|
|
|
|
|
tristate "Amlogic Meson SPIFC controller"
|
|
|
|
|
depends on ARCH_MESON || COMPILE_TEST
|
2014-11-26 23:07:48 +00:00
|
|
|
select REGMAP_MMIO
|
2014-11-22 15:21:41 +00:00
|
|
|
help
|
|
|
|
|
This enables master mode support for the SPIFC (SPI flash
|
|
|
|
|
controller) available in Amlogic Meson SoCs.
|
|
|
|
|
|
2022-06-07 07:38:33 +00:00
|
|
|
config SPI_MICROCHIP_CORE
|
|
|
|
|
tristate "Microchip FPGA SPI controllers"
|
|
|
|
|
depends on SPI_MASTER
|
|
|
|
|
help
|
|
|
|
|
This enables the SPI driver for Microchip FPGA SPI controllers.
|
|
|
|
|
Say Y or M here if you want to use the "hard" controllers on
|
|
|
|
|
PolarFire SoC.
|
|
|
|
|
If built as a module, it will be called spi-microchip-core.
|
|
|
|
|
|
2022-08-08 06:46:02 +00:00
|
|
|
config SPI_MICROCHIP_CORE_QSPI
|
|
|
|
|
tristate "Microchip FPGA QSPI controllers"
|
|
|
|
|
depends on SPI_MASTER
|
|
|
|
|
help
|
|
|
|
|
This enables the QSPI driver for Microchip FPGA QSPI controllers.
|
|
|
|
|
Say Y or M here if you want to use the QSPI controllers on
|
|
|
|
|
PolarFire SoC.
|
|
|
|
|
If built as a module, it will be called spi-microchip-core-qspi.
|
|
|
|
|
|
2015-08-07 07:19:50 +00:00
|
|
|
config SPI_MT65XX
|
|
|
|
|
tristate "MediaTek SPI controller"
|
|
|
|
|
depends on ARCH_MEDIATEK || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This selects the MediaTek(R) SPI bus driver.
|
|
|
|
|
If you want to use MediaTek(R) SPI interface,
|
|
|
|
|
say Y or M here.If you are not sure, say N.
|
|
|
|
|
SPI drivers for Mediatek MT65XX and MT81XX series ARM SoCs.
|
|
|
|
|
|
2019-03-25 08:29:25 +00:00
|
|
|
config SPI_MT7621
|
|
|
|
|
tristate "MediaTek MT7621 SPI Controller"
|
|
|
|
|
depends on RALINK || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This selects a driver for the MediaTek MT7621 SPI Controller.
|
|
|
|
|
|
2020-03-06 08:50:50 +00:00
|
|
|
config SPI_MTK_NOR
|
|
|
|
|
tristate "MediaTek SPI NOR controller"
|
|
|
|
|
depends on ARCH_MEDIATEK || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This enables support for SPI NOR controller found on MediaTek
|
2020-07-16 05:11:44 +00:00
|
|
|
ARM SoCs. This is a controller specifically for SPI NOR flash.
|
2020-03-06 08:50:50 +00:00
|
|
|
It can perform generic SPI transfers up to 6 bytes via generic
|
2020-07-16 05:11:44 +00:00
|
|
|
SPI interface as well as several SPI NOR specific instructions
|
2020-03-06 08:50:50 +00:00
|
|
|
via SPI MEM interface.
|
|
|
|
|
|
2022-04-24 03:25:24 +00:00
|
|
|
config SPI_MTK_SNFI
|
|
|
|
|
tristate "MediaTek SPI NAND Flash Interface"
|
|
|
|
|
depends on ARCH_MEDIATEK || COMPILE_TEST
|
|
|
|
|
depends on MTD_NAND_ECC_MEDIATEK
|
|
|
|
|
help
|
|
|
|
|
This enables support for SPI-NAND mode on the MediaTek NAND
|
|
|
|
|
Flash Interface found on MediaTek ARM SoCs. This controller
|
|
|
|
|
is implemented as a SPI-MEM controller with pipelined ECC
|
|
|
|
|
capcability.
|
|
|
|
|
|
2022-11-24 19:13:59 +00:00
|
|
|
config SPI_WPCM_FIU
|
|
|
|
|
tristate "Nuvoton WPCM450 Flash Interface Unit"
|
|
|
|
|
depends on ARCH_NPCM || COMPILE_TEST
|
|
|
|
|
select REGMAP
|
|
|
|
|
help
|
|
|
|
|
This enables support got the Flash Interface Unit SPI controller
|
|
|
|
|
present in the Nuvoton WPCM450 SoC.
|
|
|
|
|
|
|
|
|
|
This driver does not support generic SPI. The implementation only
|
|
|
|
|
supports the spi-mem interface.
|
|
|
|
|
|
2019-08-28 14:25:13 +00:00
|
|
|
config SPI_NPCM_FIU
|
|
|
|
|
tristate "Nuvoton NPCM FLASH Interface Unit"
|
|
|
|
|
depends on ARCH_NPCM || COMPILE_TEST
|
|
|
|
|
depends on OF && HAS_IOMEM
|
|
|
|
|
help
|
|
|
|
|
This enables support for the Flash Interface Unit SPI controller
|
|
|
|
|
in master mode.
|
|
|
|
|
This driver does not support generic SPI. The implementation only
|
|
|
|
|
supports spi-mem interface.
|
|
|
|
|
|
2018-11-12 16:42:32 +00:00
|
|
|
config SPI_NPCM_PSPI
|
|
|
|
|
tristate "Nuvoton NPCM PSPI Controller"
|
|
|
|
|
depends on ARCH_NPCM || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This driver provides support for Nuvoton NPCM BMC
|
|
|
|
|
Peripheral SPI controller in master mode.
|
|
|
|
|
|
2017-02-13 23:31:11 +00:00
|
|
|
config SPI_LANTIQ_SSC
|
|
|
|
|
tristate "Lantiq SSC SPI controller"
|
2020-07-17 06:27:57 +00:00
|
|
|
depends on LANTIQ || X86 || COMPILE_TEST
|
2017-02-13 23:31:11 +00:00
|
|
|
help
|
|
|
|
|
This driver supports the Lantiq SSC SPI controller in master
|
|
|
|
|
mode. This controller is found on Intel (former Lantiq) SoCs like
|
2020-07-17 06:27:57 +00:00
|
|
|
the Danube, Falcon, xRX200, xRX300, Lightning Mountain.
|
2017-02-13 23:31:11 +00:00
|
|
|
|
2011-02-14 02:20:39 +00:00
|
|
|
config SPI_OC_TINY
|
|
|
|
|
tristate "OpenCores tiny SPI"
|
2015-05-05 16:32:33 +00:00
|
|
|
depends on GPIOLIB || COMPILE_TEST
|
2011-02-14 02:20:39 +00:00
|
|
|
select SPI_BITBANG
|
|
|
|
|
help
|
|
|
|
|
This is the driver for OpenCores tiny SPI master controller.
|
|
|
|
|
|
2012-08-22 19:25:07 +00:00
|
|
|
config SPI_OCTEON
|
|
|
|
|
tristate "Cavium OCTEON SPI controller"
|
2013-05-22 15:10:46 +00:00
|
|
|
depends on CAVIUM_OCTEON_SOC
|
2012-08-22 19:25:07 +00:00
|
|
|
help
|
|
|
|
|
SPI host driver for the hardware found on some Cavium OCTEON
|
|
|
|
|
SOCs.
|
|
|
|
|
|
2007-02-12 08:52:37 +00:00
|
|
|
config SPI_OMAP_UWIRE
|
|
|
|
|
tristate "OMAP1 MicroWire"
|
2019-08-05 19:28:15 +00:00
|
|
|
depends on ARCH_OMAP1 || (ARM && COMPILE_TEST)
|
2007-02-12 08:52:37 +00:00
|
|
|
select SPI_BITBANG
|
|
|
|
|
help
|
|
|
|
|
This hooks up to the MicroWire controller on OMAP1 chips.
|
|
|
|
|
|
2007-07-17 11:04:13 +00:00
|
|
|
config SPI_OMAP24XX
|
2010-05-14 19:05:25 +00:00
|
|
|
tristate "McSPI driver for OMAP"
|
2018-11-07 10:39:26 +00:00
|
|
|
depends on ARCH_OMAP2PLUS || ARCH_K3 || COMPILE_TEST
|
2016-07-07 17:17:49 +00:00
|
|
|
select SG_SPLIT
|
2007-07-17 11:04:13 +00:00
|
|
|
help
|
2010-05-14 19:05:25 +00:00
|
|
|
SPI master controller for OMAP24XX and later Multichannel SPI
|
2007-07-17 11:04:13 +00:00
|
|
|
(McSPI) modules.
|
2007-02-12 08:52:39 +00:00
|
|
|
|
2013-08-20 13:25:48 +00:00
|
|
|
config SPI_TI_QSPI
|
|
|
|
|
tristate "DRA7xxx QSPI controller support"
|
|
|
|
|
depends on ARCH_OMAP2PLUS || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
QSPI master controller for DRA7xxx used for flash devices.
|
|
|
|
|
This device supports single, dual and quad read support, while
|
|
|
|
|
it only supports single write mode.
|
|
|
|
|
|
2008-08-05 20:01:09 +00:00
|
|
|
config SPI_ORION
|
2013-01-17 02:53:55 +00:00
|
|
|
tristate "Orion SPI master"
|
2016-04-22 13:17:28 +00:00
|
|
|
depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
|
2008-08-05 20:01:09 +00:00
|
|
|
help
|
2016-11-30 10:47:44 +00:00
|
|
|
This enables using the SPI master controller on the Orion
|
|
|
|
|
and MVEBU chips.
|
2008-08-05 20:01:09 +00:00
|
|
|
|
2022-10-06 05:05:13 +00:00
|
|
|
config SPI_PCI1XXXX
|
|
|
|
|
tristate "PCI1XXXX SPI Bus support"
|
|
|
|
|
depends on PCI
|
|
|
|
|
help
|
|
|
|
|
Say "yes" to Enable the SPI Bus support for the PCI1xxxx card
|
|
|
|
|
This is a PCI to SPI Bus driver
|
|
|
|
|
This driver can be built as module. If so, the module will be
|
|
|
|
|
called as spi-pci1xxxx.
|
|
|
|
|
|
2016-04-01 11:18:50 +00:00
|
|
|
config SPI_PIC32
|
|
|
|
|
tristate "Microchip PIC32 series SPI"
|
|
|
|
|
depends on MACH_PIC32 || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
SPI driver for Microchip PIC32 SPI master controller.
|
|
|
|
|
|
2016-04-15 11:27:19 +00:00
|
|
|
config SPI_PIC32_SQI
|
|
|
|
|
tristate "Microchip PIC32 Quad SPI driver"
|
|
|
|
|
depends on MACH_PIC32 || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
SPI driver for PIC32 Quad SPI controller.
|
|
|
|
|
|
2009-06-09 07:11:42 +00:00
|
|
|
config SPI_PL022
|
2011-05-19 12:13:19 +00:00
|
|
|
tristate "ARM AMBA PL022 SSP controller"
|
|
|
|
|
depends on ARM_AMBA
|
2009-09-22 23:46:01 +00:00
|
|
|
default y if ARCH_REALVIEW
|
|
|
|
|
default y if INTEGRATOR_IMPD1
|
|
|
|
|
default y if ARCH_VERSATILE
|
2009-06-09 07:11:42 +00:00
|
|
|
help
|
|
|
|
|
This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP
|
|
|
|
|
controller. If you have an embedded system with an AMBA(R)
|
|
|
|
|
bus and a PL022 controller, say Y or M here.
|
|
|
|
|
|
2009-09-22 23:45:58 +00:00
|
|
|
config SPI_PPC4xx
|
|
|
|
|
tristate "PPC4xx SPI Controller"
|
2012-02-23 09:37:55 +00:00
|
|
|
depends on PPC32 && 4xx
|
2009-09-22 23:45:58 +00:00
|
|
|
select SPI_BITBANG
|
|
|
|
|
help
|
|
|
|
|
This selects a driver for the PPC4xx SPI Controller.
|
|
|
|
|
|
2006-03-08 07:53:24 +00:00
|
|
|
config SPI_PXA2XX
|
|
|
|
|
tristate "PXA2xx SSP SPI master"
|
2020-02-10 09:30:27 +00:00
|
|
|
depends on ARCH_PXA || ARCH_MMP || PCI || ACPI || COMPILE_TEST
|
spi: fix building SPI_PXA on MMP
When the audio driver selects CONFIG_PXA_SSP on ARCH_MMP as a
loadable module, and the PXA SPI driver is built-in, we get
a link error in the SPI driver:
drivers/spi/spi-pxa2xx.o: In function `pxa2xx_spi_remove':
spi-pxa2xx.c:(.text+0x5f0): undefined reference to `pxa_ssp_free'
drivers/spi/spi-pxa2xx.o: In function `pxa2xx_spi_probe':
spi-pxa2xx.c:(.text+0xeac): undefined reference to `pxa_ssp_request'
spi-pxa2xx.c:(.text+0x1468): undefined reference to `pxa_ssp_free'
spi-pxa2xx.c:(.text+0x15bc): undefined reference to `pxa_ssp_free'
The problem is that the PXA SPI driver only uses 'select SSP'
specifically when building it for PXA, but we can also build it
for PCI, which is meant for Intel x86 SoCs that use the same SPI
block. When the sound driver forces the SSP to be a loadable
module, the IS_ENABLED() check in include/linux/pxa2xx_ssp.h
triggers but the spi driver can't reference the exported symbols.
I had a different approach before, making the PCI case depend
on X86, which fixed the problem by avoiding the MMP case.
This goes a different route, making the driver select PXA_SSP
also on MMP, which has an SSP that none of the boards in mainline
Linux use for SPI. There is no harm in always enabling the build
on MMP (PCI or not PCI), so I do that too, to document that this
hardware is actually available on MMP.
Link: https://patchwork.kernel.org/patch/8879921/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-08-07 15:42:55 +00:00
|
|
|
select PXA_SSP if ARCH_PXA || ARCH_MMP
|
2006-03-08 07:53:24 +00:00
|
|
|
help
|
2010-11-24 09:17:14 +00:00
|
|
|
This enables using a PXA2xx or Sodaville SSP port as a SPI master
|
|
|
|
|
controller. The driver can be configured to use any SSP port and
|
2019-07-31 20:08:50 +00:00
|
|
|
additional documentation can be found a Documentation/spi/pxa2xx.rst.
|
2010-11-24 09:17:14 +00:00
|
|
|
|
|
|
|
|
config SPI_PXA2XX_PCI
|
2014-07-24 17:10:54 +00:00
|
|
|
def_tristate SPI_PXA2XX && PCI && COMMON_CLK
|
2006-03-08 07:53:24 +00:00
|
|
|
|
2014-07-01 01:03:59 +00:00
|
|
|
config SPI_ROCKCHIP
|
|
|
|
|
tristate "Rockchip SPI controller driver"
|
2023-02-23 17:20:22 +00:00
|
|
|
depends on ARCH_ROCKCHIP || COMPILE_TEST
|
2014-07-01 01:03:59 +00:00
|
|
|
help
|
|
|
|
|
This selects a driver for Rockchip SPI controller.
|
|
|
|
|
|
|
|
|
|
If you say yes to this option, support will be included for
|
|
|
|
|
RK3066, RK3188 and RK3288 families of SPI controller.
|
|
|
|
|
Rockchip SPI controller support DMA transport and PIO mode.
|
|
|
|
|
The main usecase of this controller is to use spi flash as boot
|
|
|
|
|
device.
|
|
|
|
|
|
2021-08-12 13:45:42 +00:00
|
|
|
config SPI_ROCKCHIP_SFC
|
|
|
|
|
tristate "Rockchip Serial Flash Controller (SFC)"
|
|
|
|
|
depends on ARCH_ROCKCHIP || COMPILE_TEST
|
|
|
|
|
depends on HAS_IOMEM && HAS_DMA
|
|
|
|
|
help
|
|
|
|
|
This enables support for Rockchip serial flash controller. This
|
|
|
|
|
is a specialized controller used to access SPI flash on some
|
|
|
|
|
Rockchip SOCs.
|
|
|
|
|
|
|
|
|
|
ROCKCHIP SFC supports DMA and PIO modes. When DMA is not available,
|
|
|
|
|
the driver automatically falls back to PIO mode.
|
|
|
|
|
|
2015-04-15 15:43:52 +00:00
|
|
|
config SPI_RB4XX
|
|
|
|
|
tristate "Mikrotik RB4XX SPI master"
|
|
|
|
|
depends on SPI_MASTER && ATH79
|
|
|
|
|
help
|
|
|
|
|
SPI controller driver for the Mikrotik RB4xx series boards.
|
|
|
|
|
|
2020-06-13 19:18:34 +00:00
|
|
|
config SPI_RPCIF
|
|
|
|
|
tristate "Renesas RPC-IF SPI driver"
|
|
|
|
|
depends on RENESAS_RPCIF
|
|
|
|
|
help
|
2021-01-02 11:54:11 +00:00
|
|
|
SPI driver for Renesas R-Car Gen3 or RZ/G2 RPC-IF.
|
2020-06-13 19:18:34 +00:00
|
|
|
|
2012-03-07 05:46:25 +00:00
|
|
|
config SPI_RSPI
|
2014-01-21 15:10:09 +00:00
|
|
|
tristate "Renesas RSPI/QSPI controller"
|
2016-02-18 01:47:52 +00:00
|
|
|
depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
|
2012-03-07 05:46:25 +00:00
|
|
|
help
|
2014-01-21 15:10:09 +00:00
|
|
|
SPI driver for Renesas RSPI and QSPI blocks.
|
2012-03-07 05:46:25 +00:00
|
|
|
|
2023-06-22 11:33:39 +00:00
|
|
|
config SPI_RZV2M_CSI
|
2023-07-03 09:05:30 +00:00
|
|
|
tristate "Renesas RZ/V2M CSI controller"
|
2023-06-22 11:33:39 +00:00
|
|
|
depends on ARCH_RENESAS || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
SPI driver for Renesas RZ/V2M Clocked Serial Interface (CSI)
|
|
|
|
|
|
2018-10-02 21:47:08 +00:00
|
|
|
config SPI_QCOM_QSPI
|
|
|
|
|
tristate "QTI QSPI controller"
|
2023-02-23 17:20:26 +00:00
|
|
|
depends on ARCH_QCOM || COMPILE_TEST
|
2018-10-02 21:47:08 +00:00
|
|
|
help
|
|
|
|
|
QSPI(Quad SPI) driver for Qualcomm QSPI controller.
|
|
|
|
|
|
2014-02-13 16:21:38 +00:00
|
|
|
config SPI_QUP
|
|
|
|
|
tristate "Qualcomm SPI controller with QUP interface"
|
2020-09-04 16:37:10 +00:00
|
|
|
depends on ARCH_QCOM || COMPILE_TEST
|
2014-02-13 16:21:38 +00:00
|
|
|
help
|
|
|
|
|
Qualcomm Universal Peripheral (QUP) core is an AHB slave that
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provides a common data path (an output FIFO and an input FIFO)
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for serial peripheral interface (SPI) mini-core. SPI in master
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mode supports up to 50MHz, up to four chip selects, programmable
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data path from 4 bits to 32 bits and numerous protocol variants.
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This driver can also be built as a module. If so, the module
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will be called spi_qup.
|
2012-03-07 05:46:25 +00:00
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2018-10-03 13:44:25 +00:00
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|
config SPI_QCOM_GENI
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tristate "Qualcomm GENI based SPI controller"
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depends on QCOM_GENI_SE
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help
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This driver supports GENI serial engine based SPI controller in
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master mode on the Qualcomm Technologies Inc.'s SoCs. If you say
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yes to this option, support will be included for the built-in SPI
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interface on the Qualcomm Technologies Inc.'s SoCs.
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This driver can also be built as a module. If so, the module
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will be called spi-geni-qcom.
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2009-11-30 07:39:42 +00:00
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config SPI_S3C64XX
|
2021-09-24 13:31:14 +00:00
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tristate "Samsung S3C64XX/Exynos SoC series type SPI"
|
2020-08-06 18:20:35 +00:00
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depends on (PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST)
|
2009-11-30 07:39:42 +00:00
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help
|
2021-09-24 13:31:14 +00:00
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SPI driver for Samsung S3C64XX, S5Pv210 and Exynos SoCs.
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Choose Y/M here only if you build for such Samsung SoC.
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2009-11-30 07:39:42 +00:00
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2012-08-18 16:06:27 +00:00
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config SPI_SC18IS602
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tristate "NXP SC18IS602/602B/603 I2C to SPI bridge"
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depends on I2C
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help
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SPI driver for NXP SC18IS602/602B/603 I2C to SPI bridge.
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2009-11-26 11:10:05 +00:00
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config SPI_SH_MSIOF
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tristate "SuperH MSIOF SPI controller"
|
2018-04-17 17:49:18 +00:00
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depends on HAVE_CLK
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2016-08-31 09:37:05 +00:00
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depends on ARCH_SHMOBILE || ARCH_RENESAS || COMPILE_TEST
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2009-11-26 11:10:05 +00:00
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help
|
2012-11-07 11:40:05 +00:00
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SPI driver for SuperH and SH Mobile MSIOF blocks.
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2009-11-26 11:10:05 +00:00
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2011-02-15 01:30:32 +00:00
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config SPI_SH
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tristate "SuperH SPI controller"
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2013-07-05 18:42:58 +00:00
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depends on SUPERH || COMPILE_TEST
|
2011-02-15 01:30:32 +00:00
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help
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SPI driver for SuperH SPI blocks.
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2008-02-06 09:38:15 +00:00
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config SPI_SH_SCI
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tristate "SuperH SCI SPI controller"
|
2008-07-24 04:29:53 +00:00
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depends on SUPERH
|
2008-02-06 09:38:15 +00:00
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select SPI_BITBANG
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help
|
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SPI driver for SuperH SCI blocks.
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2012-03-02 01:10:17 +00:00
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config SPI_SH_HSPI
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tristate "SuperH HSPI controller"
|
2016-02-18 01:47:52 +00:00
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depends on ARCH_RENESAS || COMPILE_TEST
|
2012-03-02 01:10:17 +00:00
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|
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help
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SPI driver for SuperH HSPI blocks.
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|
2019-02-19 11:40:07 +00:00
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config SPI_SIFIVE
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tristate "SiFive SPI controller"
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depends on HAS_IOMEM
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help
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This exposes the SPI controller IP from SiFive.
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2018-09-28 10:53:04 +00:00
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config SPI_SLAVE_MT27XX
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tristate "MediaTek SPI slave device"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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depends on SPI_SLAVE
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help
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This selects the MediaTek(R) SPI slave device driver.
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If you want to use MediaTek(R) SPI slave interface,
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say Y or M here.If you are not sure, say N.
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SPI slave drivers for Mediatek MT27XX series ARM SoCs.
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2022-11-24 00:33:51 +00:00
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config SPI_SN_F_OSPI
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tristate "Socionext F_OSPI SPI flash controller"
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depends on OF && HAS_IOMEM
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depends on SPI_MEM
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help
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This enables support for the Socionext F_OSPI controller
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for connecting an SPI Flash memory over up to 8-bit wide bus.
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It supports indirect access mode only.
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2018-08-16 12:54:51 +00:00
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config SPI_SPRD
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tristate "Spreadtrum SPI controller"
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depends on ARCH_SPRD || COMPILE_TEST
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help
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SPI driver for Spreadtrum SoCs.
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|
2017-09-15 07:29:16 +00:00
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config SPI_SPRD_ADI
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tristate "Spreadtrum ADI controller"
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depends on ARCH_SPRD || COMPILE_TEST
|
2017-10-05 20:39:37 +00:00
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depends on HWSPINLOCK || (COMPILE_TEST && !HWSPINLOCK)
|
2017-09-15 07:29:16 +00:00
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help
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ADI driver based on SPI for Spreadtrum SoCs.
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2017-06-21 14:32:06 +00:00
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config SPI_STM32
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tristate "STMicroelectronics STM32 SPI controller"
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depends on ARCH_STM32 || COMPILE_TEST
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2023-06-15 07:58:15 +00:00
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select SPI_SLAVE
|
2017-06-21 14:32:06 +00:00
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help
|
2018-12-24 22:00:30 +00:00
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SPI driver for STMicroelectronics STM32 SoCs.
|
2017-06-21 14:32:06 +00:00
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STM32 SPI controller supports DMA and PIO modes. When DMA
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is not available, the driver automatically falls back to
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PIO mode.
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|
2018-10-05 07:43:03 +00:00
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config SPI_STM32_QSPI
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tristate "STMicroelectronics STM32 QUAD SPI controller"
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depends on ARCH_STM32 || COMPILE_TEST
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depends on OF
|
2021-06-04 07:50:09 +00:00
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depends on SPI_MEM
|
2018-10-05 07:43:03 +00:00
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help
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This enables support for the Quad SPI controller in master mode.
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This driver does not support generic SPI. The implementation only
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supports spi-mem interface.
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2014-12-09 20:21:30 +00:00
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config SPI_ST_SSC4
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tristate "STMicroelectronics SPI SSC-based driver"
|
2016-04-29 05:38:41 +00:00
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depends on ARCH_STI || COMPILE_TEST
|
2014-12-09 20:21:30 +00:00
|
|
|
help
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|
STMicroelectronics SoCs support for SPI. If you say yes to
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this option, support will be included for the SSC driven SPI.
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|
spi: sunxi: Add Allwinner A10 SPI controller driver
The older Allwinner SoCs (A10, A13, A10s and A20) all have the same SPI
controller.
Unfortunately, this SPI controller, even though quite similar, is significantly
different from the recently supported A31 SPI controller (different registers
offset, split/merged registers, etc.). Supporting both controllers in a single
driver would be unreasonable, hence the addition of a new driver.
Like its more recent counterpart, it supports DMA, but the driver only does PIO
until we have a dmaengine driver for this platform.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-02-22 21:35:53 +00:00
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|
config SPI_SUN4I
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|
|
tristate "Allwinner A10 SoCs SPI controller"
|
|
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|
|
depends on ARCH_SUNXI || COMPILE_TEST
|
|
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|
help
|
|
|
|
|
SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
|
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|
2014-02-05 13:05:05 +00:00
|
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|
config SPI_SUN6I
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|
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tristate "Allwinner A31 SPI controller"
|
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|
depends on ARCH_SUNXI || COMPILE_TEST
|
2014-02-06 10:53:51 +00:00
|
|
|
depends on RESET_CONTROLLER
|
2014-02-05 13:05:05 +00:00
|
|
|
help
|
|
|
|
|
This enables using the SPI controller on the Allwinner A31 SoCs.
|
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|
|
2022-01-18 08:42:38 +00:00
|
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|
config SPI_SUNPLUS_SP7021
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|
|
tristate "Sunplus SP7021 SPI controller"
|
|
|
|
|
depends on SOC_SP7021 || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
This enables Sunplus SP7021 SPI controller driver on the SP7021 SoCs.
|
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|
|
This driver can also be built as a module. If so, the module will be
|
|
|
|
|
called as spi-sunplus-sp7021.
|
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|
|
|
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|
|
If you have a Sunplus SP7021 platform say Y here.
|
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|
|
If unsure, say N.
|
|
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|
|
|
2019-06-04 05:12:57 +00:00
|
|
|
config SPI_SYNQUACER
|
|
|
|
|
tristate "Socionext's SynQuacer HighSpeed SPI controller"
|
|
|
|
|
depends on ARCH_SYNQUACER || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
SPI driver for Socionext's High speed SPI controller which provides
|
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|
|
|
various operating modes for interfacing to serial peripheral devices
|
|
|
|
|
that use the de-facto standard SPI protocol.
|
|
|
|
|
|
|
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|
|
It also supports the new dual-bit and quad-bit SPI protocol.
|
|
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|
|
|
2018-10-17 02:08:11 +00:00
|
|
|
config SPI_MXIC
|
2019-11-20 13:39:16 +00:00
|
|
|
tristate "Macronix MX25F0A SPI controller"
|
|
|
|
|
depends on SPI_MASTER
|
2022-02-02 14:45:36 +00:00
|
|
|
imply MTD_NAND_ECC_MXIC
|
2019-11-20 13:39:16 +00:00
|
|
|
help
|
|
|
|
|
This selects the Macronix MX25F0A SPI controller driver.
|
2018-10-17 02:08:11 +00:00
|
|
|
|
2012-08-03 15:26:11 +00:00
|
|
|
config SPI_MXS
|
|
|
|
|
tristate "Freescale MXS SPI controller"
|
|
|
|
|
depends on ARCH_MXS
|
|
|
|
|
select STMP_DEVICE
|
|
|
|
|
help
|
|
|
|
|
SPI driver for Freescale MXS devices.
|
|
|
|
|
|
2020-12-21 21:17:34 +00:00
|
|
|
config SPI_TEGRA210_QUAD
|
|
|
|
|
tristate "NVIDIA Tegra QSPI Controller"
|
|
|
|
|
depends on ARCH_TEGRA || COMPILE_TEST
|
|
|
|
|
depends on RESET_CONTROLLER
|
|
|
|
|
help
|
|
|
|
|
QSPI driver for NVIDIA Tegra QSPI Controller interface. This
|
|
|
|
|
controller is different from the SPI controller and is available
|
|
|
|
|
on Tegra SoCs starting from Tegra210.
|
|
|
|
|
|
2013-02-22 12:37:39 +00:00
|
|
|
config SPI_TEGRA114
|
|
|
|
|
tristate "NVIDIA Tegra114 SPI Controller"
|
2013-07-05 18:42:58 +00:00
|
|
|
depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
|
2018-04-17 17:49:18 +00:00
|
|
|
depends on RESET_CONTROLLER
|
2013-02-22 12:37:39 +00:00
|
|
|
help
|
|
|
|
|
SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller
|
|
|
|
|
is different than the older SoCs SPI controller and also register interface
|
|
|
|
|
get changed with this controller.
|
|
|
|
|
|
2012-11-14 00:24:47 +00:00
|
|
|
config SPI_TEGRA20_SFLASH
|
|
|
|
|
tristate "Nvidia Tegra20 Serial flash Controller"
|
2013-07-05 18:42:58 +00:00
|
|
|
depends on ARCH_TEGRA || COMPILE_TEST
|
2013-11-06 23:31:24 +00:00
|
|
|
depends on RESET_CONTROLLER
|
2012-11-14 00:24:47 +00:00
|
|
|
help
|
|
|
|
|
SPI driver for Nvidia Tegra20 Serial flash Controller interface.
|
|
|
|
|
The main usecase of this controller is to use spi flash as boot
|
|
|
|
|
device.
|
|
|
|
|
|
2012-10-30 07:04:05 +00:00
|
|
|
config SPI_TEGRA20_SLINK
|
|
|
|
|
tristate "Nvidia Tegra20/Tegra30 SLINK Controller"
|
2013-07-05 18:42:58 +00:00
|
|
|
depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
|
2018-04-17 17:49:18 +00:00
|
|
|
depends on RESET_CONTROLLER
|
2012-10-30 07:04:05 +00:00
|
|
|
help
|
|
|
|
|
SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
|
|
|
|
|
|
2016-08-19 14:03:20 +00:00
|
|
|
config SPI_THUNDERX
|
|
|
|
|
tristate "Cavium ThunderX SPI controller"
|
|
|
|
|
depends on PCI && 64BIT && (ARM64 || COMPILE_TEST)
|
|
|
|
|
help
|
|
|
|
|
SPI host driver for the hardware found on Cavium ThunderX
|
|
|
|
|
SOCs.
|
|
|
|
|
|
2010-10-08 18:44:49 +00:00
|
|
|
config SPI_TOPCLIFF_PCH
|
2011-10-28 00:35:21 +00:00
|
|
|
tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) SPI"
|
2015-11-30 16:21:42 +00:00
|
|
|
depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
|
2010-10-08 18:44:49 +00:00
|
|
|
help
|
2010-10-08 18:56:13 +00:00
|
|
|
SPI driver for the Topcliff PCH (Platform Controller Hub) SPI bus
|
|
|
|
|
used in some x86 embedded processors.
|
2010-10-08 18:44:49 +00:00
|
|
|
|
2011-10-28 00:35:21 +00:00
|
|
|
This driver also supports the ML7213/ML7223/ML7831, a companion chip
|
|
|
|
|
for the Atom E6xx series and compatible with the Intel EG20T PCH.
|
2011-06-07 05:50:10 +00:00
|
|
|
|
2018-08-01 07:29:12 +00:00
|
|
|
config SPI_UNIPHIER
|
|
|
|
|
tristate "Socionext UniPhier SPI Controller"
|
|
|
|
|
depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
|
2020-05-11 08:25:29 +00:00
|
|
|
depends on HAS_IOMEM
|
2018-08-01 07:29:12 +00:00
|
|
|
help
|
|
|
|
|
This enables a driver for the Socionext UniPhier SoC SCSSI SPI controller.
|
|
|
|
|
|
|
|
|
|
UniPhier SoCs have SCSSI and MCSSI SPI controllers.
|
|
|
|
|
Every UniPhier SoC has SCSSI which supports single channel.
|
|
|
|
|
Older UniPhier Pro4/Pro5 also has MCSSI which support multiple channels.
|
|
|
|
|
This driver supports SCSSI only.
|
|
|
|
|
|
|
|
|
|
If your SoC supports SCSSI, say Y here.
|
|
|
|
|
|
2012-07-19 16:44:07 +00:00
|
|
|
config SPI_XCOMM
|
|
|
|
|
tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver"
|
|
|
|
|
depends on I2C
|
|
|
|
|
help
|
|
|
|
|
Support for the SPI-I2C bridge found on the Analog Devices
|
|
|
|
|
AD-FMCOMMS1-EBZ board.
|
|
|
|
|
|
2007-07-17 11:04:11 +00:00
|
|
|
config SPI_XILINX
|
2009-11-13 11:28:55 +00:00
|
|
|
tristate "Xilinx SPI controller common module"
|
2013-01-17 02:53:55 +00:00
|
|
|
depends on HAS_IOMEM
|
2007-07-17 11:04:11 +00:00
|
|
|
select SPI_BITBANG
|
|
|
|
|
help
|
|
|
|
|
This exposes the SPI controller IP from the Xilinx EDK.
|
|
|
|
|
|
|
|
|
|
See the "OPB Serial Peripheral Interface (SPI) (v1.00e)"
|
|
|
|
|
Product Specification document (DS464) for hardware details.
|
|
|
|
|
|
2009-11-13 11:28:55 +00:00
|
|
|
Or for the DS570, see "XPS Serial Peripheral Interface (SPI) (v2.00b)"
|
|
|
|
|
|
2015-08-27 12:19:28 +00:00
|
|
|
config SPI_XLP
|
2021-11-09 16:13:25 +00:00
|
|
|
tristate "Cavium ThunderX2 SPI controller driver"
|
|
|
|
|
depends on ARCH_THUNDER2 || COMPILE_TEST
|
2015-08-27 12:19:28 +00:00
|
|
|
help
|
2021-11-09 16:13:25 +00:00
|
|
|
Enable support for the SPI controller on the Cavium ThunderX2.
|
|
|
|
|
(Originally on Netlogic XLP SoCs.)
|
2015-08-27 12:19:28 +00:00
|
|
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2021-11-09 16:13:25 +00:00
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If you have a Cavium ThunderX2 platform say Y here.
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2015-08-27 12:19:28 +00:00
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If unsure, say N.
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2014-03-12 17:55:24 +00:00
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config SPI_XTENSA_XTFPGA
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tristate "Xtensa SPI controller for xtfpga"
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2014-03-20 10:08:04 +00:00
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depends on (XTENSA && XTENSA_PLATFORM_XTFPGA) || COMPILE_TEST
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2014-03-12 17:55:24 +00:00
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select SPI_BITBANG
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help
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SPI driver for xtfpga SPI master controller.
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This simple SPI master controller is built into xtfpga bitstreams
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and is used to control daughterboard audio codec. It always transfers
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16 bit words in SPI mode 0, automatically asserting CS on transfer
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start and deasserting on end.
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2019-04-01 07:59:13 +00:00
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config SPI_ZYNQ_QSPI
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tristate "Xilinx Zynq QSPI controller"
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depends on ARCH_ZYNQ || COMPILE_TEST
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help
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This enables support for the Zynq Quad SPI controller
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in master mode.
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This controller only supports SPI memory interface.
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2015-06-10 10:38:21 +00:00
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config SPI_ZYNQMP_GQSPI
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tristate "Xilinx ZynqMP GQSPI controller"
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2019-04-01 07:59:13 +00:00
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depends on (SPI_MASTER && HAS_DMA) || COMPILE_TEST
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2015-06-10 10:38:21 +00:00
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help
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Enables Xilinx GQSPI controller driver for Zynq UltraScale+ MPSoC.
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2020-04-25 19:59:48 +00:00
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config SPI_AMD
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tristate "AMD SPI controller"
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depends on SPI_MASTER || COMPILE_TEST
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help
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Enables SPI controller driver for AMD SoC.
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
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#
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# Add new SPI master controllers in alphabetical order above this line
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#
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2020-02-04 03:28:38 +00:00
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comment "SPI Multiplexer support"
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config SPI_MUX
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tristate "SPI multiplexer support"
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select MULTIPLEXER
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help
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This adds support for SPI multiplexers. Each SPI mux will be
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accessible as a SPI controller, the devices behind the mux will appear
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to be chip selects on this controller. It is still necessary to
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select one or more specific mux-controller drivers.
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
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#
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# There are lots of SPI device types, with sensors and memory
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# being probably the most widely used ones.
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#
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comment "SPI Protocol Masters"
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2007-05-08 07:32:15 +00:00
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config SPI_SPIDEV
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tristate "User mode SPI device driver support"
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help
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This supports user mode SPI protocol drivers.
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2015-11-27 16:17:21 +00:00
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config SPI_LOOPBACK_TEST
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tristate "spi loopback test framework support"
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depends on m
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help
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This enables the SPI loopback testing framework driver
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primarily used for development of spi_master drivers
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and to detect regressions
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2007-07-17 11:04:10 +00:00
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config SPI_TLE62X0
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tristate "Infineon TLE62X0 (for power switching)"
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2008-07-24 04:29:53 +00:00
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depends on SYSFS
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2007-07-17 11:04:10 +00:00
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help
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SPI driver for Infineon TLE62X0 series line driver chips,
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such as the TLE6220, TLE6230 and TLE6240. This provides a
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sysfs interface, with each line presented as a kind of GPIO
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exposing both switch control and diagnostic feedback.
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[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
|
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#
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# Add new SPI protocol masters in alphabetical order above this line
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#
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2008-07-24 04:29:53 +00:00
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endif # SPI_MASTER
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2017-05-22 13:11:41 +00:00
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#
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# SLAVE side ... listening to other SPI masters
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#
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config SPI_SLAVE
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bool "SPI slave protocol handlers"
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help
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|
|
If your system has a slave-capable SPI controller, you can enable
|
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slave protocol handlers.
|
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if SPI_SLAVE
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2017-05-22 13:11:44 +00:00
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config SPI_SLAVE_TIME
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tristate "SPI slave handler reporting boot up time"
|
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help
|
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|
|
SPI slave handler responding with the time of reception of the last
|
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SPI message.
|
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2017-05-22 13:11:45 +00:00
|
|
|
config SPI_SLAVE_SYSTEM_CONTROL
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tristate "SPI slave handler controlling system state"
|
|
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|
|
help
|
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|
|
SPI slave handler to allow remote control of system reboot, power
|
|
|
|
|
off, halt, and suspend.
|
|
|
|
|
|
2017-05-22 13:11:41 +00:00
|
|
|
endif # SPI_SLAVE
|
[PATCH] spi: simple SPI framework
This is the core of a small SPI framework, implementing the model of a
queue of messages which complete asynchronously (with thin synchronous
wrappers on top).
- It's still less than 2KB of ".text" (ARM). If there's got to be a
mid-layer for something so simple, that's the right size budget. :)
- The guts use board-specific SPI device tables to build the driver
model tree. (Hardware probing is rarely an option.)
- This version of Kconfig includes no drivers. At this writing there
are two known master controller drivers (PXA/SSP, OMAP MicroWire)
and three protocol drivers (CS8415a, ADS7846, DataFlash) with LKML
mentions of other drivers in development.
- No userspace API. There are several implementations to compare.
Implement them like any other driver, and bind them with sysfs.
The changes from last version posted to LKML (on 11-Nov-2005) are minor,
and include:
- One bugfix (removes a FIXME), with the visible effect of making device
names be "spiB.C" where B is the bus number and C is the chipselect.
- The "caller provides DMA mappings" mechanism now has kerneldoc, for
DMA drivers that want to be fancy.
- Hey, the framework init can be subsys_init. Even though board init
logic fires earlier, at arch_init ... since the framework init is
for driver support, and the board init support uses static init.
- Various additional spec/doc clarifications based on discussions
with other folk. It adds a brief "thank you" at the end, for folk
who've helped nudge this framework into existence.
As I've said before, I think that "protocol tweaking" is the main support
that this driver framework will need to evolve.
From: Mark Underwood <basicmark@yahoo.com>
Update the SPI framework to remove a potential priority inversion case by
reverting to kmalloc if the pre-allocated DMA-safe buffer isn't available.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-01-08 21:34:19 +00:00
|
|
|
|
2020-08-03 11:09:01 +00:00
|
|
|
config SPI_DYNAMIC
|
|
|
|
|
def_bool ACPI || OF_DYNAMIC || SPI_SLAVE
|
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|
2008-04-28 09:14:16 +00:00
|
|
|
endif # SPI
|
