2016-07-21 11:06:38 +00:00
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/*
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* Copyright (c) 2016 Hisilicon Limited.
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* Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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2016-08-23 20:44:50 +00:00
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#include <linux/acpi.h>
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2016-07-21 11:06:38 +00:00
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#include <linux/of_platform.h>
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2017-02-17 14:38:26 +00:00
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#include <linux/module.h>
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2016-07-21 11:06:38 +00:00
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#include <rdma/ib_addr.h>
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#include <rdma/ib_smi.h>
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#include <rdma/ib_user_verbs.h>
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2016-11-23 19:41:08 +00:00
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#include <rdma/ib_cache.h>
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2016-07-21 11:06:38 +00:00
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#include "hns_roce_common.h"
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#include "hns_roce_device.h"
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2016-10-19 17:13:07 +00:00
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#include <rdma/hns-abi.h>
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2016-07-21 11:06:38 +00:00
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#include "hns_roce_hem.h"
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/**
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* hns_get_gid_index - Get gid index.
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* @hr_dev: pointer to structure hns_roce_dev.
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* @port: port, value range: 0 ~ MAX
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* @gid_index: gid_index, value range: 0 ~ MAX
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* Description:
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* N ports shared gids, allocation method as follow:
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* GID[0][0], GID[1][0],.....GID[N - 1][0],
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* GID[0][0], GID[1][0],.....GID[N - 1][0],
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* And so on
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*/
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int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
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{
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return gid_index * hr_dev->caps.num_ports + port;
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}
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2017-08-30 09:22:59 +00:00
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EXPORT_SYMBOL_GPL(hns_get_gid_index);
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2016-07-21 11:06:38 +00:00
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2017-09-29 15:10:09 +00:00
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static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
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2016-07-21 11:06:38 +00:00
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{
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u8 phy_port;
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u32 i = 0;
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if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
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2017-09-29 15:10:09 +00:00
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return 0;
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2016-07-21 11:06:38 +00:00
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for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
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hr_dev->dev_addr[port][i] = addr[i];
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phy_port = hr_dev->iboe.phy_port[port];
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2017-09-29 15:10:09 +00:00
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return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
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2016-07-21 11:06:38 +00:00
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}
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2016-11-23 19:41:08 +00:00
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static int hns_roce_add_gid(struct ib_device *device, u8 port_num,
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unsigned int index, const union ib_gid *gid,
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const struct ib_gid_attr *attr, void **context)
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2016-07-21 11:06:38 +00:00
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{
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2016-11-23 19:41:08 +00:00
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struct hns_roce_dev *hr_dev = to_hr_dev(device);
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u8 port = port_num - 1;
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unsigned long flags;
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if (port >= hr_dev->caps.num_ports)
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return -EINVAL;
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2016-07-21 11:06:38 +00:00
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2016-11-23 19:41:08 +00:00
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spin_lock_irqsave(&hr_dev->iboe.lock, flags);
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hr_dev->hw->set_gid(hr_dev, port, index, (union ib_gid *)gid);
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spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
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return 0;
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}
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static int hns_roce_del_gid(struct ib_device *device, u8 port_num,
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unsigned int index, void **context)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(device);
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union ib_gid zgid = { {0} };
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u8 port = port_num - 1;
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unsigned long flags;
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if (port >= hr_dev->caps.num_ports)
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return -EINVAL;
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spin_lock_irqsave(&hr_dev->iboe.lock, flags);
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hr_dev->hw->set_gid(hr_dev, port, index, &zgid);
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spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
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return 0;
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2016-07-21 11:06:38 +00:00
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}
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static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
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unsigned long event)
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{
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2017-08-30 09:23:02 +00:00
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struct device *dev = hr_dev->dev;
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2016-07-21 11:06:38 +00:00
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struct net_device *netdev;
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2017-09-29 15:10:09 +00:00
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int ret = 0;
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2016-07-21 11:06:38 +00:00
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netdev = hr_dev->iboe.netdevs[port];
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if (!netdev) {
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dev_err(dev, "port(%d) can't find netdev\n", port);
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return -ENODEV;
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}
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switch (event) {
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case NETDEV_UP:
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case NETDEV_CHANGE:
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case NETDEV_REGISTER:
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case NETDEV_CHANGEADDR:
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2017-09-29 15:10:09 +00:00
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ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
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2016-07-21 11:06:38 +00:00
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break;
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case NETDEV_DOWN:
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/*
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2016-11-23 19:41:09 +00:00
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* In v1 engine, only support all ports closed together.
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*/
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2016-07-21 11:06:38 +00:00
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break;
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default:
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dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
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break;
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}
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2017-09-29 15:10:09 +00:00
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return ret;
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2016-07-21 11:06:38 +00:00
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}
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static int hns_roce_netdev_event(struct notifier_block *self,
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unsigned long event, void *ptr)
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{
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struct net_device *dev = netdev_notifier_info_to_dev(ptr);
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struct hns_roce_ib_iboe *iboe = NULL;
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struct hns_roce_dev *hr_dev = NULL;
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u8 port = 0;
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int ret = 0;
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hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
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iboe = &hr_dev->iboe;
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for (port = 0; port < hr_dev->caps.num_ports; port++) {
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if (dev == iboe->netdevs[port]) {
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ret = handle_en_event(hr_dev, port, event);
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if (ret)
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return NOTIFY_DONE;
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break;
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}
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}
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return NOTIFY_DONE;
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}
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2016-11-23 19:41:08 +00:00
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static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
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2016-07-21 11:06:38 +00:00
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{
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2017-09-29 15:10:09 +00:00
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int ret;
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2016-11-23 19:41:08 +00:00
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u8 i;
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2016-07-21 11:06:38 +00:00
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for (i = 0; i < hr_dev->caps.num_ports; i++) {
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2017-08-30 09:22:59 +00:00
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if (hr_dev->hw->set_mtu)
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hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
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hr_dev->caps.max_mtu);
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2017-09-29 15:10:09 +00:00
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ret = hns_roce_set_mac(hr_dev, i,
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hr_dev->iboe.netdevs[i]->dev_addr);
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if (ret)
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return ret;
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2016-07-21 11:06:38 +00:00
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}
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2016-11-23 19:41:08 +00:00
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return 0;
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2016-07-21 11:06:38 +00:00
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}
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static int hns_roce_query_device(struct ib_device *ib_dev,
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struct ib_device_attr *props,
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struct ib_udata *uhw)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
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memset(props, 0, sizeof(*props));
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props->sys_image_guid = hr_dev->sys_image_guid;
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props->max_mr_size = (u64)(~(0ULL));
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props->page_size_cap = hr_dev->caps.page_size_cap;
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props->vendor_id = hr_dev->vendor_id;
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props->vendor_part_id = hr_dev->vendor_part_id;
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props->hw_ver = hr_dev->hw_rev;
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props->max_qp = hr_dev->caps.num_qps;
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props->max_qp_wr = hr_dev->caps.max_wqes;
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props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
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2016-09-15 22:48:08 +00:00
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IB_DEVICE_RC_RNR_NAK_GEN;
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2017-08-30 09:23:04 +00:00
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props->max_sge = max(hr_dev->caps.max_sq_sg, hr_dev->caps.max_rq_sg);
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2016-07-21 11:06:38 +00:00
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props->max_sge_rd = 1;
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props->max_cq = hr_dev->caps.num_cqs;
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props->max_cqe = hr_dev->caps.max_cqes;
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props->max_mr = hr_dev->caps.num_mtpts;
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props->max_pd = hr_dev->caps.num_pds;
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props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
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props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
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props->atomic_cap = IB_ATOMIC_NONE;
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props->max_pkeys = 1;
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props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
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return 0;
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}
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2016-09-15 22:48:06 +00:00
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static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
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u8 port_num)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
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struct net_device *ndev;
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if (port_num < 1 || port_num > hr_dev->caps.num_ports)
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return NULL;
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rcu_read_lock();
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ndev = hr_dev->iboe.netdevs[port_num - 1];
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if (ndev)
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dev_hold(ndev);
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rcu_read_unlock();
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return ndev;
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}
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2016-07-21 11:06:38 +00:00
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static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
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struct ib_port_attr *props)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
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2017-08-30 09:23:02 +00:00
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struct device *dev = hr_dev->dev;
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2016-07-21 11:06:38 +00:00
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struct net_device *net_dev;
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unsigned long flags;
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enum ib_mtu mtu;
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u8 port;
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assert(port_num > 0);
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port = port_num - 1;
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2017-01-24 11:02:39 +00:00
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/* props being zeroed by the caller, avoid zeroing it here */
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2016-07-21 11:06:38 +00:00
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props->max_mtu = hr_dev->caps.max_mtu;
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props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
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props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
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IB_PORT_VENDOR_CLASS_SUP |
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IB_PORT_BOOT_MGMT_SUP;
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props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
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props->pkey_tbl_len = 1;
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props->active_width = IB_WIDTH_4X;
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props->active_speed = 1;
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spin_lock_irqsave(&hr_dev->iboe.lock, flags);
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net_dev = hr_dev->iboe.netdevs[port];
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if (!net_dev) {
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spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
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dev_err(dev, "find netdev %d failed!\r\n", port);
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return -EINVAL;
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}
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mtu = iboe_get_mtu(net_dev->mtu);
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props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
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props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
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IB_PORT_ACTIVE : IB_PORT_DOWN;
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props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
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spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
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return 0;
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}
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static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
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u8 port_num)
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{
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return IB_LINK_LAYER_ETHERNET;
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}
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static int hns_roce_query_gid(struct ib_device *ib_dev, u8 port_num, int index,
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union ib_gid *gid)
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{
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return 0;
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}
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static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
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u16 *pkey)
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{
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*pkey = PKEY_ID;
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return 0;
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}
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static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
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struct ib_device_modify *props)
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{
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unsigned long flags;
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if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
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return -EOPNOTSUPP;
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if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
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|
|
spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
|
|
|
|
memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
|
|
|
|
spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
|
|
|
|
struct ib_port_modify *props)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
|
|
|
|
struct ib_udata *udata)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
struct hns_roce_ucontext *context;
|
|
|
|
struct hns_roce_ib_alloc_ucontext_resp resp;
|
|
|
|
struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
|
|
|
|
|
|
|
|
resp.qp_tab_size = hr_dev->caps.num_qps;
|
|
|
|
|
|
|
|
context = kmalloc(sizeof(*context), GFP_KERNEL);
|
|
|
|
if (!context)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
ret = hns_roce_uar_alloc(hr_dev, &context->uar);
|
|
|
|
if (ret)
|
|
|
|
goto error_fail_uar_alloc;
|
|
|
|
|
|
|
|
ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
|
|
|
|
if (ret)
|
|
|
|
goto error_fail_copy_to_udata;
|
|
|
|
|
|
|
|
return &context->ibucontext;
|
|
|
|
|
|
|
|
error_fail_copy_to_udata:
|
|
|
|
hns_roce_uar_free(hr_dev, &context->uar);
|
|
|
|
|
|
|
|
error_fail_uar_alloc:
|
|
|
|
kfree(context);
|
|
|
|
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
|
|
|
|
{
|
|
|
|
struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
|
|
|
|
|
|
|
|
hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
|
|
|
|
kfree(context);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hns_roce_mmap(struct ib_ucontext *context,
|
|
|
|
struct vm_area_struct *vma)
|
|
|
|
{
|
2016-11-23 19:41:00 +00:00
|
|
|
struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
|
|
|
|
|
2016-07-21 11:06:38 +00:00
|
|
|
if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (vma->vm_pgoff == 0) {
|
|
|
|
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
|
|
|
if (io_remap_pfn_range(vma, vma->vm_start,
|
|
|
|
to_hr_ucontext(context)->uar.pfn,
|
|
|
|
PAGE_SIZE, vma->vm_page_prot))
|
|
|
|
return -EAGAIN;
|
2017-08-30 09:23:17 +00:00
|
|
|
} else if (vma->vm_pgoff == 1 && hr_dev->tptr_dma_addr &&
|
|
|
|
hr_dev->tptr_size) {
|
2016-11-23 19:41:00 +00:00
|
|
|
/* vm_pgoff: 1 -- TPTR */
|
|
|
|
if (io_remap_pfn_range(vma, vma->vm_start,
|
|
|
|
hr_dev->tptr_dma_addr >> PAGE_SHIFT,
|
|
|
|
hr_dev->tptr_size,
|
|
|
|
vma->vm_page_prot))
|
|
|
|
return -EAGAIN;
|
|
|
|
} else
|
2016-07-21 11:06:38 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
|
|
|
|
struct ib_port_immutable *immutable)
|
|
|
|
{
|
|
|
|
struct ib_port_attr attr;
|
|
|
|
int ret;
|
|
|
|
|
2017-01-24 11:02:39 +00:00
|
|
|
immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
|
|
|
|
|
|
|
|
ret = ib_query_port(ib_dev, port_num, &attr);
|
2016-07-21 11:06:38 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
immutable->pkey_tbl_len = attr.pkey_tbl_len;
|
|
|
|
immutable->gid_tbl_len = attr.gid_tbl_len;
|
|
|
|
|
|
|
|
immutable->max_mad_size = IB_MGMT_MAD_SIZE;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
|
|
|
|
{
|
|
|
|
struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
|
|
|
|
|
|
|
|
unregister_netdevice_notifier(&iboe->nb);
|
|
|
|
ib_unregister_device(&hr_dev->ib_dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
struct hns_roce_ib_iboe *iboe = NULL;
|
|
|
|
struct ib_device *ib_dev = NULL;
|
2017-08-30 09:23:02 +00:00
|
|
|
struct device *dev = hr_dev->dev;
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
iboe = &hr_dev->iboe;
|
2016-09-20 16:07:02 +00:00
|
|
|
spin_lock_init(&iboe->lock);
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
ib_dev = &hr_dev->ib_dev;
|
2016-11-29 23:10:30 +00:00
|
|
|
strlcpy(ib_dev->name, "hns_%d", IB_DEVICE_NAME_MAX);
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
ib_dev->owner = THIS_MODULE;
|
|
|
|
ib_dev->node_type = RDMA_NODE_IB_CA;
|
2017-01-20 21:04:18 +00:00
|
|
|
ib_dev->dev.parent = dev;
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
|
|
|
|
ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
|
|
|
|
ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
|
|
|
|
ib_dev->uverbs_abi_ver = 1;
|
|
|
|
ib_dev->uverbs_cmd_mask =
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_REG_MR) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
|
|
|
|
(1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
|
|
|
|
|
|
|
|
/* HCA||device||port */
|
|
|
|
ib_dev->modify_device = hns_roce_modify_device;
|
|
|
|
ib_dev->query_device = hns_roce_query_device;
|
|
|
|
ib_dev->query_port = hns_roce_query_port;
|
|
|
|
ib_dev->modify_port = hns_roce_modify_port;
|
|
|
|
ib_dev->get_link_layer = hns_roce_get_link_layer;
|
2016-09-15 22:48:06 +00:00
|
|
|
ib_dev->get_netdev = hns_roce_get_netdev;
|
2016-07-21 11:06:38 +00:00
|
|
|
ib_dev->query_gid = hns_roce_query_gid;
|
2016-11-23 19:41:08 +00:00
|
|
|
ib_dev->add_gid = hns_roce_add_gid;
|
|
|
|
ib_dev->del_gid = hns_roce_del_gid;
|
2016-07-21 11:06:38 +00:00
|
|
|
ib_dev->query_pkey = hns_roce_query_pkey;
|
|
|
|
ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
|
|
|
|
ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
|
|
|
|
ib_dev->mmap = hns_roce_mmap;
|
|
|
|
|
|
|
|
/* PD */
|
|
|
|
ib_dev->alloc_pd = hns_roce_alloc_pd;
|
|
|
|
ib_dev->dealloc_pd = hns_roce_dealloc_pd;
|
|
|
|
|
|
|
|
/* AH */
|
|
|
|
ib_dev->create_ah = hns_roce_create_ah;
|
|
|
|
ib_dev->query_ah = hns_roce_query_ah;
|
|
|
|
ib_dev->destroy_ah = hns_roce_destroy_ah;
|
|
|
|
|
|
|
|
/* QP */
|
|
|
|
ib_dev->create_qp = hns_roce_create_qp;
|
|
|
|
ib_dev->modify_qp = hns_roce_modify_qp;
|
|
|
|
ib_dev->query_qp = hr_dev->hw->query_qp;
|
|
|
|
ib_dev->destroy_qp = hr_dev->hw->destroy_qp;
|
|
|
|
ib_dev->post_send = hr_dev->hw->post_send;
|
|
|
|
ib_dev->post_recv = hr_dev->hw->post_recv;
|
|
|
|
|
|
|
|
/* CQ */
|
|
|
|
ib_dev->create_cq = hns_roce_ib_create_cq;
|
|
|
|
ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
|
|
|
|
ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
|
|
|
|
ib_dev->poll_cq = hr_dev->hw->poll_cq;
|
|
|
|
|
|
|
|
/* MR */
|
|
|
|
ib_dev->get_dma_mr = hns_roce_get_dma_mr;
|
|
|
|
ib_dev->reg_user_mr = hns_roce_reg_user_mr;
|
|
|
|
ib_dev->dereg_mr = hns_roce_dereg_mr;
|
|
|
|
|
|
|
|
/* OTHERS */
|
|
|
|
ib_dev->get_port_immutable = hns_roce_port_immutable;
|
|
|
|
|
|
|
|
ret = ib_register_device(ib_dev, NULL);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "ib_register_device failed!\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-11-23 19:41:08 +00:00
|
|
|
ret = hns_roce_setup_mtu_mac(hr_dev);
|
2016-07-21 11:06:38 +00:00
|
|
|
if (ret) {
|
2016-11-23 19:41:08 +00:00
|
|
|
dev_err(dev, "setup_mtu_mac failed!\n");
|
|
|
|
goto error_failed_setup_mtu_mac;
|
2016-07-21 11:06:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
iboe->nb.notifier_call = hns_roce_netdev_event;
|
|
|
|
ret = register_netdevice_notifier(&iboe->nb);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "register_netdevice_notifier failed!\n");
|
2016-11-23 19:41:08 +00:00
|
|
|
goto error_failed_setup_mtu_mac;
|
2016-07-21 11:06:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2016-11-23 19:41:08 +00:00
|
|
|
error_failed_setup_mtu_mac:
|
2016-07-21 11:06:38 +00:00
|
|
|
ib_unregister_device(ib_dev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
|
|
|
|
{
|
|
|
|
int ret;
|
2017-08-30 09:23:02 +00:00
|
|
|
struct device *dev = hr_dev->dev;
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
|
|
|
|
HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
|
|
|
|
hr_dev->caps.num_mtt_segs, 1);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init MTT context memory, aborting.\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-08-30 09:23:09 +00:00
|
|
|
if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
|
|
|
|
ret = hns_roce_init_hem_table(hr_dev,
|
|
|
|
&hr_dev->mr_table.mtt_cqe_table,
|
|
|
|
HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
|
|
|
|
hr_dev->caps.num_cqe_segs, 1);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
|
|
|
|
goto err_unmap_cqe;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-07-21 11:06:38 +00:00
|
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
|
|
|
|
HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
|
|
|
|
hr_dev->caps.num_mtpts, 1);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
|
|
|
|
goto err_unmap_mtt;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
|
|
|
|
HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
|
|
|
|
hr_dev->caps.num_qps, 1);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init QP context memory, aborting.\n");
|
|
|
|
goto err_unmap_dmpt;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
|
|
|
|
HEM_TYPE_IRRL,
|
|
|
|
hr_dev->caps.irrl_entry_sz *
|
|
|
|
hr_dev->caps.max_qp_init_rdma,
|
|
|
|
hr_dev->caps.num_qps, 1);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
|
|
|
|
goto err_unmap_qp;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
|
|
|
|
HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
|
|
|
|
hr_dev->caps.num_cqs, 1);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init CQ context memory, aborting.\n");
|
|
|
|
goto err_unmap_irrl;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_unmap_irrl:
|
|
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
|
|
|
|
|
|
|
|
err_unmap_qp:
|
|
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
|
|
|
|
|
|
|
|
err_unmap_dmpt:
|
|
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
|
|
|
|
|
|
|
|
err_unmap_mtt:
|
|
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
|
2017-08-30 09:23:09 +00:00
|
|
|
if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
|
|
|
|
hns_roce_cleanup_hem_table(hr_dev,
|
|
|
|
&hr_dev->mr_table.mtt_cqe_table);
|
|
|
|
|
|
|
|
err_unmap_cqe:
|
|
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2016-11-23 19:41:09 +00:00
|
|
|
* hns_roce_setup_hca - setup host channel adapter
|
|
|
|
* @hr_dev: pointer to hns roce device
|
|
|
|
* Return : int
|
|
|
|
*/
|
2016-07-21 11:06:38 +00:00
|
|
|
static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
|
|
|
|
{
|
|
|
|
int ret;
|
2017-08-30 09:23:02 +00:00
|
|
|
struct device *dev = hr_dev->dev;
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
spin_lock_init(&hr_dev->sm_lock);
|
|
|
|
spin_lock_init(&hr_dev->bt_cmd_lock);
|
|
|
|
|
|
|
|
ret = hns_roce_init_uar_table(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to initialize uar table. aborting\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to allocate priv_uar.\n");
|
|
|
|
goto err_uar_table_free;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_init_pd_table(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init protected domain table.\n");
|
|
|
|
goto err_uar_alloc_free;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_init_mr_table(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init memory region table.\n");
|
|
|
|
goto err_pd_table_free;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_init_cq_table(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init completion queue table.\n");
|
|
|
|
goto err_mr_table_free;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_init_qp_table(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to init queue pair table.\n");
|
|
|
|
goto err_cq_table_free;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_cq_table_free:
|
|
|
|
hns_roce_cleanup_cq_table(hr_dev);
|
|
|
|
|
|
|
|
err_mr_table_free:
|
|
|
|
hns_roce_cleanup_mr_table(hr_dev);
|
|
|
|
|
|
|
|
err_pd_table_free:
|
|
|
|
hns_roce_cleanup_pd_table(hr_dev);
|
|
|
|
|
|
|
|
err_uar_alloc_free:
|
|
|
|
hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
|
|
|
|
|
|
|
|
err_uar_table_free:
|
|
|
|
hns_roce_cleanup_uar_table(hr_dev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-08-30 09:22:59 +00:00
|
|
|
int hns_roce_init(struct hns_roce_dev *hr_dev)
|
2016-07-21 11:06:38 +00:00
|
|
|
{
|
|
|
|
int ret;
|
2017-08-30 09:23:02 +00:00
|
|
|
struct device *dev = hr_dev->dev;
|
2016-07-21 11:06:38 +00:00
|
|
|
|
2017-08-30 09:22:59 +00:00
|
|
|
if (hr_dev->hw->reset) {
|
|
|
|
ret = hr_dev->hw->reset(hr_dev, true);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Reset RoCE engine failed!\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2016-07-21 11:06:38 +00:00
|
|
|
}
|
|
|
|
|
2017-08-30 09:23:03 +00:00
|
|
|
if (hr_dev->hw->cmq_init) {
|
|
|
|
ret = hr_dev->hw->cmq_init(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Init RoCE Command Queue failed!\n");
|
|
|
|
goto error_failed_cmq_init;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-08-30 09:23:04 +00:00
|
|
|
ret = hr_dev->hw->hw_profile(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Get RoCE engine profile failed!\n");
|
|
|
|
goto error_failed_cmd_init;
|
|
|
|
}
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
ret = hns_roce_cmd_init(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "cmd init failed!\n");
|
|
|
|
goto error_failed_cmd_init;
|
|
|
|
}
|
|
|
|
|
2017-08-30 09:22:59 +00:00
|
|
|
if (hr_dev->cmd_mod) {
|
|
|
|
ret = hns_roce_init_eq_table(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "eq init failed!\n");
|
|
|
|
goto error_failed_eq_table;
|
|
|
|
}
|
2016-07-21 11:06:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (hr_dev->cmd_mod) {
|
|
|
|
ret = hns_roce_cmd_use_events(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Switch to event-driven cmd failed!\n");
|
|
|
|
goto error_failed_use_event;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_init_hem(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
|
|
|
|
goto error_failed_init_hem;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_setup_hca(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "setup hca failed!\n");
|
|
|
|
goto error_failed_setup_hca;
|
|
|
|
}
|
|
|
|
|
2017-08-30 09:22:59 +00:00
|
|
|
if (hr_dev->hw->hw_init) {
|
|
|
|
ret = hr_dev->hw->hw_init(hr_dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "hw_init failed!\n");
|
|
|
|
goto error_failed_engine_init;
|
|
|
|
}
|
2016-07-21 11:06:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = hns_roce_register_device(hr_dev);
|
|
|
|
if (ret)
|
|
|
|
goto error_failed_register_device;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error_failed_register_device:
|
2017-08-30 09:22:59 +00:00
|
|
|
if (hr_dev->hw->hw_exit)
|
|
|
|
hr_dev->hw->hw_exit(hr_dev);
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
error_failed_engine_init:
|
|
|
|
hns_roce_cleanup_bitmap(hr_dev);
|
|
|
|
|
|
|
|
error_failed_setup_hca:
|
|
|
|
hns_roce_cleanup_hem(hr_dev);
|
|
|
|
|
|
|
|
error_failed_init_hem:
|
|
|
|
if (hr_dev->cmd_mod)
|
|
|
|
hns_roce_cmd_use_polling(hr_dev);
|
|
|
|
|
|
|
|
error_failed_use_event:
|
2017-08-30 09:22:59 +00:00
|
|
|
if (hr_dev->cmd_mod)
|
|
|
|
hns_roce_cleanup_eq_table(hr_dev);
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
error_failed_eq_table:
|
|
|
|
hns_roce_cmd_cleanup(hr_dev);
|
|
|
|
|
|
|
|
error_failed_cmd_init:
|
2017-08-30 09:23:03 +00:00
|
|
|
if (hr_dev->hw->cmq_exit)
|
|
|
|
hr_dev->hw->cmq_exit(hr_dev);
|
|
|
|
|
|
|
|
error_failed_cmq_init:
|
2017-08-30 09:22:59 +00:00
|
|
|
if (hr_dev->hw->reset) {
|
|
|
|
ret = hr_dev->hw->reset(hr_dev, false);
|
|
|
|
if (ret)
|
|
|
|
dev_err(dev, "Dereset RoCE engine failed!\n");
|
|
|
|
}
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
2017-08-30 09:22:59 +00:00
|
|
|
EXPORT_SYMBOL_GPL(hns_roce_init);
|
2016-07-21 11:06:38 +00:00
|
|
|
|
2017-08-30 09:22:59 +00:00
|
|
|
void hns_roce_exit(struct hns_roce_dev *hr_dev)
|
2016-07-21 11:06:38 +00:00
|
|
|
{
|
|
|
|
hns_roce_unregister_device(hr_dev);
|
2017-08-30 09:22:59 +00:00
|
|
|
if (hr_dev->hw->hw_exit)
|
|
|
|
hr_dev->hw->hw_exit(hr_dev);
|
2016-07-21 11:06:38 +00:00
|
|
|
hns_roce_cleanup_bitmap(hr_dev);
|
|
|
|
hns_roce_cleanup_hem(hr_dev);
|
|
|
|
|
|
|
|
if (hr_dev->cmd_mod)
|
|
|
|
hns_roce_cmd_use_polling(hr_dev);
|
|
|
|
|
2017-08-30 09:22:59 +00:00
|
|
|
if (hr_dev->cmd_mod)
|
|
|
|
hns_roce_cleanup_eq_table(hr_dev);
|
2016-07-21 11:06:38 +00:00
|
|
|
hns_roce_cmd_cleanup(hr_dev);
|
2017-08-30 09:23:03 +00:00
|
|
|
if (hr_dev->hw->cmq_exit)
|
|
|
|
hr_dev->hw->cmq_exit(hr_dev);
|
2017-08-30 09:22:59 +00:00
|
|
|
if (hr_dev->hw->reset)
|
|
|
|
hr_dev->hw->reset(hr_dev, false);
|
2016-07-21 11:06:38 +00:00
|
|
|
}
|
2017-08-30 09:22:59 +00:00
|
|
|
EXPORT_SYMBOL_GPL(hns_roce_exit);
|
2016-07-21 11:06:38 +00:00
|
|
|
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
|
|
|
MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
|
|
|
|
MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
|
|
|
|
MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
|
|
|
|
MODULE_DESCRIPTION("HNS RoCE Driver");
|