2010-03-06 03:34:20 +00:00
|
|
|
/*
|
2010-09-15 18:50:55 +00:00
|
|
|
* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
|
2010-03-06 03:34:20 +00:00
|
|
|
* All rights reserved
|
|
|
|
* www.brocade.com
|
|
|
|
*
|
|
|
|
* Linux driver for Brocade Fibre Channel Host Bus Adapter.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
|
|
* under the terms of the GNU General Public License (GPL) Version 2 as
|
|
|
|
* published by the Free Software Foundation
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful, but
|
|
|
|
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
* General Public License for more details.
|
|
|
|
*/
|
|
|
|
|
2010-12-10 03:12:32 +00:00
|
|
|
#include "bfad_drv.h"
|
2010-09-15 18:50:55 +00:00
|
|
|
#include "bfa_ioc.h"
|
|
|
|
#include "bfi_cbreg.h"
|
|
|
|
#include "bfa_defs.h"
|
2010-03-06 03:34:20 +00:00
|
|
|
|
|
|
|
BFA_TRC_FILE(CNA, IOC_CB);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* forward declarations
|
|
|
|
*/
|
|
|
|
static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc);
|
|
|
|
static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc);
|
|
|
|
static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc);
|
|
|
|
static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc);
|
|
|
|
static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
|
2010-12-14 00:17:11 +00:00
|
|
|
static void bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc);
|
2010-03-06 03:34:20 +00:00
|
|
|
static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc);
|
2010-12-14 00:17:11 +00:00
|
|
|
static void bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc);
|
|
|
|
static void bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc);
|
|
|
|
static void bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc);
|
|
|
|
static bfa_boolean_t bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc);
|
2010-03-06 03:34:20 +00:00
|
|
|
|
2010-11-30 02:21:32 +00:00
|
|
|
static struct bfa_ioc_hwif_s hwif_cb;
|
2010-03-06 03:34:20 +00:00
|
|
|
|
2010-10-19 00:17:23 +00:00
|
|
|
/*
|
2010-03-06 03:34:20 +00:00
|
|
|
* Called from bfa_ioc_attach() to map asic specific calls.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc)
|
|
|
|
{
|
2010-07-09 02:45:20 +00:00
|
|
|
hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init;
|
|
|
|
hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock;
|
|
|
|
hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock;
|
|
|
|
hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init;
|
|
|
|
hwif_cb.ioc_map_port = bfa_ioc_cb_map_port;
|
|
|
|
hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set;
|
2010-12-14 00:17:11 +00:00
|
|
|
hwif_cb.ioc_notify_fail = bfa_ioc_cb_notify_fail;
|
2010-07-09 02:45:20 +00:00
|
|
|
hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset;
|
2010-12-14 00:17:11 +00:00
|
|
|
hwif_cb.ioc_sync_join = bfa_ioc_cb_sync_join;
|
|
|
|
hwif_cb.ioc_sync_leave = bfa_ioc_cb_sync_leave;
|
|
|
|
hwif_cb.ioc_sync_ack = bfa_ioc_cb_sync_ack;
|
|
|
|
hwif_cb.ioc_sync_complete = bfa_ioc_cb_sync_complete;
|
2010-03-06 03:34:20 +00:00
|
|
|
|
2010-07-09 02:45:20 +00:00
|
|
|
ioc->ioc_hwif = &hwif_cb;
|
2010-03-06 03:34:20 +00:00
|
|
|
}
|
|
|
|
|
2010-12-14 00:17:11 +00:00
|
|
|
/**
|
2010-03-06 03:34:20 +00:00
|
|
|
* Return true if firmware of current driver matches the running firmware.
|
|
|
|
*/
|
|
|
|
static bfa_boolean_t
|
|
|
|
bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc)
|
|
|
|
{
|
2010-12-14 00:17:11 +00:00
|
|
|
struct bfi_ioc_image_hdr_s fwhdr;
|
|
|
|
uint32_t fwstate = readl(ioc->ioc_regs.ioc_fwstate);
|
|
|
|
|
|
|
|
if ((fwstate == BFI_IOC_UNINIT) || bfa_ioc_is_uefi(ioc) ||
|
|
|
|
bfa_ioc_is_bios_optrom(ioc))
|
|
|
|
return BFA_TRUE;
|
|
|
|
|
|
|
|
bfa_ioc_fwver_get(ioc, &fwhdr);
|
|
|
|
|
|
|
|
if (swab32(fwhdr.exec) == BFI_BOOT_TYPE_NORMAL)
|
|
|
|
return BFA_TRUE;
|
|
|
|
|
|
|
|
bfa_trc(ioc, fwstate);
|
|
|
|
bfa_trc(ioc, fwhdr.exec);
|
|
|
|
writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
|
|
|
|
|
2010-03-06 03:34:20 +00:00
|
|
|
return BFA_TRUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2010-10-19 00:17:23 +00:00
|
|
|
/*
|
2010-03-06 03:34:20 +00:00
|
|
|
* Notify other functions on HB failure.
|
|
|
|
*/
|
|
|
|
static void
|
2010-12-14 00:17:11 +00:00
|
|
|
bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc)
|
2010-03-06 03:34:20 +00:00
|
|
|
{
|
2010-10-19 00:12:29 +00:00
|
|
|
writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
|
|
|
|
readl(ioc->ioc_regs.err_set);
|
2010-03-06 03:34:20 +00:00
|
|
|
}
|
|
|
|
|
2010-10-19 00:17:23 +00:00
|
|
|
/*
|
2010-03-06 03:34:20 +00:00
|
|
|
* Host to LPU mailbox message addresses
|
|
|
|
*/
|
2010-03-06 03:38:44 +00:00
|
|
|
static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
|
2010-03-06 03:34:20 +00:00
|
|
|
{ HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
|
|
|
|
{ HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }
|
|
|
|
};
|
|
|
|
|
2010-10-19 00:17:23 +00:00
|
|
|
/*
|
2010-03-06 03:34:20 +00:00
|
|
|
* Host <-> LPU mailbox command/status registers
|
|
|
|
*/
|
2010-03-06 03:38:44 +00:00
|
|
|
static struct { u32 hfn, lpu; } iocreg_mbcmd[] = {
|
2010-09-15 18:50:55 +00:00
|
|
|
|
2010-03-06 03:34:20 +00:00
|
|
|
{ HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
|
|
|
|
{ HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT }
|
|
|
|
};
|
|
|
|
|
|
|
|
static void
|
|
|
|
bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc)
|
|
|
|
{
|
2010-10-19 00:12:29 +00:00
|
|
|
void __iomem *rb;
|
2010-03-06 03:34:20 +00:00
|
|
|
int pcifn = bfa_ioc_pcifn(ioc);
|
|
|
|
|
|
|
|
rb = bfa_ioc_bar0(ioc);
|
|
|
|
|
|
|
|
ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
|
|
|
|
ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
|
|
|
|
ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
|
|
|
|
|
|
|
|
if (ioc->port_id == 0) {
|
|
|
|
ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
|
|
|
|
ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
|
2010-12-14 00:17:11 +00:00
|
|
|
ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
|
2010-03-06 03:34:20 +00:00
|
|
|
} else {
|
|
|
|
ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
|
|
|
|
ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
|
2010-12-14 00:17:11 +00:00
|
|
|
ioc->ioc_regs.alt_ioc_fwstate = (rb + BFA_IOC0_STATE_REG);
|
2010-03-06 03:34:20 +00:00
|
|
|
}
|
|
|
|
|
2010-10-19 00:17:23 +00:00
|
|
|
/*
|
2010-03-06 03:34:20 +00:00
|
|
|
* Host <-> LPU mailbox command/status registers
|
|
|
|
*/
|
|
|
|
ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn;
|
|
|
|
ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PSS control registers
|
|
|
|
*/
|
|
|
|
ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
|
2010-03-06 03:34:44 +00:00
|
|
|
ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
|
2010-03-06 03:34:20 +00:00
|
|
|
ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG);
|
|
|
|
ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* IOC semaphore registers and serialization
|
|
|
|
*/
|
|
|
|
ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
|
|
|
|
ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
|
|
|
|
|
2010-10-19 00:17:23 +00:00
|
|
|
/*
|
2010-03-06 03:34:20 +00:00
|
|
|
* sram memory access
|
|
|
|
*/
|
|
|
|
ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
|
|
|
|
ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* err set reg : for notification of hb failure
|
|
|
|
*/
|
|
|
|
ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
|
|
|
|
}
|
|
|
|
|
2010-10-19 00:17:23 +00:00
|
|
|
/*
|
2010-03-06 03:34:20 +00:00
|
|
|
* Initialize IOC to port mapping.
|
|
|
|
*/
|
2010-09-15 18:50:55 +00:00
|
|
|
|
2010-03-06 03:34:20 +00:00
|
|
|
static void
|
|
|
|
bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc)
|
|
|
|
{
|
2010-10-19 00:17:23 +00:00
|
|
|
/*
|
2010-03-06 03:34:20 +00:00
|
|
|
* For crossbow, port id is same as pci function.
|
|
|
|
*/
|
|
|
|
ioc->port_id = bfa_ioc_pcifn(ioc);
|
2010-09-15 18:50:55 +00:00
|
|
|
|
2010-03-06 03:34:20 +00:00
|
|
|
bfa_trc(ioc, ioc->port_id);
|
|
|
|
}
|
|
|
|
|
2010-10-19 00:17:23 +00:00
|
|
|
/*
|
2010-03-06 03:34:20 +00:00
|
|
|
* Set interrupt mode for a function: INTX or MSIX
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2010-10-19 00:17:23 +00:00
|
|
|
/*
|
2010-09-15 18:50:55 +00:00
|
|
|
* Cleanup hw semaphore and usecnt registers
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc)
|
2010-03-06 03:34:20 +00:00
|
|
|
{
|
|
|
|
|
|
|
|
/*
|
2010-09-15 18:50:55 +00:00
|
|
|
* Read the hw sem reg to make sure that it is locked
|
|
|
|
* before we clear it. If it is not locked, writing 1
|
|
|
|
* will lock it instead of clearing it.
|
2010-03-06 03:34:20 +00:00
|
|
|
*/
|
2010-10-19 00:12:29 +00:00
|
|
|
readl(ioc->ioc_regs.ioc_sem_reg);
|
2010-12-10 03:08:43 +00:00
|
|
|
writel(1, ioc->ioc_regs.ioc_sem_reg);
|
2010-09-15 18:50:55 +00:00
|
|
|
}
|
|
|
|
|
2010-12-14 00:17:11 +00:00
|
|
|
/**
|
|
|
|
* Synchronized IOC failure processing routines
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc)
|
|
|
|
{
|
|
|
|
writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bfa_boolean_t
|
|
|
|
bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc)
|
|
|
|
{
|
|
|
|
uint32_t fwstate, alt_fwstate;
|
|
|
|
fwstate = readl(ioc->ioc_regs.ioc_fwstate);
|
2010-09-15 18:50:55 +00:00
|
|
|
|
2010-12-14 00:17:11 +00:00
|
|
|
/**
|
|
|
|
* At this point, this IOC is hoding the hw sem in the
|
|
|
|
* start path (fwcheck) OR in the disable/enable path
|
|
|
|
* OR to check if the other IOC has acknowledged failure.
|
|
|
|
*
|
|
|
|
* So, this IOC can be in UNINIT, INITING, DISABLED, FAIL
|
|
|
|
* or in MEMTEST states. In a normal scenario, this IOC
|
|
|
|
* can not be in OP state when this function is called.
|
|
|
|
*
|
|
|
|
* However, this IOC could still be in OP state when
|
|
|
|
* the OS driver is starting up, if the OptROM code has
|
|
|
|
* left it in that state.
|
|
|
|
*
|
|
|
|
* If we had marked this IOC's fwstate as BFI_IOC_FAIL
|
|
|
|
* in the failure case and now, if the fwstate is not
|
|
|
|
* BFI_IOC_FAIL it implies that the other PCI fn have
|
|
|
|
* reinitialized the ASIC or this IOC got disabled, so
|
|
|
|
* return TRUE.
|
|
|
|
*/
|
|
|
|
if (fwstate == BFI_IOC_UNINIT ||
|
|
|
|
fwstate == BFI_IOC_INITING ||
|
|
|
|
fwstate == BFI_IOC_DISABLED ||
|
|
|
|
fwstate == BFI_IOC_MEMTEST ||
|
|
|
|
fwstate == BFI_IOC_OP)
|
|
|
|
return BFA_TRUE;
|
|
|
|
else {
|
|
|
|
alt_fwstate = readl(ioc->ioc_regs.alt_ioc_fwstate);
|
|
|
|
if (alt_fwstate == BFI_IOC_FAIL ||
|
|
|
|
alt_fwstate == BFI_IOC_DISABLED ||
|
|
|
|
alt_fwstate == BFI_IOC_UNINIT ||
|
|
|
|
alt_fwstate == BFI_IOC_INITING ||
|
|
|
|
alt_fwstate == BFI_IOC_MEMTEST)
|
|
|
|
return BFA_TRUE;
|
|
|
|
else
|
|
|
|
return BFA_FALSE;
|
|
|
|
}
|
|
|
|
}
|
2010-09-15 18:50:55 +00:00
|
|
|
|
|
|
|
bfa_status_t
|
2010-10-19 00:12:29 +00:00
|
|
|
bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
|
2010-09-15 18:50:55 +00:00
|
|
|
{
|
|
|
|
u32 pll_sclk, pll_fclk;
|
2010-03-06 03:34:20 +00:00
|
|
|
|
|
|
|
pll_sclk = __APP_PLL_212_ENABLE | __APP_PLL_212_LRESETN |
|
2010-09-15 18:50:55 +00:00
|
|
|
__APP_PLL_212_P0_1(3U) |
|
|
|
|
__APP_PLL_212_JITLMT0_1(3U) |
|
|
|
|
__APP_PLL_212_CNTLMT0_1(3U);
|
2010-03-06 03:34:20 +00:00
|
|
|
pll_fclk = __APP_PLL_400_ENABLE | __APP_PLL_400_LRESETN |
|
2010-09-15 18:50:55 +00:00
|
|
|
__APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) |
|
|
|
|
__APP_PLL_400_JITLMT0_1(3U) |
|
|
|
|
__APP_PLL_400_CNTLMT0_1(3U);
|
2010-10-19 00:12:29 +00:00
|
|
|
writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
|
|
|
|
writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
|
|
|
|
writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
|
|
|
|
writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
|
|
|
|
writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
|
|
|
|
writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
|
|
|
|
writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
|
|
|
|
writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
|
|
|
|
writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG);
|
|
|
|
writel(__APP_PLL_212_BYPASS | __APP_PLL_212_LOGIC_SOFT_RESET,
|
|
|
|
rb + APP_PLL_212_CTL_REG);
|
|
|
|
writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG);
|
|
|
|
writel(__APP_PLL_400_BYPASS | __APP_PLL_400_LOGIC_SOFT_RESET,
|
|
|
|
rb + APP_PLL_400_CTL_REG);
|
2010-10-19 00:08:54 +00:00
|
|
|
udelay(2);
|
2010-10-19 00:12:29 +00:00
|
|
|
writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG);
|
|
|
|
writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG);
|
|
|
|
writel(pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET,
|
|
|
|
rb + APP_PLL_212_CTL_REG);
|
|
|
|
writel(pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET,
|
|
|
|
rb + APP_PLL_400_CTL_REG);
|
2010-10-19 00:08:54 +00:00
|
|
|
udelay(2000);
|
2010-10-19 00:12:29 +00:00
|
|
|
writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
|
|
|
|
writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
|
|
|
|
writel(pll_sclk, (rb + APP_PLL_212_CTL_REG));
|
|
|
|
writel(pll_fclk, (rb + APP_PLL_400_CTL_REG));
|
2010-03-06 03:34:20 +00:00
|
|
|
|
|
|
|
return BFA_STATUS_OK;
|
|
|
|
}
|