2014-05-08 21:57:00 +00:00
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/*
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* BMG160 Gyro Sensor driver
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* Copyright (c) 2014, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/acpi.h>
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#include <linux/gpio/consumer.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/events.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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2015-08-12 14:50:04 +00:00
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#include <linux/regmap.h>
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2015-08-19 12:12:45 +00:00
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#include "bmg160.h"
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2014-05-08 21:57:00 +00:00
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#define BMG160_IRQ_NAME "bmg160_event"
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#define BMG160_GPIO_NAME "gpio_int"
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#define BMG160_REG_CHIP_ID 0x00
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#define BMG160_CHIP_ID_VAL 0x0F
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#define BMG160_REG_PMU_LPW 0x11
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#define BMG160_MODE_NORMAL 0x00
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#define BMG160_MODE_DEEP_SUSPEND 0x20
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#define BMG160_MODE_SUSPEND 0x80
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#define BMG160_REG_RANGE 0x0F
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#define BMG160_RANGE_2000DPS 0
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#define BMG160_RANGE_1000DPS 1
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#define BMG160_RANGE_500DPS 2
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#define BMG160_RANGE_250DPS 3
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#define BMG160_RANGE_125DPS 4
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#define BMG160_REG_PMU_BW 0x10
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#define BMG160_NO_FILTER 0
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#define BMG160_DEF_BW 100
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#define BMG160_REG_INT_MAP_0 0x17
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#define BMG160_INT_MAP_0_BIT_ANY BIT(1)
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#define BMG160_REG_INT_MAP_1 0x18
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#define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0)
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#define BMG160_REG_INT_RST_LATCH 0x21
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#define BMG160_INT_MODE_LATCH_RESET 0x80
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#define BMG160_INT_MODE_LATCH_INT 0x0F
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#define BMG160_INT_MODE_NON_LATCH_INT 0x00
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#define BMG160_REG_INT_EN_0 0x15
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#define BMG160_DATA_ENABLE_INT BIT(7)
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2014-10-11 03:33:26 +00:00
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#define BMG160_REG_INT_EN_1 0x16
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#define BMG160_INT1_BIT_OD BIT(1)
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2014-05-08 21:57:00 +00:00
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#define BMG160_REG_XOUT_L 0x02
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#define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2))
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#define BMG160_REG_SLOPE_THRES 0x1B
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#define BMG160_SLOPE_THRES_MASK 0x0F
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#define BMG160_REG_MOTION_INTR 0x1C
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#define BMG160_INT_MOTION_X BIT(0)
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#define BMG160_INT_MOTION_Y BIT(1)
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#define BMG160_INT_MOTION_Z BIT(2)
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#define BMG160_ANY_DUR_MASK 0x30
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#define BMG160_ANY_DUR_SHIFT 4
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#define BMG160_REG_INT_STATUS_2 0x0B
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#define BMG160_ANY_MOTION_MASK 0x07
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2014-10-11 03:33:27 +00:00
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#define BMG160_ANY_MOTION_BIT_X BIT(0)
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#define BMG160_ANY_MOTION_BIT_Y BIT(1)
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#define BMG160_ANY_MOTION_BIT_Z BIT(2)
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2014-05-08 21:57:00 +00:00
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#define BMG160_REG_TEMP 0x08
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#define BMG160_TEMP_CENTER_VAL 23
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#define BMG160_MAX_STARTUP_TIME_MS 80
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#define BMG160_AUTO_SUSPEND_DELAY_MS 2000
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struct bmg160_data {
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2015-08-12 14:50:05 +00:00
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struct device *dev;
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2015-08-12 14:50:04 +00:00
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struct regmap *regmap;
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2014-05-08 21:57:00 +00:00
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struct iio_trigger *dready_trig;
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struct iio_trigger *motion_trig;
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struct mutex mutex;
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s16 buffer[8];
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u8 bw_bits;
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u32 dps_range;
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int ev_enable_state;
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int slope_thres;
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bool dready_trigger_on;
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bool motion_trigger_on;
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2015-08-12 14:50:07 +00:00
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int irq;
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2014-05-08 21:57:00 +00:00
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};
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enum bmg160_axis {
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AXIS_X,
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AXIS_Y,
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AXIS_Z,
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};
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static const struct {
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int val;
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int bw_bits;
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} bmg160_samp_freq_table[] = { {100, 0x07},
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{200, 0x06},
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{400, 0x03},
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{1000, 0x02},
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{2000, 0x01} };
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static const struct {
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int scale;
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int dps_range;
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} bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS},
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{ 532, BMG160_RANGE_1000DPS},
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{ 266, BMG160_RANGE_500DPS},
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{ 133, BMG160_RANGE_250DPS},
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{ 66, BMG160_RANGE_125DPS} };
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static int bmg160_set_mode(struct bmg160_data *data, u8 mode)
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{
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int ret;
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2015-08-12 14:50:04 +00:00
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ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode);
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2014-05-08 21:57:00 +00:00
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev, "Error writing reg_pmu_lpw\n");
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2014-05-08 21:57:00 +00:00
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return ret;
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}
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return 0;
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}
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static int bmg160_convert_freq_to_bit(int val)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
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if (bmg160_samp_freq_table[i].val == val)
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return bmg160_samp_freq_table[i].bw_bits;
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}
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return -EINVAL;
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}
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static int bmg160_set_bw(struct bmg160_data *data, int val)
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{
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int ret;
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int bw_bits;
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bw_bits = bmg160_convert_freq_to_bit(val);
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if (bw_bits < 0)
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return bw_bits;
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2015-08-12 14:50:04 +00:00
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ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits);
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2014-05-08 21:57:00 +00:00
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev, "Error writing reg_pmu_bw\n");
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2014-05-08 21:57:00 +00:00
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return ret;
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}
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data->bw_bits = bw_bits;
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return 0;
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}
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static int bmg160_chip_init(struct bmg160_data *data)
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{
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int ret;
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2015-08-12 14:50:04 +00:00
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unsigned int val;
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2014-05-08 21:57:00 +00:00
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2015-08-12 14:50:04 +00:00
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ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val);
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2014-05-08 21:57:00 +00:00
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev, "Error reading reg_chip_id\n");
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2014-05-08 21:57:00 +00:00
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return ret;
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}
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2015-08-12 14:50:05 +00:00
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dev_dbg(data->dev, "Chip Id %x\n", val);
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2015-08-12 14:50:04 +00:00
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if (val != BMG160_CHIP_ID_VAL) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev, "invalid chip %x\n", val);
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2014-05-08 21:57:00 +00:00
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return -ENODEV;
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}
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ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
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if (ret < 0)
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return ret;
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/* Wait upto 500 ms to be ready after changing mode */
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usleep_range(500, 1000);
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/* Set Bandwidth */
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ret = bmg160_set_bw(data, BMG160_DEF_BW);
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if (ret < 0)
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return ret;
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/* Set Default Range */
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2015-08-12 14:50:04 +00:00
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ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS);
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2014-05-08 21:57:00 +00:00
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev, "Error writing reg_range\n");
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2014-05-08 21:57:00 +00:00
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return ret;
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}
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data->dps_range = BMG160_RANGE_500DPS;
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2015-08-12 14:50:04 +00:00
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ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val);
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2014-05-08 21:57:00 +00:00
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev, "Error reading reg_slope_thres\n");
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2014-05-08 21:57:00 +00:00
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return ret;
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}
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2015-08-12 14:50:04 +00:00
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data->slope_thres = val;
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2014-05-08 21:57:00 +00:00
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/* Set default interrupt mode */
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2015-08-12 14:50:04 +00:00
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ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1,
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BMG160_INT1_BIT_OD, 0);
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2014-10-11 03:33:26 +00:00
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev, "Error updating bits in reg_int_en_1\n");
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2014-10-11 03:33:26 +00:00
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return ret;
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}
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2015-08-12 14:50:04 +00:00
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ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
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BMG160_INT_MODE_LATCH_INT |
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BMG160_INT_MODE_LATCH_RESET);
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2014-05-08 21:57:00 +00:00
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev,
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2014-05-08 21:57:00 +00:00
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"Error writing reg_motion_intr\n");
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return ret;
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}
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return 0;
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}
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static int bmg160_set_power_state(struct bmg160_data *data, bool on)
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{
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2014-12-04 00:08:13 +00:00
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#ifdef CONFIG_PM
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2014-05-08 21:57:00 +00:00
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int ret;
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if (on)
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2015-08-12 14:50:05 +00:00
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ret = pm_runtime_get_sync(data->dev);
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2014-05-08 21:57:00 +00:00
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else {
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2015-08-12 14:50:05 +00:00
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pm_runtime_mark_last_busy(data->dev);
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ret = pm_runtime_put_autosuspend(data->dev);
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2014-05-08 21:57:00 +00:00
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}
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev,
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2014-05-08 21:57:00 +00:00
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"Failed: bmg160_set_power_state for %d\n", on);
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2014-10-11 03:33:25 +00:00
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if (on)
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2015-08-12 14:50:05 +00:00
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pm_runtime_put_noidle(data->dev);
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2014-10-11 03:33:25 +00:00
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2014-05-08 21:57:00 +00:00
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return ret;
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}
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2014-08-09 14:05:00 +00:00
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#endif
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2014-05-08 21:57:00 +00:00
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return 0;
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}
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static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data,
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bool status)
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{
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int ret;
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/* Enable/Disable INT_MAP0 mapping */
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2015-08-12 14:50:04 +00:00
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ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0,
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BMG160_INT_MAP_0_BIT_ANY,
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(status ? BMG160_INT_MAP_0_BIT_ANY : 0));
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2014-05-08 21:57:00 +00:00
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev, "Error updating bits reg_int_map0\n");
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2014-05-08 21:57:00 +00:00
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return ret;
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}
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/* Enable/Disable slope interrupts */
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if (status) {
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/* Update slope thres */
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2015-08-12 14:50:04 +00:00
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ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES,
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data->slope_thres);
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2014-05-08 21:57:00 +00:00
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev,
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2014-05-08 21:57:00 +00:00
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"Error writing reg_slope_thres\n");
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return ret;
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}
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2015-08-12 14:50:04 +00:00
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ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR,
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BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y |
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BMG160_INT_MOTION_Z);
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2014-05-08 21:57:00 +00:00
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if (ret < 0) {
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2015-08-12 14:50:05 +00:00
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dev_err(data->dev,
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2014-05-08 21:57:00 +00:00
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"Error writing reg_motion_intr\n");
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return ret;
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}
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/*
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* New data interrupt is always non-latched,
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* which will have higher priority, so no need
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* to set latched mode, we will be flooded anyway with INTR
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*/
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if (!data->dready_trigger_on) {
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2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_write(data->regmap,
|
|
|
|
BMG160_REG_INT_RST_LATCH,
|
|
|
|
BMG160_INT_MODE_LATCH_INT |
|
|
|
|
BMG160_INT_MODE_LATCH_RESET);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev,
|
2014-05-08 21:57:00 +00:00
|
|
|
"Error writing reg_rst_latch\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
|
|
|
|
BMG160_DATA_ENABLE_INT);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
} else {
|
|
|
|
ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
|
|
|
|
}
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev, "Error writing reg_int_en0\n");
|
2014-05-08 21:57:00 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_setup_new_data_interrupt(struct bmg160_data *data,
|
|
|
|
bool status)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Enable/Disable INT_MAP1 mapping */
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1,
|
|
|
|
BMG160_INT_MAP_1_BIT_NEW_DATA,
|
|
|
|
(status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0));
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev, "Error updating bits in reg_int_map1\n");
|
2014-05-08 21:57:00 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status) {
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
|
|
|
|
BMG160_INT_MODE_NON_LATCH_INT |
|
|
|
|
BMG160_INT_MODE_LATCH_RESET);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev,
|
2014-05-08 21:57:00 +00:00
|
|
|
"Error writing reg_rst_latch\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
|
|
|
|
BMG160_DATA_ENABLE_INT);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
} else {
|
|
|
|
/* Restore interrupt mode */
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
|
|
|
|
BMG160_INT_MODE_LATCH_INT |
|
|
|
|
BMG160_INT_MODE_LATCH_RESET);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev,
|
2014-05-08 21:57:00 +00:00
|
|
|
"Error writing reg_rst_latch\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
|
2014-05-08 21:57:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev, "Error writing reg_int_en0\n");
|
2014-05-08 21:57:00 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_get_bw(struct bmg160_data *data, int *val)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
|
|
|
|
if (bmg160_samp_freq_table[i].bw_bits == data->bw_bits) {
|
|
|
|
*val = bmg160_samp_freq_table[i].val;
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_set_scale(struct bmg160_data *data, int val)
|
|
|
|
{
|
|
|
|
int ret, i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
|
|
|
|
if (bmg160_scale_table[i].scale == val) {
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_write(data->regmap, BMG160_REG_RANGE,
|
|
|
|
bmg160_scale_table[i].dps_range);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev,
|
2014-05-08 21:57:00 +00:00
|
|
|
"Error writing reg_range\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
data->dps_range = bmg160_scale_table[i].dps_range;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_get_temp(struct bmg160_data *data, int *val)
|
|
|
|
{
|
|
|
|
int ret;
|
2015-08-12 14:50:04 +00:00
|
|
|
unsigned int raw_val;
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
mutex_lock(&data->mutex);
|
|
|
|
ret = bmg160_set_power_state(data, true);
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev, "Error reading reg_temp\n");
|
2014-05-08 21:57:00 +00:00
|
|
|
bmg160_set_power_state(data, false);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
*val = sign_extend32(raw_val, 7);
|
2014-05-08 21:57:00 +00:00
|
|
|
ret = bmg160_set_power_state(data, false);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val)
|
|
|
|
{
|
|
|
|
int ret;
|
2015-08-12 14:50:04 +00:00
|
|
|
unsigned int raw_val;
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
mutex_lock(&data->mutex);
|
|
|
|
ret = bmg160_set_power_state(data, true);
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val,
|
|
|
|
2);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev, "Error reading axis %d\n", axis);
|
2014-05-08 21:57:00 +00:00
|
|
|
bmg160_set_power_state(data, false);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
*val = sign_extend32(raw_val, 15);
|
2014-05-08 21:57:00 +00:00
|
|
|
ret = bmg160_set_power_state(data, false);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_read_raw(struct iio_dev *indio_dev,
|
|
|
|
struct iio_chan_spec const *chan,
|
|
|
|
int *val, int *val2, long mask)
|
|
|
|
{
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (mask) {
|
|
|
|
case IIO_CHAN_INFO_RAW:
|
|
|
|
switch (chan->type) {
|
|
|
|
case IIO_TEMP:
|
|
|
|
return bmg160_get_temp(data, val);
|
|
|
|
case IIO_ANGL_VEL:
|
|
|
|
if (iio_buffer_enabled(indio_dev))
|
|
|
|
return -EBUSY;
|
|
|
|
else
|
|
|
|
return bmg160_get_axis(data, chan->scan_index,
|
|
|
|
val);
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
case IIO_CHAN_INFO_OFFSET:
|
|
|
|
if (chan->type == IIO_TEMP) {
|
|
|
|
*val = BMG160_TEMP_CENTER_VAL;
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
} else
|
|
|
|
return -EINVAL;
|
|
|
|
case IIO_CHAN_INFO_SCALE:
|
|
|
|
*val = 0;
|
|
|
|
switch (chan->type) {
|
|
|
|
case IIO_TEMP:
|
|
|
|
*val2 = 500000;
|
|
|
|
return IIO_VAL_INT_PLUS_MICRO;
|
|
|
|
case IIO_ANGL_VEL:
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
|
|
|
|
if (bmg160_scale_table[i].dps_range ==
|
|
|
|
data->dps_range) {
|
|
|
|
*val2 = bmg160_scale_table[i].scale;
|
|
|
|
return IIO_VAL_INT_PLUS_MICRO;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
|
|
*val2 = 0;
|
|
|
|
mutex_lock(&data->mutex);
|
|
|
|
ret = bmg160_get_bw(data, val);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_write_raw(struct iio_dev *indio_dev,
|
|
|
|
struct iio_chan_spec const *chan,
|
|
|
|
int val, int val2, long mask)
|
|
|
|
{
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (mask) {
|
|
|
|
case IIO_CHAN_INFO_SAMP_FREQ:
|
|
|
|
mutex_lock(&data->mutex);
|
|
|
|
/*
|
|
|
|
* Section 4.2 of spec
|
|
|
|
* In suspend mode, the only supported operations are reading
|
|
|
|
* registers as well as writing to the (0x14) softreset
|
|
|
|
* register. Since we will be in suspend mode by default, change
|
|
|
|
* mode to power on for other writes.
|
|
|
|
*/
|
|
|
|
ret = bmg160_set_power_state(data, true);
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ret = bmg160_set_bw(data, val);
|
|
|
|
if (ret < 0) {
|
|
|
|
bmg160_set_power_state(data, false);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ret = bmg160_set_power_state(data, false);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
case IIO_CHAN_INFO_SCALE:
|
|
|
|
if (val)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mutex_lock(&data->mutex);
|
|
|
|
/* Refer to comments above for the suspend mode ops */
|
|
|
|
ret = bmg160_set_power_state(data, true);
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ret = bmg160_set_scale(data, val2);
|
|
|
|
if (ret < 0) {
|
|
|
|
bmg160_set_power_state(data, false);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ret = bmg160_set_power_state(data, false);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_read_event(struct iio_dev *indio_dev,
|
|
|
|
const struct iio_chan_spec *chan,
|
|
|
|
enum iio_event_type type,
|
|
|
|
enum iio_event_direction dir,
|
|
|
|
enum iio_event_info info,
|
|
|
|
int *val, int *val2)
|
|
|
|
{
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
*val2 = 0;
|
|
|
|
switch (info) {
|
|
|
|
case IIO_EV_INFO_VALUE:
|
|
|
|
*val = data->slope_thres & BMG160_SLOPE_THRES_MASK;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_write_event(struct iio_dev *indio_dev,
|
|
|
|
const struct iio_chan_spec *chan,
|
|
|
|
enum iio_event_type type,
|
|
|
|
enum iio_event_direction dir,
|
|
|
|
enum iio_event_info info,
|
|
|
|
int val, int val2)
|
|
|
|
{
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
switch (info) {
|
|
|
|
case IIO_EV_INFO_VALUE:
|
|
|
|
if (data->ev_enable_state)
|
|
|
|
return -EBUSY;
|
|
|
|
data->slope_thres &= ~BMG160_SLOPE_THRES_MASK;
|
|
|
|
data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_read_event_config(struct iio_dev *indio_dev,
|
|
|
|
const struct iio_chan_spec *chan,
|
|
|
|
enum iio_event_type type,
|
|
|
|
enum iio_event_direction dir)
|
|
|
|
{
|
|
|
|
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
return data->ev_enable_state;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_write_event_config(struct iio_dev *indio_dev,
|
|
|
|
const struct iio_chan_spec *chan,
|
|
|
|
enum iio_event_type type,
|
|
|
|
enum iio_event_direction dir,
|
|
|
|
int state)
|
|
|
|
{
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (state && data->ev_enable_state)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
mutex_lock(&data->mutex);
|
|
|
|
|
|
|
|
if (!state && data->motion_trigger_on) {
|
|
|
|
data->ev_enable_state = 0;
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* We will expect the enable and disable to do operation in
|
|
|
|
* in reverse order. This will happen here anyway as our
|
|
|
|
* resume operation uses sync mode runtime pm calls, the
|
|
|
|
* suspend operation will be delayed by autosuspend delay
|
|
|
|
* So the disable operation will still happen in reverse of
|
|
|
|
* enable operation. When runtime pm is disabled the mode
|
|
|
|
* is always on so sequence doesn't matter
|
|
|
|
*/
|
|
|
|
ret = bmg160_set_power_state(data, state);
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = bmg160_setup_any_motion_interrupt(data, state);
|
|
|
|
if (ret < 0) {
|
2014-10-11 03:33:25 +00:00
|
|
|
bmg160_set_power_state(data, false);
|
2014-05-08 21:57:00 +00:00
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
data->ev_enable_state = state;
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000");
|
|
|
|
|
|
|
|
static IIO_CONST_ATTR(in_anglvel_scale_available,
|
|
|
|
"0.001065 0.000532 0.000266 0.000133 0.000066");
|
|
|
|
|
|
|
|
static struct attribute *bmg160_attributes[] = {
|
|
|
|
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
|
|
|
|
&iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct attribute_group bmg160_attrs_group = {
|
|
|
|
.attrs = bmg160_attributes,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct iio_event_spec bmg160_event = {
|
|
|
|
.type = IIO_EV_TYPE_ROC,
|
2014-10-11 03:33:28 +00:00
|
|
|
.dir = IIO_EV_DIR_EITHER,
|
2014-05-08 21:57:00 +00:00
|
|
|
.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
|
|
|
|
BIT(IIO_EV_INFO_ENABLE)
|
|
|
|
};
|
|
|
|
|
|
|
|
#define BMG160_CHANNEL(_axis) { \
|
|
|
|
.type = IIO_ANGL_VEL, \
|
|
|
|
.modified = 1, \
|
|
|
|
.channel2 = IIO_MOD_##_axis, \
|
|
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
|
|
|
|
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
|
|
|
|
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
|
|
|
|
.scan_index = AXIS_##_axis, \
|
|
|
|
.scan_type = { \
|
|
|
|
.sign = 's', \
|
|
|
|
.realbits = 16, \
|
|
|
|
.storagebits = 16, \
|
|
|
|
}, \
|
|
|
|
.event_spec = &bmg160_event, \
|
|
|
|
.num_event_specs = 1 \
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct iio_chan_spec bmg160_channels[] = {
|
|
|
|
{
|
|
|
|
.type = IIO_TEMP,
|
|
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
|
|
|
BIT(IIO_CHAN_INFO_SCALE) |
|
|
|
|
BIT(IIO_CHAN_INFO_OFFSET),
|
|
|
|
.scan_index = -1,
|
|
|
|
},
|
|
|
|
BMG160_CHANNEL(X),
|
|
|
|
BMG160_CHANNEL(Y),
|
|
|
|
BMG160_CHANNEL(Z),
|
|
|
|
IIO_CHAN_SOFT_TIMESTAMP(3),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct iio_info bmg160_info = {
|
|
|
|
.attrs = &bmg160_attrs_group,
|
|
|
|
.read_raw = bmg160_read_raw,
|
|
|
|
.write_raw = bmg160_write_raw,
|
|
|
|
.read_event_value = bmg160_read_event,
|
|
|
|
.write_event_value = bmg160_write_event,
|
|
|
|
.write_event_config = bmg160_write_event_config,
|
|
|
|
.read_event_config = bmg160_read_event_config,
|
|
|
|
.driver_module = THIS_MODULE,
|
|
|
|
};
|
|
|
|
|
|
|
|
static irqreturn_t bmg160_trigger_handler(int irq, void *p)
|
|
|
|
{
|
|
|
|
struct iio_poll_func *pf = p;
|
|
|
|
struct iio_dev *indio_dev = pf->indio_dev;
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
int bit, ret, i = 0;
|
2015-08-12 14:50:04 +00:00
|
|
|
unsigned int val;
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
mutex_lock(&data->mutex);
|
2015-03-02 19:03:05 +00:00
|
|
|
for_each_set_bit(bit, indio_dev->active_scan_mask,
|
2014-05-08 21:57:00 +00:00
|
|
|
indio_dev->masklength) {
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(bit),
|
|
|
|
&val, 2);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
data->buffer[i++] = ret;
|
|
|
|
}
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
|
|
|
|
iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
|
2015-05-13 13:30:08 +00:00
|
|
|
pf->timestamp);
|
2014-05-08 21:57:00 +00:00
|
|
|
err:
|
|
|
|
iio_trigger_notify_done(indio_dev->trig);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_trig_try_reen(struct iio_trigger *trig)
|
|
|
|
{
|
|
|
|
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* new data interrupts don't need ack */
|
|
|
|
if (data->dready_trigger_on)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Set latched mode interrupt and clear any latched interrupt */
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
|
|
|
|
BMG160_INT_MODE_LATCH_INT |
|
|
|
|
BMG160_INT_MODE_LATCH_RESET);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev, "Error writing reg_rst_latch\n");
|
2014-05-08 21:57:00 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig,
|
|
|
|
bool state)
|
|
|
|
{
|
|
|
|
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&data->mutex);
|
|
|
|
|
|
|
|
if (!state && data->ev_enable_state && data->motion_trigger_on) {
|
|
|
|
data->motion_trigger_on = false;
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Refer to comment in bmg160_write_event_config for
|
|
|
|
* enable/disable operation order
|
|
|
|
*/
|
|
|
|
ret = bmg160_set_power_state(data, state);
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (data->motion_trig == trig)
|
|
|
|
ret = bmg160_setup_any_motion_interrupt(data, state);
|
|
|
|
else
|
|
|
|
ret = bmg160_setup_new_data_interrupt(data, state);
|
|
|
|
if (ret < 0) {
|
2014-10-11 03:33:25 +00:00
|
|
|
bmg160_set_power_state(data, false);
|
2014-05-08 21:57:00 +00:00
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (data->motion_trig == trig)
|
|
|
|
data->motion_trigger_on = state;
|
|
|
|
else
|
|
|
|
data->dready_trigger_on = state;
|
|
|
|
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct iio_trigger_ops bmg160_trigger_ops = {
|
|
|
|
.set_trigger_state = bmg160_data_rdy_trigger_set_state,
|
|
|
|
.try_reenable = bmg160_trig_try_reen,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
};
|
|
|
|
|
|
|
|
static irqreturn_t bmg160_event_handler(int irq, void *private)
|
|
|
|
{
|
|
|
|
struct iio_dev *indio_dev = private;
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
int ret;
|
|
|
|
int dir;
|
2015-08-12 14:50:04 +00:00
|
|
|
unsigned int val;
|
2014-05-08 21:57:00 +00:00
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev, "Error reading reg_int_status2\n");
|
2014-05-08 21:57:00 +00:00
|
|
|
goto ack_intr_status;
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
if (val & 0x08)
|
2014-05-08 21:57:00 +00:00
|
|
|
dir = IIO_EV_DIR_RISING;
|
|
|
|
else
|
|
|
|
dir = IIO_EV_DIR_FALLING;
|
|
|
|
|
2015-08-12 14:50:04 +00:00
|
|
|
if (val & BMG160_ANY_MOTION_BIT_X)
|
2014-05-08 21:57:00 +00:00
|
|
|
iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
|
|
|
|
0,
|
2014-10-11 03:33:27 +00:00
|
|
|
IIO_MOD_X,
|
|
|
|
IIO_EV_TYPE_ROC,
|
|
|
|
dir),
|
2015-05-13 13:30:08 +00:00
|
|
|
iio_get_time_ns());
|
2015-08-12 14:50:04 +00:00
|
|
|
if (val & BMG160_ANY_MOTION_BIT_Y)
|
2014-10-11 03:33:27 +00:00
|
|
|
iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
|
|
|
|
0,
|
|
|
|
IIO_MOD_Y,
|
|
|
|
IIO_EV_TYPE_ROC,
|
|
|
|
dir),
|
2015-05-13 13:30:08 +00:00
|
|
|
iio_get_time_ns());
|
2015-08-12 14:50:04 +00:00
|
|
|
if (val & BMG160_ANY_MOTION_BIT_Z)
|
2014-10-11 03:33:27 +00:00
|
|
|
iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
|
|
|
|
0,
|
|
|
|
IIO_MOD_Z,
|
2014-05-08 21:57:00 +00:00
|
|
|
IIO_EV_TYPE_ROC,
|
|
|
|
dir),
|
2015-05-13 13:30:08 +00:00
|
|
|
iio_get_time_ns());
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
ack_intr_status:
|
|
|
|
if (!data->dready_trigger_on) {
|
2015-08-12 14:50:04 +00:00
|
|
|
ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
|
|
|
|
BMG160_INT_MODE_LATCH_INT |
|
|
|
|
BMG160_INT_MODE_LATCH_RESET);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret < 0)
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev,
|
2014-05-08 21:57:00 +00:00
|
|
|
"Error writing reg_rst_latch\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private)
|
|
|
|
{
|
|
|
|
struct iio_dev *indio_dev = private;
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
if (data->dready_trigger_on)
|
|
|
|
iio_trigger_poll(data->dready_trig);
|
|
|
|
else if (data->motion_trigger_on)
|
|
|
|
iio_trigger_poll(data->motion_trig);
|
|
|
|
|
|
|
|
if (data->ev_enable_state)
|
|
|
|
return IRQ_WAKE_THREAD;
|
|
|
|
else
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2015-05-13 13:30:09 +00:00
|
|
|
static int bmg160_buffer_preenable(struct iio_dev *indio_dev)
|
|
|
|
{
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
return bmg160_set_power_state(data, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_buffer_postdisable(struct iio_dev *indio_dev)
|
|
|
|
{
|
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
return bmg160_set_power_state(data, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = {
|
|
|
|
.preenable = bmg160_buffer_preenable,
|
|
|
|
.postenable = iio_triggered_buffer_postenable,
|
|
|
|
.predisable = iio_triggered_buffer_predisable,
|
|
|
|
.postdisable = bmg160_buffer_postdisable,
|
|
|
|
};
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
static int bmg160_gpio_probe(struct bmg160_data *data)
|
2014-02-09 11:59:00 +00:00
|
|
|
|
2014-05-08 21:57:00 +00:00
|
|
|
{
|
|
|
|
struct device *dev;
|
|
|
|
struct gpio_desc *gpio;
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
dev = data->dev;
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
/* data ready gpio interrupt pin */
|
2015-02-18 12:47:11 +00:00
|
|
|
gpio = devm_gpiod_get_index(dev, BMG160_GPIO_NAME, 0, GPIOD_IN);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (IS_ERR(gpio)) {
|
|
|
|
dev_err(dev, "acpi gpio get index failed\n");
|
|
|
|
return PTR_ERR(gpio);
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
data->irq = gpiod_to_irq(gpio);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio),
|
|
|
|
data->irq);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
return 0;
|
2014-05-08 21:57:00 +00:00
|
|
|
}
|
|
|
|
|
2014-02-09 11:59:00 +00:00
|
|
|
static const char *bmg160_match_acpi_device(struct device *dev)
|
|
|
|
{
|
|
|
|
const struct acpi_device_id *id;
|
|
|
|
|
|
|
|
id = acpi_match_device(dev->driver->acpi_match_table, dev);
|
|
|
|
if (!id)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return dev_name(dev);
|
|
|
|
}
|
|
|
|
|
2015-08-19 12:12:45 +00:00
|
|
|
int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq,
|
|
|
|
const char *name)
|
2014-05-08 21:57:00 +00:00
|
|
|
{
|
|
|
|
struct bmg160_data *data;
|
|
|
|
struct iio_dev *indio_dev;
|
|
|
|
int ret;
|
|
|
|
|
2015-08-19 12:12:45 +00:00
|
|
|
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
|
2014-05-08 21:57:00 +00:00
|
|
|
if (!indio_dev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
data = iio_priv(indio_dev);
|
2015-08-12 14:50:07 +00:00
|
|
|
dev_set_drvdata(dev, indio_dev);
|
|
|
|
data->dev = dev;
|
2015-08-19 12:12:45 +00:00
|
|
|
data->irq = irq;
|
|
|
|
data->regmap = regmap;
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
ret = bmg160_chip_init(data);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
mutex_init(&data->mutex);
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
if (ACPI_HANDLE(dev))
|
|
|
|
name = bmg160_match_acpi_device(dev);
|
2014-02-09 11:59:00 +00:00
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
indio_dev->dev.parent = dev;
|
2014-05-08 21:57:00 +00:00
|
|
|
indio_dev->channels = bmg160_channels;
|
|
|
|
indio_dev->num_channels = ARRAY_SIZE(bmg160_channels);
|
2014-02-09 11:59:00 +00:00
|
|
|
indio_dev->name = name;
|
2014-05-08 21:57:00 +00:00
|
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
|
|
indio_dev->info = &bmg160_info;
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
if (data->irq <= 0)
|
|
|
|
bmg160_gpio_probe(data);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
if (data->irq > 0) {
|
|
|
|
ret = devm_request_threaded_irq(dev,
|
|
|
|
data->irq,
|
2014-05-08 21:57:00 +00:00
|
|
|
bmg160_data_rdy_trig_poll,
|
|
|
|
bmg160_event_handler,
|
|
|
|
IRQF_TRIGGER_RISING,
|
|
|
|
BMG160_IRQ_NAME,
|
|
|
|
indio_dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
data->dready_trig = devm_iio_trigger_alloc(dev,
|
2014-05-08 21:57:00 +00:00
|
|
|
"%s-dev%d",
|
|
|
|
indio_dev->name,
|
|
|
|
indio_dev->id);
|
|
|
|
if (!data->dready_trig)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
data->motion_trig = devm_iio_trigger_alloc(dev,
|
2014-05-08 21:57:00 +00:00
|
|
|
"%s-any-motion-dev%d",
|
|
|
|
indio_dev->name,
|
|
|
|
indio_dev->id);
|
|
|
|
if (!data->motion_trig)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
data->dready_trig->dev.parent = dev;
|
2014-05-08 21:57:00 +00:00
|
|
|
data->dready_trig->ops = &bmg160_trigger_ops;
|
|
|
|
iio_trigger_set_drvdata(data->dready_trig, indio_dev);
|
|
|
|
ret = iio_trigger_register(data->dready_trig);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
data->motion_trig->dev.parent = dev;
|
2014-05-08 21:57:00 +00:00
|
|
|
data->motion_trig->ops = &bmg160_trigger_ops;
|
|
|
|
iio_trigger_set_drvdata(data->motion_trig, indio_dev);
|
|
|
|
ret = iio_trigger_register(data->motion_trig);
|
|
|
|
if (ret) {
|
|
|
|
data->motion_trig = NULL;
|
|
|
|
goto err_trigger_unregister;
|
|
|
|
}
|
2015-05-13 13:30:09 +00:00
|
|
|
}
|
2014-05-08 21:57:00 +00:00
|
|
|
|
2015-05-13 13:30:09 +00:00
|
|
|
ret = iio_triggered_buffer_setup(indio_dev,
|
|
|
|
iio_pollfunc_store_time,
|
|
|
|
bmg160_trigger_handler,
|
|
|
|
&bmg160_buffer_setup_ops);
|
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:07 +00:00
|
|
|
dev_err(dev,
|
2015-05-13 13:30:09 +00:00
|
|
|
"iio triggered buffer setup failed\n");
|
|
|
|
goto err_trigger_unregister;
|
2014-05-08 21:57:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:07 +00:00
|
|
|
dev_err(dev, "unable to register iio device\n");
|
2014-05-08 21:57:00 +00:00
|
|
|
goto err_buffer_cleanup;
|
|
|
|
}
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
ret = pm_runtime_set_active(dev);
|
2014-05-08 21:57:00 +00:00
|
|
|
if (ret)
|
|
|
|
goto err_iio_unregister;
|
|
|
|
|
2015-08-12 14:50:07 +00:00
|
|
|
pm_runtime_enable(dev);
|
|
|
|
pm_runtime_set_autosuspend_delay(dev,
|
2014-05-08 21:57:00 +00:00
|
|
|
BMG160_AUTO_SUSPEND_DELAY_MS);
|
2015-08-12 14:50:07 +00:00
|
|
|
pm_runtime_use_autosuspend(dev);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_iio_unregister:
|
|
|
|
iio_device_unregister(indio_dev);
|
|
|
|
err_buffer_cleanup:
|
2015-05-13 13:30:09 +00:00
|
|
|
iio_triggered_buffer_cleanup(indio_dev);
|
2014-05-08 21:57:00 +00:00
|
|
|
err_trigger_unregister:
|
|
|
|
if (data->dready_trig)
|
|
|
|
iio_trigger_unregister(data->dready_trig);
|
|
|
|
if (data->motion_trig)
|
|
|
|
iio_trigger_unregister(data->motion_trig);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
2015-08-19 12:12:45 +00:00
|
|
|
EXPORT_SYMBOL_GPL(bmg160_core_probe);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
2015-08-19 12:12:45 +00:00
|
|
|
void bmg160_core_remove(struct device *dev)
|
2014-05-08 21:57:00 +00:00
|
|
|
{
|
2015-08-19 12:12:45 +00:00
|
|
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
2014-05-08 21:57:00 +00:00
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
|
2015-08-19 12:12:45 +00:00
|
|
|
pm_runtime_disable(dev);
|
|
|
|
pm_runtime_set_suspended(dev);
|
|
|
|
pm_runtime_put_noidle(dev);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
iio_device_unregister(indio_dev);
|
2015-05-13 13:30:09 +00:00
|
|
|
iio_triggered_buffer_cleanup(indio_dev);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
if (data->dready_trig) {
|
|
|
|
iio_trigger_unregister(data->dready_trig);
|
|
|
|
iio_trigger_unregister(data->motion_trig);
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_lock(&data->mutex);
|
|
|
|
bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
}
|
2015-08-19 12:12:45 +00:00
|
|
|
EXPORT_SYMBOL_GPL(bmg160_core_remove);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int bmg160_suspend(struct device *dev)
|
|
|
|
{
|
2015-08-12 14:50:06 +00:00
|
|
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
2014-05-08 21:57:00 +00:00
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
mutex_lock(&data->mutex);
|
|
|
|
bmg160_set_mode(data, BMG160_MODE_SUSPEND);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_resume(struct device *dev)
|
|
|
|
{
|
2015-08-12 14:50:06 +00:00
|
|
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
2014-05-08 21:57:00 +00:00
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
|
|
|
|
mutex_lock(&data->mutex);
|
|
|
|
if (data->dready_trigger_on || data->motion_trigger_on ||
|
|
|
|
data->ev_enable_state)
|
|
|
|
bmg160_set_mode(data, BMG160_MODE_NORMAL);
|
|
|
|
mutex_unlock(&data->mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-12-04 00:08:13 +00:00
|
|
|
#ifdef CONFIG_PM
|
2014-05-08 21:57:00 +00:00
|
|
|
static int bmg160_runtime_suspend(struct device *dev)
|
|
|
|
{
|
2015-08-12 14:50:06 +00:00
|
|
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
2014-05-08 21:57:00 +00:00
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
2014-10-11 03:33:25 +00:00
|
|
|
int ret;
|
2014-05-08 21:57:00 +00:00
|
|
|
|
2014-10-11 03:33:25 +00:00
|
|
|
ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND);
|
|
|
|
if (ret < 0) {
|
2015-08-12 14:50:05 +00:00
|
|
|
dev_err(data->dev, "set mode failed\n");
|
2014-10-11 03:33:25 +00:00
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2014-05-08 21:57:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int bmg160_runtime_resume(struct device *dev)
|
|
|
|
{
|
2015-08-12 14:50:06 +00:00
|
|
|
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
2014-05-08 21:57:00 +00:00
|
|
|
struct bmg160_data *data = iio_priv(indio_dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2015-08-19 12:12:45 +00:00
|
|
|
const struct dev_pm_ops bmg160_pm_ops = {
|
2014-05-08 21:57:00 +00:00
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume)
|
|
|
|
SET_RUNTIME_PM_OPS(bmg160_runtime_suspend,
|
|
|
|
bmg160_runtime_resume, NULL)
|
|
|
|
};
|
2015-08-19 12:12:45 +00:00
|
|
|
EXPORT_SYMBOL_GPL(bmg160_pm_ops);
|
2014-05-08 21:57:00 +00:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DESCRIPTION("BMG160 Gyro driver");
|