linux/include/dt-bindings/clock/stih415-clks.h

/*
 * This header provides constants clk index STMicroelectronics
 * STiH415 SoC.
 */
#ifndef _CLK_STIH415
#define _CLK_STIH415

/* CLOCKGEN A0 */
#define CLK_ICN_REG		0
#define CLK_ETH1_PHY		4

/* CLOCKGEN A1 */
#define CLK_ICN_IF_2		0
#define CLK_GMAC0_PHY		3

#endif
ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12 Patch adds DT entries for clockgen A0/1/10/11/12 Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> 2014-05-20 13:22:00 +00:00			`/*`
			`* This header provides constants clk index STMicroelectronics`
			`* STiH415 SoC.`
			`*/`
			`#ifndef _CLK_STIH415`
			`#define _CLK_STIH415`

			`/* CLOCKGEN A0 */`
			`#define CLK_ICN_REG 0`
			`#define CLK_ETH1_PHY 4`

			`/* CLOCKGEN A1 */`
ARM: STi: DT: Properly define sti-ethclk & stmmaceth for stih415/6 This patch fixes two problems: - 1) The device tree isn't currently providing sti-ethclk which is required by the dwmac glue code to correctly configure the ethernet PHY clock speed. This means depending on what the bootloader/jtag has configured this clock to, and what switch/hub the board is plugged into you most likely will NOT successfully negotiate a ethernet link. 2) The stmmaceth clock was associated with the wrong clock. It was referencing the PHY clock rather than the interconnect clock which clocks the IP. This patch also brings us closer to not having to boot the upstream kernel with the clk_ignore_unused parameter. Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> 2014-06-16 09:23:00 +00:00			`#define CLK_ICN_IF_2 0`
ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12 Patch adds DT entries for clockgen A0/1/10/11/12 Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> 2014-05-20 13:22:00 +00:00			`#define CLK_GMAC0_PHY 3`

			`#endif`