2012-03-05 11:49:26 +00:00
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/*
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2016-04-27 16:47:00 +00:00
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* Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
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2012-03-05 11:49:26 +00:00
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASSEMBLY__
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#error "Only include this from assembly code"
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#endif
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2015-02-20 13:53:13 +00:00
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#ifndef __ASM_ASSEMBLER_H
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#define __ASM_ASSEMBLER_H
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2016-04-27 16:47:00 +00:00
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-hwdef.h>
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2012-03-05 11:49:26 +00:00
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#include <asm/ptrace.h>
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arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 18:04:06 +00:00
|
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#include <asm/thread_info.h>
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2012-03-05 11:49:26 +00:00
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/*
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* Enable and disable interrupts.
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*/
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.macro disable_irq
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msr daifset, #2
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.endm
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.macro enable_irq
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msr daifclr, #2
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.endm
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/*
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* Enable and disable debug exceptions.
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*/
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.macro disable_dbg
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msr daifset, #8
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.endm
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.macro enable_dbg
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msr daifclr, #8
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.endm
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arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 18:04:06 +00:00
|
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.macro disable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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2012-03-05 11:49:26 +00:00
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mrs \tmp, mdscr_el1
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bic \tmp, \tmp, #1
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msr mdscr_el1, \tmp
|
arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 18:04:06 +00:00
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isb // Synchronise with enable_dbg
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9990:
|
2012-03-05 11:49:26 +00:00
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|
.endm
|
|
|
|
|
|
arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 18:04:06 +00:00
|
|
|
.macro enable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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disable_dbg
|
2012-03-05 11:49:26 +00:00
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|
mrs \tmp, mdscr_el1
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orr \tmp, \tmp, #1
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msr mdscr_el1, \tmp
|
arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 18:04:06 +00:00
|
|
|
9990:
|
2012-03-05 11:49:26 +00:00
|
|
|
.endm
|
|
|
|
|
|
arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-04-29 18:04:06 +00:00
|
|
|
/*
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|
|
|
|
* Enable both debug exceptions and interrupts. This is likely to be
|
|
|
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|
* faster than two daifclr operations, since writes to this register
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* are self-synchronising.
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|
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|
*/
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.macro enable_dbg_and_irq
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msr daifclr, #(8 | 2)
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2012-03-05 11:49:26 +00:00
|
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|
.endm
|
|
|
|
|
|
|
|
|
|
/*
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|
|
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* SMP data memory barrier
|
|
|
|
|
*/
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|
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.macro smp_dmb, opt
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|
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|
dmb \opt
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|
|
.endm
|
|
|
|
|
|
2016-01-01 14:02:12 +00:00
|
|
|
/*
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|
|
* Emit an entry into the exception table
|
|
|
|
|
*/
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|
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|
|
.macro _asm_extable, from, to
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|
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|
.pushsection __ex_table, "a"
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|
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|
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.align 3
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.long (\from - .), (\to - .)
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.popsection
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|
.endm
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|
2012-03-05 11:49:26 +00:00
|
|
|
#define USER(l, x...) \
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|
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|
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9999: x; \
|
2016-01-01 14:02:12 +00:00
|
|
|
_asm_extable 9999b, l
|
2012-03-05 11:49:26 +00:00
|
|
|
|
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|
|
/*
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|
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* Register aliases.
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*/
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|
lr .req x30 // link register
|
2012-10-19 16:37:35 +00:00
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|
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|
/*
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* Vector entry
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*/
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.macro ventry label
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.align 7
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b \label
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|
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|
|
.endm
|
2013-10-11 13:52:15 +00:00
|
|
|
|
|
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|
|
/*
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* Select code when configured for BE.
|
|
|
|
|
*/
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|
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|
#ifdef CONFIG_CPU_BIG_ENDIAN
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|
|
|
|
#define CPU_BE(code...) code
|
|
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|
#else
|
|
|
|
|
#define CPU_BE(code...)
|
|
|
|
|
#endif
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|
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|
|
/*
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* Select code when configured for LE.
|
|
|
|
|
*/
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|
#ifdef CONFIG_CPU_BIG_ENDIAN
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|
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#define CPU_LE(code...)
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|
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|
|
#else
|
|
|
|
|
#define CPU_LE(code...) code
|
|
|
|
|
#endif
|
|
|
|
|
|
2013-10-11 13:52:13 +00:00
|
|
|
/*
|
|
|
|
|
* Define a macro that constructs a 64-bit value by concatenating two
|
|
|
|
|
* 32-bit registers. Note that on big endian systems the order of the
|
|
|
|
|
* registers is swapped.
|
|
|
|
|
*/
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|
|
|
|
#ifndef CONFIG_CPU_BIG_ENDIAN
|
|
|
|
|
.macro regs_to_64, rd, lbits, hbits
|
|
|
|
|
#else
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|
|
|
|
.macro regs_to_64, rd, hbits, lbits
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|
#endif
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|
|
|
|
orr \rd, \lbits, \hbits, lsl #32
|
|
|
|
|
.endm
|
2015-02-20 13:53:13 +00:00
|
|
|
|
2015-03-04 18:45:38 +00:00
|
|
|
/*
|
|
|
|
|
* Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
|
|
|
|
|
* <symbol> is within the range +/- 4 GB of the PC.
|
|
|
|
|
*/
|
|
|
|
|
/*
|
|
|
|
|
* @dst: destination register (64 bit wide)
|
|
|
|
|
* @sym: name of the symbol
|
|
|
|
|
* @tmp: optional scratch register to be used if <dst> == sp, which
|
|
|
|
|
* is not allowed in an adrp instruction
|
|
|
|
|
*/
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|
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|
|
.macro adr_l, dst, sym, tmp=
|
|
|
|
|
.ifb \tmp
|
|
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|
adrp \dst, \sym
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|
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|
|
add \dst, \dst, :lo12:\sym
|
|
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|
|
.else
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adrp \tmp, \sym
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add \dst, \tmp, :lo12:\sym
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|
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.endif
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* @dst: destination register (32 or 64 bit wide)
|
|
|
|
|
* @sym: name of the symbol
|
|
|
|
|
* @tmp: optional 64-bit scratch register to be used if <dst> is a
|
|
|
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|
* 32-bit wide register, in which case it cannot be used to hold
|
|
|
|
|
* the address
|
|
|
|
|
*/
|
|
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|
|
.macro ldr_l, dst, sym, tmp=
|
|
|
|
|
.ifb \tmp
|
|
|
|
|
adrp \dst, \sym
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|
|
|
|
ldr \dst, [\dst, :lo12:\sym]
|
|
|
|
|
.else
|
|
|
|
|
adrp \tmp, \sym
|
|
|
|
|
ldr \dst, [\tmp, :lo12:\sym]
|
|
|
|
|
.endif
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* @src: source register (32 or 64 bit wide)
|
|
|
|
|
* @sym: name of the symbol
|
|
|
|
|
* @tmp: mandatory 64-bit scratch register to calculate the address
|
|
|
|
|
* while <src> needs to be preserved.
|
|
|
|
|
*/
|
|
|
|
|
.macro str_l, src, sym, tmp
|
|
|
|
|
adrp \tmp, \sym
|
|
|
|
|
str \src, [\tmp, :lo12:\sym]
|
|
|
|
|
.endm
|
|
|
|
|
|
2015-12-10 10:22:39 +00:00
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/*
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* @sym: The name of the per-cpu variable
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* @reg: Result of per_cpu(sym, smp_processor_id())
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* @tmp: scratch register
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*/
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.macro this_cpu_ptr, sym, reg, tmp
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adr_l \reg, \sym
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mrs \tmp, tpidr_el1
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add \reg, \reg, \tmp
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.endm
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2016-04-27 16:47:00 +00:00
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/*
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* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
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*/
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.macro vma_vm_mm, rd, rn
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ldr \rd, [\rn, #VMA_VM_MM]
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.endm
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/*
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* mmid - get context id from mm pointer (mm->context.id)
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*/
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.macro mmid, rd, rn
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ldr \rd, [\rn, #MM_CONTEXT_ID]
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.endm
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/*
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* dcache_line_size - get the minimum D-cache line size from the CTR register.
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*/
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.macro dcache_line_size, reg, tmp
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mrs \tmp, ctr_el0 // read CTR
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ubfm \tmp, \tmp, #16, #19 // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* icache_line_size - get the minimum I-cache line size from the CTR register.
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*/
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.macro icache_line_size, reg, tmp
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mrs \tmp, ctr_el0 // read CTR
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and \tmp, \tmp, #0xf // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
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*/
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.macro tcr_set_idmap_t0sz, valreg, tmpreg
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#ifndef CONFIG_ARM64_VA_BITS_48
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ldr_l \tmpreg, idmap_t0sz
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bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
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#endif
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.endm
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/*
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* Macro to perform a data cache maintenance for the interval
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* [kaddr, kaddr + size)
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*
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* op: operation passed to dc instruction
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* domain: domain used in dsb instruciton
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* kaddr: starting virtual address of the region
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* size: size of the region
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* Corrupts: kaddr, size, tmp1, tmp2
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*/
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.macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
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dcache_line_size \tmp1, \tmp2
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add \size, \kaddr, \size
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sub \tmp2, \tmp1, #1
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bic \kaddr, \kaddr, \tmp2
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9998: dc \op, \kaddr
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add \kaddr, \kaddr, \tmp1
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cmp \kaddr, \size
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b.lo 9998b
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dsb \domain
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.endm
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/*
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* reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
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*/
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.macro reset_pmuserenr_el0, tmpreg
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mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
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sbfx \tmpreg, \tmpreg, #8, #4
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cmp \tmpreg, #1 // Skip if no PMU present
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b.lt 9000f
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msr pmuserenr_el0, xzr // Disable PMU access from EL0
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9000:
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.endm
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2015-10-08 19:02:03 +00:00
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/*
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* Annotate a function as position independent, i.e., safe to be called before
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* the kernel virtual mapping is activated.
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*/
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#define ENDPIPROC(x) \
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.globl __pi_##x; \
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.type __pi_##x, %function; \
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.set __pi_##x, x; \
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.size __pi_##x, . - x; \
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ENDPROC(x)
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2015-12-26 12:48:02 +00:00
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/*
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* Emit a 64-bit absolute little endian symbol reference in a way that
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* ensures that it will be resolved at build time, even when building a
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* PIE binary. This requires cooperation from the linker script, which
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* must emit the lo32/hi32 halves individually.
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*/
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.macro le64sym, sym
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.long \sym\()_lo32
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.long \sym\()_hi32
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.endm
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2016-04-18 15:09:44 +00:00
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/*
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* mov_q - move an immediate constant into a 64-bit register using
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* between 2 and 4 movz/movk instructions (depending on the
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* magnitude and sign of the operand)
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*/
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.macro mov_q, reg, val
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.if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
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movz \reg, :abs_g1_s:\val
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.else
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.if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
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movz \reg, :abs_g2_s:\val
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.else
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movz \reg, :abs_g3:\val
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movk \reg, :abs_g2_nc:\val
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.endif
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movk \reg, :abs_g1_nc:\val
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.endif
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movk \reg, :abs_g0_nc:\val
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.endm
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2015-02-20 13:53:13 +00:00
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#endif /* __ASM_ASSEMBLER_H */
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