License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-16 22:20:36 +00:00
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/*
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* Purpose: PCI Express Port Bus Driver
|
2016-08-22 21:59:44 +00:00
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* Author: Tom Nguyen <tom.l.nguyen@intel.com>
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2005-04-16 22:20:36 +00:00
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*
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* Copyright (C) 2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/pm.h>
|
2012-06-23 02:23:49 +00:00
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#include <linux/pm_runtime.h>
|
2005-04-16 22:20:36 +00:00
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#include <linux/init.h>
|
2006-07-31 07:26:16 +00:00
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#include <linux/aer.h>
|
2010-02-17 22:40:07 +00:00
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#include <linux/dmi.h>
|
2005-04-16 22:20:36 +00:00
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2016-10-28 08:52:06 +00:00
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#include "../pci.h"
|
2005-04-16 22:20:36 +00:00
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#include "portdrv.h"
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|
2010-08-20 23:51:44 +00:00
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|
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/* If this switch is set, PCIe port native services should not be enabled. */
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|
bool pcie_ports_disabled;
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|
PCI: PCIe: Ask BIOS for control of all native services at once
After commit 852972acff8f10f3a15679be2059bb94916cba5d (ACPI: Disable
ASPM if the platform won't provide _OSC control for PCIe) control of
the PCIe Capability Structure is unconditionally requested by
acpi_pci_root_add(), which in principle may cause problems to
happen in two ways. First, the BIOS may refuse to give control of
the PCIe Capability Structure if it is not asked for any of the
_OSC features depending on it at the same time. Second, the BIOS may
assume that control of the _OSC features depending on the PCIe
Capability Structure will be requested in the future and may behave
incorrectly if that doesn't happen. For this reason, control of
the PCIe Capability Structure should always be requested along with
control of any other _OSC features that may depend on it (ie. PCIe
native PME, PCIe native hot-plug, PCIe AER).
Rework the PCIe port driver so that (1) it checks which native PCIe
port services can be enabled, according to the BIOS, and (2) it
requests control of all these services simultaneously. In
particular, this causes pcie_portdrv_probe() to fail if the BIOS
refuses to grant control of the PCIe Capability Structure, which
means that no native PCIe port services can be enabled for the PCIe
Root Complex the given port belongs to. If that happens, ASPM is
disabled to avoid problems with mishandling it by the part of the
PCIe hierarchy for which control of the PCIe Capability Structure
has not been received.
Make it possible to override this behavior using 'pcie_ports=native'
(use the PCIe native services regardless of the BIOS response to the
control request), or 'pcie_ports=compat' (do not use the PCIe native
services at all).
Accordingly, rework the existing PCIe port service drivers so that
they don't request control of the services directly.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-08-21 20:02:38 +00:00
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/*
|
2018-03-09 17:21:30 +00:00
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* If the user specified "pcie_ports=native", use the PCIe services regardless
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* of whether the platform has given us permission. On ACPI systems, this
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|
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* means we ignore _OSC.
|
PCI: PCIe: Ask BIOS for control of all native services at once
After commit 852972acff8f10f3a15679be2059bb94916cba5d (ACPI: Disable
ASPM if the platform won't provide _OSC control for PCIe) control of
the PCIe Capability Structure is unconditionally requested by
acpi_pci_root_add(), which in principle may cause problems to
happen in two ways. First, the BIOS may refuse to give control of
the PCIe Capability Structure if it is not asked for any of the
_OSC features depending on it at the same time. Second, the BIOS may
assume that control of the _OSC features depending on the PCIe
Capability Structure will be requested in the future and may behave
incorrectly if that doesn't happen. For this reason, control of
the PCIe Capability Structure should always be requested along with
control of any other _OSC features that may depend on it (ie. PCIe
native PME, PCIe native hot-plug, PCIe AER).
Rework the PCIe port driver so that (1) it checks which native PCIe
port services can be enabled, according to the BIOS, and (2) it
requests control of all these services simultaneously. In
particular, this causes pcie_portdrv_probe() to fail if the BIOS
refuses to grant control of the PCIe Capability Structure, which
means that no native PCIe port services can be enabled for the PCIe
Root Complex the given port belongs to. If that happens, ASPM is
disabled to avoid problems with mishandling it by the part of the
PCIe hierarchy for which control of the PCIe Capability Structure
has not been received.
Make it possible to override this behavior using 'pcie_ports=native'
(use the PCIe native services regardless of the BIOS response to the
control request), or 'pcie_ports=compat' (do not use the PCIe native
services at all).
Accordingly, rework the existing PCIe port service drivers so that
they don't request control of the services directly.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-08-21 20:02:38 +00:00
|
|
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*/
|
2018-03-09 17:21:30 +00:00
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bool pcie_ports_native;
|
PCI: PCIe: Ask BIOS for control of all native services at once
After commit 852972acff8f10f3a15679be2059bb94916cba5d (ACPI: Disable
ASPM if the platform won't provide _OSC control for PCIe) control of
the PCIe Capability Structure is unconditionally requested by
acpi_pci_root_add(), which in principle may cause problems to
happen in two ways. First, the BIOS may refuse to give control of
the PCIe Capability Structure if it is not asked for any of the
_OSC features depending on it at the same time. Second, the BIOS may
assume that control of the _OSC features depending on the PCIe
Capability Structure will be requested in the future and may behave
incorrectly if that doesn't happen. For this reason, control of
the PCIe Capability Structure should always be requested along with
control of any other _OSC features that may depend on it (ie. PCIe
native PME, PCIe native hot-plug, PCIe AER).
Rework the PCIe port driver so that (1) it checks which native PCIe
port services can be enabled, according to the BIOS, and (2) it
requests control of all these services simultaneously. In
particular, this causes pcie_portdrv_probe() to fail if the BIOS
refuses to grant control of the PCIe Capability Structure, which
means that no native PCIe port services can be enabled for the PCIe
Root Complex the given port belongs to. If that happens, ASPM is
disabled to avoid problems with mishandling it by the part of the
PCIe hierarchy for which control of the PCIe Capability Structure
has not been received.
Make it possible to override this behavior using 'pcie_ports=native'
(use the PCIe native services regardless of the BIOS response to the
control request), or 'pcie_ports=compat' (do not use the PCIe native
services at all).
Accordingly, rework the existing PCIe port service drivers so that
they don't request control of the services directly.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-08-21 20:02:38 +00:00
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PCI/DPC: Add "pcie_ports=dpc-native" to allow DPC without AER control
Prior to eed85ff4c0da7 ("PCI/DPC: Enable DPC only if AER is available"),
Linux handled DPC events regardless of whether firmware had granted it
ownership of AER or DPC, e.g., via _OSC.
PCIe r5.0, sec 6.2.10, recommends that the OS link control of DPC to
control of AER, so after eed85ff4c0da7, Linux handles DPC events only if it
has control of AER.
On platforms that do not grant OS control of AER via _OSC, Linux DPC
handling worked before eed85ff4c0da7 but not after.
To make Linux DPC handling work on those platforms the same way they did
before, add a "pcie_ports=dpc-native" kernel parameter that makes Linux
handle DPC events regardless of whether it has control of AER.
[bhelgaas: commit log, move pcie_ports_dpc_native to drivers/pci/]
Link: https://lore.kernel.org/r/20191023192205.97024-1-olof@lixom.net
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-10-23 19:22:05 +00:00
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/*
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* If the user specified "pcie_ports=dpc-native", use the Linux DPC PCIe
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* service even if the platform hasn't given us permission.
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*/
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bool pcie_ports_dpc_native;
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2010-08-20 23:51:44 +00:00
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static int __init pcie_port_setup(char *str)
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{
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2018-03-09 17:21:30 +00:00
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if (!strncmp(str, "compat", 6))
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2010-08-20 23:51:44 +00:00
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pcie_ports_disabled = true;
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2018-03-09 17:21:30 +00:00
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else if (!strncmp(str, "native", 6))
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pcie_ports_native = true;
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PCI/DPC: Add "pcie_ports=dpc-native" to allow DPC without AER control
Prior to eed85ff4c0da7 ("PCI/DPC: Enable DPC only if AER is available"),
Linux handled DPC events regardless of whether firmware had granted it
ownership of AER or DPC, e.g., via _OSC.
PCIe r5.0, sec 6.2.10, recommends that the OS link control of DPC to
control of AER, so after eed85ff4c0da7, Linux handles DPC events only if it
has control of AER.
On platforms that do not grant OS control of AER via _OSC, Linux DPC
handling worked before eed85ff4c0da7 but not after.
To make Linux DPC handling work on those platforms the same way they did
before, add a "pcie_ports=dpc-native" kernel parameter that makes Linux
handle DPC events regardless of whether it has control of AER.
[bhelgaas: commit log, move pcie_ports_dpc_native to drivers/pci/]
Link: https://lore.kernel.org/r/20191023192205.97024-1-olof@lixom.net
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2019-10-23 19:22:05 +00:00
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else if (!strncmp(str, "dpc-native", 10))
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pcie_ports_dpc_native = true;
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2010-08-20 23:51:44 +00:00
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return 1;
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}
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__setup("pcie_ports=", pcie_port_setup);
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2005-04-16 22:20:36 +00:00
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/* global data */
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2006-09-28 06:35:59 +00:00
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#ifdef CONFIG_PM
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2016-06-02 08:17:15 +00:00
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static int pcie_port_runtime_suspend(struct device *dev)
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{
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2018-09-27 21:41:48 +00:00
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if (!to_pci_dev(dev)->bridge_d3)
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return -EBUSY;
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2016-06-02 08:17:15 +00:00
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2018-09-27 21:41:48 +00:00
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return pcie_port_device_runtime_suspend(dev);
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2016-06-02 08:17:15 +00:00
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}
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static int pcie_port_runtime_idle(struct device *dev)
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{
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/*
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* Assume the PCI core has set bridge_d3 whenever it thinks the port
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* should be good to go to D3. Everything else, including moving
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* the port to D3, is handled by the PCI core.
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*/
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return to_pci_dev(dev)->bridge_d3 ? 0 : -EBUSY;
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}
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2009-12-15 02:00:08 +00:00
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static const struct dev_pm_ops pcie_portdrv_pm_ops = {
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2009-02-15 21:32:48 +00:00
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.suspend = pcie_port_device_suspend,
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2018-07-19 22:27:53 +00:00
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.resume_noirq = pcie_port_device_resume_noirq,
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2009-02-15 21:32:48 +00:00
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.resume = pcie_port_device_resume,
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.freeze = pcie_port_device_suspend,
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.thaw = pcie_port_device_resume,
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.poweroff = pcie_port_device_suspend,
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2018-07-19 22:27:53 +00:00
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.restore_noirq = pcie_port_device_resume_noirq,
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2009-02-15 21:32:48 +00:00
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.restore = pcie_port_device_resume,
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2016-06-02 08:17:15 +00:00
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.runtime_suspend = pcie_port_runtime_suspend,
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2018-09-27 21:41:48 +00:00
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.runtime_resume = pcie_port_device_runtime_resume,
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2016-06-02 08:17:15 +00:00
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.runtime_idle = pcie_port_runtime_idle,
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2009-02-15 21:32:48 +00:00
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};
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2006-07-31 07:26:16 +00:00
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2009-02-15 21:32:48 +00:00
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#define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops)
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2008-12-27 15:28:58 +00:00
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2009-02-15 21:32:48 +00:00
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#else /* !PM */
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#define PCIE_PORTDRV_PM_OPS NULL
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#endif /* !PM */
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2006-07-31 07:26:16 +00:00
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2005-04-16 22:20:36 +00:00
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/*
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* pcie_portdrv_probe - Probe PCI-Express port devices
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* @dev: PCI-Express port device being probed
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*
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2009-12-15 02:38:04 +00:00
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* If detected invokes the pcie_port_device_register() method for
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2005-04-16 22:20:36 +00:00
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* this port device.
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*
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*/
|
2012-11-21 20:35:00 +00:00
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static int pcie_portdrv_probe(struct pci_dev *dev,
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2009-11-25 12:00:53 +00:00
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const struct pci_device_id *id)
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2005-04-16 22:20:36 +00:00
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{
|
2020-11-21 00:10:27 +00:00
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int type = pci_pcie_type(dev);
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2009-11-25 12:00:53 +00:00
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int status;
|
2005-04-16 22:20:36 +00:00
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2009-11-25 12:00:53 +00:00
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if (!pci_is_pcie(dev) ||
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2020-11-21 00:10:27 +00:00
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((type != PCI_EXP_TYPE_ROOT_PORT) &&
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(type != PCI_EXP_TYPE_UPSTREAM) &&
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(type != PCI_EXP_TYPE_DOWNSTREAM) &&
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(type != PCI_EXP_TYPE_RC_EC)))
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2009-11-25 12:00:53 +00:00
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return -ENODEV;
|
2005-04-16 22:20:36 +00:00
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2020-11-21 00:10:32 +00:00
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if (type == PCI_EXP_TYPE_RC_EC)
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pcie_link_rcec(dev);
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2009-01-13 13:42:01 +00:00
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status = pcie_port_device_register(dev);
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if (status)
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return status;
|
2005-04-16 22:20:36 +00:00
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2009-01-13 13:43:07 +00:00
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pci_save_state(dev);
|
2016-06-02 08:17:15 +00:00
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2020-04-18 16:53:01 +00:00
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dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE |
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2018-09-27 21:41:47 +00:00
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DPM_FLAG_SMART_SUSPEND);
|
2018-01-03 00:38:27 +00:00
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2016-10-28 08:52:06 +00:00
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if (pci_bridge_d3_possible(dev)) {
|
2016-06-02 08:17:15 +00:00
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/*
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* Keep the port resumed 100ms to make sure things like
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* config space accesses from userspace (lspci) will not
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* cause the port to repeatedly suspend and resume.
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*/
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|
|
pm_runtime_set_autosuspend_delay(&dev->dev, 100);
|
|
|
|
pm_runtime_use_autosuspend(&dev->dev);
|
|
|
|
pm_runtime_mark_last_busy(&dev->dev);
|
|
|
|
pm_runtime_put_autosuspend(&dev->dev);
|
|
|
|
pm_runtime_allow(&dev->dev);
|
|
|
|
}
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-12-15 02:38:04 +00:00
|
|
|
static void pcie_portdrv_remove(struct pci_dev *dev)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2016-10-28 08:52:06 +00:00
|
|
|
if (pci_bridge_d3_possible(dev)) {
|
2016-06-02 08:17:15 +00:00
|
|
|
pm_runtime_forbid(&dev->dev);
|
|
|
|
pm_runtime_get_noresume(&dev->dev);
|
|
|
|
pm_runtime_dont_use_autosuspend(&dev->dev);
|
|
|
|
}
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
pcie_port_device_remove(dev);
|
|
|
|
}
|
|
|
|
|
2006-07-31 07:26:16 +00:00
|
|
|
static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,
|
2020-07-02 16:26:49 +00:00
|
|
|
pci_channel_state_t error)
|
2006-07-06 14:05:51 +00:00
|
|
|
{
|
2021-01-04 23:03:00 +00:00
|
|
|
if (error == pci_channel_io_frozen)
|
|
|
|
return PCI_ERS_RESULT_NEED_RESET;
|
2017-06-19 18:04:58 +00:00
|
|
|
return PCI_ERS_RESULT_CAN_RECOVER;
|
2006-07-06 14:05:51 +00:00
|
|
|
}
|
|
|
|
|
2018-09-20 16:27:07 +00:00
|
|
|
static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev)
|
|
|
|
{
|
PCI: pciehp: Ignore Link Down/Up caused by error-induced Hot Reset
Stuart Hayes reports that an error handled by DPC at a Root Port results
in pciehp gratuitously bringing down a subordinate hotplug port:
RP -- UP -- DP -- UP -- DP (hotplug) -- EP
pciehp brings the slot down because the Link to the Endpoint goes down.
That is caused by a Hot Reset being propagated as a result of DPC.
Per PCIe Base Spec 5.0, section 6.6.1 "Conventional Reset":
For a Switch, the following must cause a hot reset to be sent on all
Downstream Ports: [...]
* The Data Link Layer of the Upstream Port reporting DL_Down status.
In Switches that support Link speeds greater than 5.0 GT/s, the
Upstream Port must direct the LTSSM of each Downstream Port to the
Hot Reset state, but not hold the LTSSMs in that state. This permits
each Downstream Port to begin Link training immediately after its
hot reset completes. This behavior is recommended for all Switches.
* Receiving a hot reset on the Upstream Port.
Once DPC recovers, pcie_do_recovery() walks down the hierarchy and
invokes pcie_portdrv_slot_reset() to restore each port's config space.
At that point, a hotplug interrupt is signaled per PCIe Base Spec r5.0,
section 6.7.3.4 "Software Notification of Hot-Plug Events":
If the Port is enabled for edge-triggered interrupt signaling using
MSI or MSI-X, an interrupt message must be sent every time the logical
AND of the following conditions transitions from FALSE to TRUE: [...]
* The Hot-Plug Interrupt Enable bit in the Slot Control register is
set to 1b.
* At least one hot-plug event status bit in the Slot Status register
and its associated enable bit in the Slot Control register are both
set to 1b.
Prevent pciehp from gratuitously bringing down the slot by clearing the
error-induced Data Link Layer State Changed event before restoring
config space. Afterwards, check whether the link has unexpectedly
failed to retrain and synthesize a DLLSC event if so.
Allow each pcie_port_service_driver (one of them being pciehp) to define
a slot_reset callback and re-use the existing pm_iter() function to
iterate over the callbacks.
Thereby, the Endpoint driver remains bound throughout error recovery and
may restore the device to working state.
Surprise removal during error recovery is detected through a Presence
Detect Changed event. The hotplug port is expected to not signal that
event as a result of a Hot Reset.
The issue isn't DPC-specific, it also occurs when an error is handled by
AER through aer_root_reset(). So while the issue was noticed only now,
it's been around since 2006 when AER support was first introduced.
[bhelgaas: drop PCI_ERROR_RECOVERY Kconfig, split pm_iter() rename to
preparatory patch]
Link: https://lore.kernel.org/linux-pci/08c046b0-c9f2-3489-eeef-7e7aca435bb9@gmail.com/
Fixes: 6c2b374d7485 ("PCI-Express AER implemetation: AER core and aerdriver")
Link: https://lore.kernel.org/r/251f4edcc04c14f873ff1c967bc686169cd07d2d.1627638184.git.lukas@wunner.de
Reported-by: Stuart Hayes <stuart.w.hayes@gmail.com>
Tested-by: Stuart Hayes <stuart.w.hayes@gmail.com>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org # v2.6.19+: ba952824e6c1: PCI/portdrv: Report reset for frozen channel
Cc: Keith Busch <kbusch@kernel.org>
2021-07-31 12:39:01 +00:00
|
|
|
size_t off = offsetof(struct pcie_port_service_driver, slot_reset);
|
|
|
|
device_for_each_child(&dev->dev, &off, pcie_port_device_iter);
|
|
|
|
|
2018-09-20 16:27:07 +00:00
|
|
|
pci_restore_state(dev);
|
|
|
|
pci_save_state(dev);
|
|
|
|
return PCI_ERS_RESULT_RECOVERED;
|
|
|
|
}
|
|
|
|
|
2006-07-31 07:26:16 +00:00
|
|
|
static pci_ers_result_t pcie_portdrv_mmio_enabled(struct pci_dev *dev)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2017-06-19 18:04:58 +00:00
|
|
|
return PCI_ERS_RESULT_RECOVERED;
|
2006-07-31 07:26:16 +00:00
|
|
|
}
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* LINUX Device Driver Model
|
|
|
|
*/
|
2019-02-15 19:49:18 +00:00
|
|
|
static const struct pci_device_id port_pci_ids[] = {
|
2005-04-16 22:20:36 +00:00
|
|
|
/* handle any PCI-Express port */
|
2022-02-14 11:41:08 +00:00
|
|
|
{ PCI_DEVICE_CLASS(PCI_CLASS_BRIDGE_PCI_NORMAL, ~0) },
|
2019-02-14 05:21:17 +00:00
|
|
|
/* subtractive decode PCI-to-PCI bridge, class type is 060401h */
|
2022-02-14 11:41:08 +00:00
|
|
|
{ PCI_DEVICE_CLASS(PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE, ~0) },
|
2020-11-21 00:10:23 +00:00
|
|
|
/* handle any Root Complex Event Collector */
|
|
|
|
{ PCI_DEVICE_CLASS(((PCI_CLASS_SYSTEM_RCEC << 8) | 0x00), ~0) },
|
2019-02-15 19:49:18 +00:00
|
|
|
{ },
|
2005-04-16 22:20:36 +00:00
|
|
|
};
|
|
|
|
|
2012-09-07 16:33:14 +00:00
|
|
|
static const struct pci_error_handlers pcie_portdrv_err_handler = {
|
|
|
|
.error_detected = pcie_portdrv_error_detected,
|
2018-09-20 16:27:07 +00:00
|
|
|
.slot_reset = pcie_portdrv_slot_reset,
|
2012-09-07 16:33:14 +00:00
|
|
|
.mmio_enabled = pcie_portdrv_mmio_enabled,
|
2006-07-31 07:26:16 +00:00
|
|
|
};
|
|
|
|
|
2007-02-27 09:19:17 +00:00
|
|
|
static struct pci_driver pcie_portdriver = {
|
2009-10-05 22:47:34 +00:00
|
|
|
.name = "pcieport",
|
2005-04-16 22:20:36 +00:00
|
|
|
.id_table = &port_pci_ids[0],
|
|
|
|
|
|
|
|
.probe = pcie_portdrv_probe,
|
|
|
|
.remove = pcie_portdrv_remove,
|
2017-10-25 19:01:02 +00:00
|
|
|
.shutdown = pcie_portdrv_remove,
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2013-11-14 18:28:18 +00:00
|
|
|
.err_handler = &pcie_portdrv_err_handler,
|
2009-02-15 21:32:48 +00:00
|
|
|
|
2022-04-18 00:49:55 +00:00
|
|
|
.driver_managed_dma = true,
|
|
|
|
|
2013-11-14 18:28:18 +00:00
|
|
|
.driver.pm = PCIE_PORTDRV_PM_OPS,
|
2005-04-16 22:20:36 +00:00
|
|
|
};
|
|
|
|
|
2010-02-17 22:40:07 +00:00
|
|
|
static int __init dmi_pcie_pme_disable_msi(const struct dmi_system_id *d)
|
|
|
|
{
|
|
|
|
pr_notice("%s detected: will not use MSI for PCIe PME signaling\n",
|
2014-04-19 00:13:50 +00:00
|
|
|
d->ident);
|
2010-02-17 22:40:07 +00:00
|
|
|
pcie_pme_disable_msi();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-09-14 09:59:30 +00:00
|
|
|
static const struct dmi_system_id pcie_portdrv_dmi_table[] __initconst = {
|
2010-02-17 22:40:07 +00:00
|
|
|
/*
|
|
|
|
* Boxes that should not use MSI for PCIe PME signaling.
|
|
|
|
*/
|
|
|
|
{
|
|
|
|
.callback = dmi_pcie_pme_disable_msi,
|
|
|
|
.ident = "MSI Wind U-100",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR,
|
2013-11-14 18:28:18 +00:00
|
|
|
"MICRO-STAR INTERNATIONAL CO., LTD"),
|
2010-02-17 22:40:07 +00:00
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "U-100"),
|
|
|
|
},
|
|
|
|
},
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
2018-09-20 16:27:06 +00:00
|
|
|
static void __init pcie_init_services(void)
|
|
|
|
{
|
|
|
|
pcie_aer_init();
|
|
|
|
pcie_pme_init();
|
|
|
|
pcie_dpc_init();
|
|
|
|
pcie_hp_init();
|
|
|
|
}
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
static int __init pcie_portdrv_init(void)
|
|
|
|
{
|
2010-12-19 14:57:16 +00:00
|
|
|
if (pcie_ports_disabled)
|
2018-03-09 17:06:56 +00:00
|
|
|
return -EACCES;
|
2010-08-20 23:51:44 +00:00
|
|
|
|
2018-09-20 16:27:06 +00:00
|
|
|
pcie_init_services();
|
2010-02-17 22:40:07 +00:00
|
|
|
dmi_check_system(pcie_portdrv_dmi_table);
|
|
|
|
|
2018-03-09 17:06:56 +00:00
|
|
|
return pci_register_driver(&pcie_portdriver);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2016-08-22 21:59:44 +00:00
|
|
|
device_initcall(pcie_portdrv_init);
|