2005-11-04 05:58:59 +00:00
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#ifndef _ASM_POWERPC_TLBFLUSH_H
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#define _ASM_POWERPC_TLBFLUSH_H
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2007-10-29 22:46:06 +00:00
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2005-11-04 05:58:59 +00:00
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/*
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* TLB flushing:
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*
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifdef __KERNEL__
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2007-04-24 03:09:12 +00:00
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#if defined(CONFIG_4xx) || defined(CONFIG_8xx) || defined(CONFIG_FSL_BOOKE)
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/*
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* TLB flushing for software loaded TLB chips
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*
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* TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
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* flush_tlb_kernel_range are best implemented as tlbia vs
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* specific tlbie's
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*/
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2007-10-29 22:46:06 +00:00
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#include <linux/mm.h>
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extern void _tlbie(unsigned long address, unsigned int pid);
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2007-04-24 03:09:12 +00:00
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#if defined(CONFIG_40x) || defined(CONFIG_8xx)
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#define _tlbia() asm volatile ("tlbia; sync" : : : "memory")
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#else /* CONFIG_44x || CONFIG_FSL_BOOKE */
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extern void _tlbia(void);
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#endif
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2005-11-04 05:58:59 +00:00
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2007-04-24 03:09:12 +00:00
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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_tlbia();
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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2007-11-09 09:51:14 +00:00
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_tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
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2007-04-24 03:09:12 +00:00
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}
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static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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2007-11-09 09:51:14 +00:00
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_tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
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2007-04-24 03:09:12 +00:00
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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_tlbia();
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}
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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_tlbia();
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}
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#elif defined(CONFIG_PPC32)
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/*
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* TLB flushing for "classic" hash-MMMU 32-bit CPUs, 6xx, 7xx, 7xxx
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*/
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extern void _tlbie(unsigned long address);
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extern void _tlbia(void);
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extern void flush_tlb_mm(struct mm_struct *mm);
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
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extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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#else
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/*
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* TLB flushing for 64-bit has-MMU CPUs
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*/
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2005-11-04 05:58:59 +00:00
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#include <linux/percpu.h>
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#include <asm/page.h>
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#define PPC64_TLB_BATCH_NR 192
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struct ppc64_tlb_batch {
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2007-04-10 07:09:37 +00:00
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int active;
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unsigned long index;
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struct mm_struct *mm;
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real_pte_t pte[PPC64_TLB_BATCH_NR];
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unsigned long vaddr[PPC64_TLB_BATCH_NR];
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unsigned int psize;
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2007-10-11 10:37:10 +00:00
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int ssize;
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2005-11-04 05:58:59 +00:00
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};
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DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
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extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
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2007-04-10 07:09:37 +00:00
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extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge);
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#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
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static inline void arch_enter_lazy_mmu_mode(void)
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{
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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batch->active = 1;
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}
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static inline void arch_leave_lazy_mmu_mode(void)
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2005-11-04 05:58:59 +00:00
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{
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2007-04-10 07:09:37 +00:00
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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2005-11-04 05:58:59 +00:00
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if (batch->index)
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__flush_tlb_pending(batch);
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2007-04-10 07:09:37 +00:00
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batch->active = 0;
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2005-11-04 05:58:59 +00:00
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}
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2007-04-10 07:09:37 +00:00
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#define arch_flush_lazy_mmu_mode() do {} while (0)
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2005-11-07 00:06:55 +00:00
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extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
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2007-10-11 10:37:10 +00:00
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int ssize, int local);
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2005-11-07 00:06:55 +00:00
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extern void flush_hash_range(unsigned long number, int local);
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2005-11-04 05:58:59 +00:00
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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2007-04-24 03:09:12 +00:00
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unsigned long vmaddr)
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2005-11-04 05:58:59 +00:00
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{
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}
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static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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2007-04-24 03:09:12 +00:00
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unsigned long start, unsigned long end)
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2005-11-04 05:58:59 +00:00
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{
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}
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static inline void flush_tlb_kernel_range(unsigned long start,
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2007-04-24 03:09:12 +00:00
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unsigned long end)
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2005-11-04 05:58:59 +00:00
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{
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}
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[POWERPC] Rewrite IO allocation & mapping on powerpc64
This rewrites pretty much from scratch the handling of MMIO and PIO
space allocations on powerpc64. The main goals are:
- Get rid of imalloc and use more common code where possible
- Simplify the current mess so that PIO space is allocated and
mapped in a single place for PCI bridges
- Handle allocation constraints of PIO for all bridges including
hot plugged ones within the 2GB space reserved for IO ports,
so that devices on hotplugged busses will now work with drivers
that assume IO ports fit in an int.
- Cleanup and separate tracking of the ISA space in the reserved
low 64K of IO space. No ISA -> Nothing mapped there.
I booted a cell blade with IDE on PIO and MMIO and a dual G5 so
far, that's it :-)
With this patch, all allocations are done using the code in
mm/vmalloc.c, though we use the low level __get_vm_area with
explicit start/stop constraints in order to manage separate
areas for vmalloc/vmap, ioremap, and PCI IOs.
This greatly simplifies a lot of things, as you can see in the
diffstat of that patch :-)
A new pair of functions pcibios_map/unmap_io_space() now replace
all of the previous code that used to manipulate PCI IOs space.
The allocation is done at mapping time, which is now called from
scan_phb's, just before the devices are probed (instead of after,
which is by itself a bug fix). The only other caller is the PCI
hotplug code for hot adding PCI-PCI bridges (slots).
imalloc is gone, as is the "sub-allocation" thing, but I do beleive
that hotplug should still work in the sense that the space allocation
is always done by the PHB, but if you unmap a child bus of this PHB
(which seems to be possible), then the code should properly tear
down all the HPTE mappings for that area of the PHB allocated IO space.
I now always reserve the first 64K of IO space for the bridge with
the ISA bus on it. I have moved the code for tracking ISA in a separate
file which should also make it smarter if we ever are capable of
hot unplugging or re-plugging an ISA bridge.
This should have a side effect on platforms like powermac where VGA IOs
will no longer work. This is done on purpose though as they would have
worked semi-randomly before. The idea at this point is to isolate drivers
that might need to access those and fix them by providing a proper
function to obtain an offset to the legacy IOs of a given bus.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-06-04 05:15:36 +00:00
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/* Private function for use by PCI IO mapping code */
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extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
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unsigned long end);
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2005-11-04 05:58:59 +00:00
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#endif
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#endif /*__KERNEL__ */
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#endif /* _ASM_POWERPC_TLBFLUSH_H */
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